From dfb86f8f1cddc273f055e1deabe60a4ce29fb52f Mon Sep 17 00:00:00 2001 From: Litvinov Mikhail Date: Tue, 15 Jul 2025 15:38:50 +0300 Subject: [PATCH] DFCIR: added CombinifyPass, CombPipelinePassPass -> CombPipelinePass. --- .../dfcir/include/dfcir/DFCIROperations.td | 2 +- .../dfcir/include/dfcir/passes/DFCIRPasses.h | 4 +- .../dfcir/include/dfcir/passes/DFCIRPasses.td | 6 +++ .../dfcir/lib/dfcir/passes/CMakeLists.txt | 1 + .../dfcir/passes/DFCIRCombPipelinePass.cpp | 2 +- .../lib/dfcir/passes/DFCIRCombinifyPass.cpp | 41 +++++++++++++++++++ src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp | 7 +++- 7 files changed, 59 insertions(+), 4 deletions(-) create mode 100644 src/model/dfcir/lib/dfcir/passes/DFCIRCombinifyPass.cpp diff --git a/src/model/dfcir/include/dfcir/DFCIROperations.td b/src/model/dfcir/include/dfcir/DFCIROperations.td index b6a35049..de1bfd76 100644 --- a/src/model/dfcir/include/dfcir/DFCIROperations.td +++ b/src/model/dfcir/include/dfcir/DFCIROperations.td @@ -22,7 +22,7 @@ include "mlir/IR/OpBase.td" class DFCIR_Op traits = []> : Op; def KernelOp : DFCIR_Op<"kernel", - [NoRegionArguments, NoTerminator, SingleBlock]> { + [IsolatedFromAbove, NoRegionArguments, NoTerminator, SingleBlock]> { let summary = "Defines a dataflow kernel."; let arguments = (ins diff --git a/src/model/dfcir/include/dfcir/passes/DFCIRPasses.h b/src/model/dfcir/include/dfcir/passes/DFCIRPasses.h index 7e9b8c43..a03dbb76 100644 --- a/src/model/dfcir/include/dfcir/passes/DFCIRPasses.h +++ b/src/model/dfcir/include/dfcir/passes/DFCIRPasses.h @@ -72,7 +72,9 @@ namespace mlir::dfcir { using std::unique_ptr; using mlir::Pass; -unique_ptr createDFCIRCombPipelinePassPass(uint64_t stages); +unique_ptr createDFCIRCombinifyPass(); + +unique_ptr createDFCIRCombPipelinePass(uint64_t stages); unique_ptr createDFCIRToFIRRTLPass(); diff --git a/src/model/dfcir/include/dfcir/passes/DFCIRPasses.td b/src/model/dfcir/include/dfcir/passes/DFCIRPasses.td index ffb1b6e5..eb0fbde0 100644 --- a/src/model/dfcir/include/dfcir/passes/DFCIRPasses.td +++ b/src/model/dfcir/include/dfcir/passes/DFCIRPasses.td @@ -31,6 +31,12 @@ def DFCIRCombPipelinePass: Pass<"dfcir-comb-pipeline-pass", "mlir::ModuleOp"> { ]; } +def DFCIRCombinifyPass: Pass<"dfcir-combinify-pass", "mlir::dfcir::KernelOp"> { + let summary = "Explicitly sets latency '0' for every '?' latency in the kernel."; + + let constructor = "mlir::dfcir::createDFCIRCombinifyPass()"; +} + class DFCIRSchedulerPass: Pass { let options = [ diff --git a/src/model/dfcir/lib/dfcir/passes/CMakeLists.txt b/src/model/dfcir/lib/dfcir/passes/CMakeLists.txt index 4650489a..e03da9ce 100644 --- a/src/model/dfcir/lib/dfcir/passes/CMakeLists.txt +++ b/src/model/dfcir/lib/dfcir/passes/CMakeLists.txt @@ -6,6 +6,7 @@ add_compile_options(-Wno-overloaded-virtual) add_mlir_library(UtopiaDFCIRPasses ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRASAPSchedulerPass.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRCombinifyPass.cpp ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRCombPipelinePass.cpp ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRLinearSchedulerPass.cpp ${CMAKE_CURRENT_SOURCE_DIR}/DFCIRLPUtils.cpp diff --git a/src/model/dfcir/lib/dfcir/passes/DFCIRCombPipelinePass.cpp b/src/model/dfcir/lib/dfcir/passes/DFCIRCombPipelinePass.cpp index cdd254d6..0ff7b1cd 100644 --- a/src/model/dfcir/lib/dfcir/passes/DFCIRCombPipelinePass.cpp +++ b/src/model/dfcir/lib/dfcir/passes/DFCIRCombPipelinePass.cpp @@ -54,7 +54,7 @@ class DFCIRCombPipelinePass } }; -std::unique_ptr createDFCIRCombPipelinePassPass(uint64_t stages) { +std::unique_ptr createDFCIRCombPipelinePass(uint64_t stages) { DFCIRCombPipelinePassOptions options; options.stages = stages; return std::make_unique(options); diff --git a/src/model/dfcir/lib/dfcir/passes/DFCIRCombinifyPass.cpp b/src/model/dfcir/lib/dfcir/passes/DFCIRCombinifyPass.cpp new file mode 100644 index 00000000..f9840c98 --- /dev/null +++ b/src/model/dfcir/lib/dfcir/passes/DFCIRCombinifyPass.cpp @@ -0,0 +1,41 @@ +//===----------------------------------------------------------------------===// +// +// Part of the Utopia HLS Project, under the Apache License v2.0 +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2025 ISP RAS (http://www.ispras.ru) +// +//===----------------------------------------------------------------------===// + +#include "dfcir/passes/DFCIRPasses.h" +#include "dfcir/passes/DFCIRPassesUtils.h" +#include "circt/Support/LLVM.h" +#include "mlir/IR/Dialect.h" + +namespace mlir::dfcir { +#define GEN_PASS_DECL_DFCIRCOMBINIFYPASS +#define GEN_PASS_DEF_DFCIRCOMBINIFYPASS + +#include "dfcir/passes/DFCIRPasses.h.inc" + +class DFCIRCombinifyPass + : public impl::DFCIRCombinifyPassBase { + +public: + explicit DFCIRCombinifyPass() + : impl::DFCIRCombinifyPassBase() {} + + void runOnOperation() override { + KernelOp kernel = mlir::cast(getOperation()); + Block &block = kernel.getBody().front(); + + for (Scheduled sched: block.getOps()) { + sched.setLatency(0); + } + } +}; + +std::unique_ptr createDFCIRCombinifyPass() { + return std::make_unique(); +} + +} // namespace mlir::dfcir diff --git a/src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp b/src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp index 402383c8..862199c4 100644 --- a/src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp +++ b/src/model/dfcxx/lib/dfcxx/dfcir_processor.cpp @@ -74,7 +74,12 @@ bool DFCIRProcessor::convertAndPrint(mlir::ModuleOp module, pm.addPass(mlir::dfcir::createDFCIRASAPSchedulerPass(&config)); break; case CombPipelining: - pm.addPass(mlir::dfcir::createDFCIRCombPipelinePassPass(options.stages)); + if (!options.stages) { + mlir::OpPassManager &nestedDfcir = pm.nest(); + nestedDfcir.addPass(mlir::dfcir::createDFCIRCombinifyPass()); + } else { + pm.addPass(mlir::dfcir::createDFCIRCombPipelinePass(options.stages)); + } break; }