From 181e4b9193e8140bee1f69e6e28590310b12783d Mon Sep 17 00:00:00 2001 From: Ties Stuij Date: Fri, 14 Oct 2022 12:18:51 +0100 Subject: [PATCH] update Verilator-related files to compile on version 4.228 - Starting from Verilator version 4.210, the model class is an interface object. For reaching Verilog variables internal to a module this means that we need to include an extra header in cpp files that reference them (#include "Vj1a___024root.h"). And they're now part of a rootp class which is a member of the model class; we need to add an extra level of indirection. So 'top->v__DOT__ram_prog[i] = v;' becomes 'top->rootp->v__DOT__ram_prog[i] = v;'. See https://verilator.org/guide/latest/connecting.html for more words. - I don't know when these were introduced, but Verilator has become more strict about allowing assignments to wires. So 'insn' has become a reg as we assign to it inside a procedural block. And the 'wire uart0_(wr|rd) = ..' wire declarations on line 60/61 were duplicates of the module port declarations. --- j1a/verilator/j1a.v | 6 +++--- j1a/verilator/sim_main.cpp | 3 ++- j1a/verilator/vsim.cpp | 13 +++++++------ j1b/verilator/sim_main.cpp | 3 ++- j1b/verilator/vsim.cpp | 3 ++- 5 files changed, 16 insertions(+), 12 deletions(-) diff --git a/j1a/verilator/j1a.v b/j1a/verilator/j1a.v index 76ef08a..fac8cf8 100644 --- a/j1a/verilator/j1a.v +++ b/j1a/verilator/j1a.v @@ -19,7 +19,7 @@ module j1a(input wire clk, /* verilator lint_off UNUSED */ wire [12:0] code_addr; /* verilator lint_on UNUSED */ - wire [15:0] insn; + reg [15:0] insn; reg [15:0] ram_prog[0:4095] /* verilator public_flat */; always @(posedge clk) begin @@ -57,8 +57,8 @@ module j1a(input wire clk, // ###### UART ########################################## - wire uart0_wr = io_wr_ & io_addr_[12]; - wire uart0_rd = io_rd_ & io_addr_[12]; + assign uart0_wr = io_wr_ & io_addr_[12]; + assign uart0_rd = io_rd_ & io_addr_[12]; assign uart_w = dout_[7:0]; // always @(posedge clk) begin diff --git a/j1a/verilator/sim_main.cpp b/j1a/verilator/sim_main.cpp index c6c79cb..5108fa7 100644 --- a/j1a/verilator/sim_main.cpp +++ b/j1a/verilator/sim_main.cpp @@ -1,5 +1,6 @@ #include #include "Vj1a.h" +#include "Vj1a___024root.h" #include "verilated_vcd_c.h" int main(int argc, char **argv) @@ -20,7 +21,7 @@ int main(int argc, char **argv) fprintf(stderr, "invalid hex value at line %d\n", i + 1); exit(1); } - top->v__DOT__ram_prog[i] = v; + top->rootp->v__DOT__ram_prog[i] = v; } top->resetq = 0; diff --git a/j1a/verilator/vsim.cpp b/j1a/verilator/vsim.cpp index c0fd276..bcfdeba 100644 --- a/j1a/verilator/vsim.cpp +++ b/j1a/verilator/vsim.cpp @@ -1,5 +1,6 @@ #include #include "Vj1a.h" +#include "Vj1a___024root.h" #include "verilated.h" #define VCD 0 #if VCD @@ -60,7 +61,7 @@ Vj1a_init(v3 *self, PyObject *args, PyObject *kwds) fprintf(stderr, "invalid hex value at line %d\n", i + 1); exit(1); } - self->dut->v__DOT__ram_prog[i] = v; + self->dut->rootp->v__DOT__ram_prog[i] = v; } memset(self->rdepth, 0, sizeof(self->rdepth)); memset(self->ddepth, 0, sizeof(self->ddepth)); @@ -126,11 +127,11 @@ static void cycle(v3* v) dut->clk = 1; dut->eval(); - int pc = 4095 & dut->v__DOT___j1__DOT__pc; - if (dut->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc]) - v->ddepth[pc] = dut->v__DOT___j1__DOT__dstack__DOT__depth; - if (dut->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc]) - v->rdepth[pc] = dut->v__DOT___j1__DOT__rstack__DOT__depth; + int pc = 4095 & dut->rootp->v__DOT___j1__DOT__pc; + if (dut->rootp->v__DOT___j1__DOT__dstack__DOT__depth > v->ddepth[pc]) + v->ddepth[pc] = dut->rootp->v__DOT___j1__DOT__dstack__DOT__depth; + if (dut->rootp->v__DOT___j1__DOT__rstack__DOT__depth > v->rdepth[pc]) + v->rdepth[pc] = dut->rootp->v__DOT___j1__DOT__rstack__DOT__depth; } PyObject *v3_read(PyObject *_, PyObject *args) diff --git a/j1b/verilator/sim_main.cpp b/j1b/verilator/sim_main.cpp index a2eeff0..5037f49 100644 --- a/j1b/verilator/sim_main.cpp +++ b/j1b/verilator/sim_main.cpp @@ -1,5 +1,6 @@ #include #include "Vj1b.h" +#include "Vj1b___024root.h" #include "verilated_vcd_c.h" int main(int argc, char **argv) @@ -20,7 +21,7 @@ int main(int argc, char **argv) fprintf(stderr, "invalid hex value at line %d\n", i + 1); exit(1); } - top->v__DOT__ram[i] = v; + top->rootp->v__DOT__ram[i] = v; } top->resetq = 0; diff --git a/j1b/verilator/vsim.cpp b/j1b/verilator/vsim.cpp index 728bedb..c39dfb5 100644 --- a/j1b/verilator/vsim.cpp +++ b/j1b/verilator/vsim.cpp @@ -1,5 +1,6 @@ #include #include "Vj1b.h" +#include "Vj1b___024root.h" #include "verilated.h" #define VCD 0 #if VCD @@ -59,7 +60,7 @@ Vj1b_init(v3 *self, PyObject *args, PyObject *kwds) fprintf(stderr, "invalid hex value at line %d\n", i + 1); exit(1); } - self->dut->v__DOT__ram[i] = v; + self->dut->rootp->v__DOT__ram[i] = v; } return 0;