Changing Sample Size > 2

[Skosulor]

Hi,

Thanks for this awesome library and blogpost.

I'm trying to adapt the code to work with another type of SPI slave device and want to do a minimum of 32 bits transfers and up to 32 * 12 bits.

To read 4 Bytes at each sample i changed the samp_size variable to 4 inside adc_dma_init so that DLEN will be set to 4 bytes.

To confirm the results i connected MISO to power so the results should be all 1's if it works and I have connected SCLK, MOSI and CS to a logic analyzer.

I start the program with the following arguments: sudo ./rpi_adc_stream -N 10 -R 2000 -v

The result is only one transfer which is of 4 bytes instead of ten and the received buffer is all zeroes so the received bits in the single transfer is not read either. To confirm that my setup works I have changed back samp_size to 2 and as expected i get 10 transfers and the received buffer is all 1's.

I tried everything I can come up with and read the brcm2711 (RPI 4) datasheet multiple times to understand what could be the issue but I just can't get the SPI to behave differently for any transfer that is above 16 bits. I'm sure there just a setting I'm missing somewhere but cannot figure it out.

Any help is appreciated, thanks!

[jbentham]

As you may guess, I haven't tested the code with a range of sample widths, so it is difficult to say where the problem lies. For example, I note that in adc_dma_int, the .samp_size is fixed at 2, but there might be other bugs as well. Jeremy Bentham

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On 14/07/2021 12:18, Skosulor wrote: Hi, Thanks for this awesome library and blogpost. I'm trying to adapt the code to work with another type of SPI slave device and want to do a minimum of 32 bits transfers and up to 32 * 12 bits. To read 4 Bytes at each sample i changed the |samp_size| variable to 4 inside |adc_dma_init| so that DLEN will be set to 4 bytes. To confirm the results i connected MISO to power so the results should be all 1's if it works and I have connected SCLK, MOSI and CS to a logic analyzer. I start the program with the following arguments: |sudo ./rpi_adc_stream -N 10 -R 2000 -v| The result is only one transfer which is of 4 bytes instead of ten and the received buffer is all zeroes so the received bits in the single transfer is not read either. To confirm that my setup works I have changed back |samp_size| to 2 and as expected i get 10 transfers and the received buffer is all 1's. I tried everything I can come up with and read the brcm2711 (RPI 4) datasheet multiple times to understand what could be the issue but I just can't get the SPI to behave differently for any transfer that is above 16 bits. I'm sure there just a setting I'm missing somewhere but cannot figure it out. Any help is appreciated, thanks! — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#4>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ACNUSEWDL7GNQZDA6UDZQWTTXVXAZANCNFSM5ALH4DOQ>.

[Skosulor]

I have tried changing the .samp_size to 4 along with some other settings to see what happens. For now my solution is to add more control blocks for the PWM to have a very short, near zero, delay between byte transfers and then a longer transfer after each byte transfer.

[NicolasVerbeek]

Hello,

I'm probably a bit late but I came up with a solution that could be helpful to others. I believe the reason why you could not increase the SPI transfer to more than 2 bytes is related to the SPI DC register setting on line 431:

*REG32(spi_regs, SPI_DC) = (8<<24) | (1<<16) | (8<<8) | 1; // Set DMA priorities

The RDREQ bits (23:16) are set to 1, meaning a DREQ is generated whenever the RX FIFO level is greater than 1 byte. Setting this field to the number of bytes you want to transfer solves the problem for me. Not sure why it was set to 1 in the first place, since a RX DREQ is also generated if the transfer has finished. You should also modify the size of the two buffers accordingly.