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Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu into staging
ppc queue for 20250928 * Support for PowerNV11 and PPE42 CPU/Machines. * Deprecation of Power8E and Power8NVL * Decodetree patches for some floating-point instructions * Minor bug fixes, improvements in ppc/spapr/xive/xics. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEa4EM1tK+EPOIPSFCRUTplPnWj7sFAmjZgYQACgkQRUTplPnW # j7uNJQ/8Cbr3xqyCyyqL+MM+Ze1PbXe4xSgdg13A1sNU3IHTffB77DCQVOxjudUS # uo+XHVFssc4SKDZYjEzXFnYpzRpbZzfcuhG4kgn9QQ3VyKP+2xe6kWLleDbB6ds1 # e9ZAW6Ryk4R3ZFLnZzGfEdltliaoIn6zy4R25oJfJUgIRt0Xz++GBxll+Tdr8Exy # qstvvyyjeTiIS3kA1zk6fbhDRJKKBsA0L1G1Pk6AuTMKa1RRTCniA36idnGVFAuY # ef8WCEQYQS0do9Ytai06Tp1QNRVMG2y+AsKbSQRMi92lFfn+qhvA29OJd5TNvXtp # LNiIfXHo3jLjGBUP13iVN8b8udWdis9BayvA/OwDaKWgononEHb9nqJgzVJR4n7t # DxxUxcSCiEXOpObtklrKhi1nDt16nXPZ/bnnreMSWzxHBZK1My7qnI3S0hA7c11z # YgssB5wJbRaETaEVzQfWfAcSaPpXBzBEXOAJcbd+Ni6w9SxXz2OrhckTOvfrXpmI # XQ1KFUCkmTtXF1qB+oEihlrvG2qjdGuleRZdyiktaM2psBFgN/2gHl3S+JjL9kiY # 9FdBffr/2K604l7EQkAYWixe2WMMsjHVHpuxJ7opG7MMSXJZq9cXKIK+tbkSNoRO # Ia6Qr6eWJWjFF3y4OZCbYAOVU77ez6lo7kRj0e99fOjxfI+UuWU= # =Fjdq # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Sep 2025 11:42:12 AM PDT # gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB # gpg: Good signature from "Harsh Prateek Bora <harsh.prateek.bora@gmail.com>" [undefined] # gpg: aka "Harsh Prateek Bora <harshpb@linux.ibm.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB * tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27 commits) target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask target/ppc: Deprecate Power8E and Power8NVL target/ppc: Introduce macro for deprecating PowerPC CPUs target/ppc: Move remaining floating-point move instructions to decodetree. target/ppc: Move floating-point move instructions to decodetree. target/ppc: Move floating-point compare instructions to decodetree. target/ppc: Move floating-point rounding and conversion instructions to decodetree. ppc/xive2: Fix integer overflow warning in xive2_redistribute() ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided hw/intc/xics: Add missing call to register vmstate_icp_server tests/functional: Add test for IBM PPE42 instructions hw/ppc: Add a test machine for the IBM PPE42 CPU hw/ppc: Support for an IBM PPE42 CPU decrementer target/ppc: Add IBM PPE42 special instructions target/ppc: Support for IBM PPE42 MMU target/ppc: Add IBM PPE42 exception model target/ppc: IBM PPE42 exception flags and regs target/ppc: Add IBM PPE42 family of processors target/ppc: IBM PPE42 general regs and flags tests/powernv: Add PowerNV test for Power11 ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 parents 4975b64 + 6c51df5 commit 9b16ede

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‎MAINTAINERS‎

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@@ -1530,6 +1530,13 @@ F: include/hw/pci-host/grackle.h
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F: pc-bios/qemu_vga.ndrv
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F: tests/functional/ppc/test_mac.py
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PPE42
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M: Glenn Miles <milesg@linux.ibm.com>
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L: qemu-ppc@nongnu.org
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S: Odd Fixes
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F: hw/ppc/ppe42_machine.c
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F: tests/functional/ppc/test_ppe42.py
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PReP
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M: Hervé Poussineau <hpoussin@reactos.org>
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L: qemu-ppc@nongnu.org

‎docs/about/deprecated.rst‎

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@@ -253,6 +253,15 @@ embedded 405 for power management (OCC) and other internal tasks, it
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is theoretically possible to use QEMU to model them. Let's keep the
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CPU implementation for a while before removing all support.
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Power8E and Power8NVL CPUs and corresponding Pnv chips (since 10.1)
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'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
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The Power8E and Power8NVL variants of Power8 are not really useful anymore
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in qemu, and are old and unmaintained now.
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The CPUs as well as corresponding Power8NVL and Power8E PnvChips will also
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be considered deprecated.
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System emulator machines
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------------------------
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‎docs/system/ppc/powernv.rst‎

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@@ -1,5 +1,5 @@
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PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``)
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==================================================================
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PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``, ``powernv11``)
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================================================================================
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PowerNV (as Non-Virtualized) is the "bare metal" platform using the
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OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
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Supported devices
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-----------------
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* Multi processor support for POWER8, POWER8NVL and POWER9.
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* Multi processor support for POWER8, POWER8NVL, POWER9, Power10 and Power11.
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* XSCOM, serial communication sideband bus to configure chiplets.
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* Simple LPC Controller.
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* Processor Service Interface (PSI) Controller.
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* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10).
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* Interrupt Controller, XICS (POWER8) and XIVE (POWER9) and XIVE2 (Power10 &
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Power11).
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* POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
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* Simple OCC is an on-chip micro-controller used for power management tasks.
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* iBT device to handle BMC communication, with the internal BMC simulator

‎hw/intc/pnv_xive2.c‎

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@@ -110,8 +110,8 @@ static PnvXive2 *pnv_xive2_get_remote(uint32_t vsd_type, hwaddr fwd_addr)
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int i;
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for (i = 0; i < pnv->num_chips; i++) {
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Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
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PnvXive2 *xive = &chip10->xive;
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PnvChipClass *k = PNV_CHIP_GET_CLASS(pnv->chips[i]);
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PnvXive2 *xive = PNV_XIVE2(k->intc_get(pnv->chips[i]));
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/*
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* Is this the XIVE matching the forwarded VSD address is for this

‎hw/intc/xics.c‎

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@@ -335,6 +335,8 @@ static void icp_realize(DeviceState *dev, Error **errp)
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return;
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}
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}
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vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
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}
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static void icp_unrealize(DeviceState *dev)

‎hw/intc/xive2.c‎

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}
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}
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static uint32_t xive2_nvgc_get_idx(uint32_t nvp_idx, uint8_t group)
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{
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uint32_t nvgc_idx;
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if (group > 0) {
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nvgc_idx = (nvp_idx & (0xffffffffULL << group)) |
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((1 << (group - 1)) - 1);
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} else {
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nvgc_idx = nvp_idx;
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}
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return nvgc_idx;
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}
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static uint8_t xive2_nvgc_get_blk(uint8_t nvp_blk, uint8_t crowd)
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{
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uint8_t nvgc_blk;
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if (crowd > 0) {
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crowd = (crowd == 3) ? 4 : crowd;
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nvgc_blk = (nvp_blk & (0xffffffffULL << crowd)) |
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((1 << (crowd - 1)) - 1);
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} else {
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nvgc_blk = nvp_blk;
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}
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return nvgc_blk;
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}
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uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr,
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bool crowd,
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uint8_t blk, uint32_t idx,
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trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx);
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/* convert crowd/group to blk/idx */
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if (group > 0) {
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nvgc_idx = (nvp_idx & (0xffffffff << group)) |
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((1 << (group - 1)) - 1);
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} else {
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nvgc_idx = nvp_idx;
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}
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if (crowd > 0) {
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crowd = (crowd == 3) ? 4 : crowd;
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nvgc_blk = (nvp_blk & (0xffffffff << crowd)) |
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((1 << (crowd - 1)) - 1);
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} else {
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nvgc_blk = nvp_blk;
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}
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nvgc_idx = xive2_nvgc_get_idx(nvp_idx, group);
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nvgc_blk = xive2_nvgc_get_blk(nvp_blk, crowd);
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/* Use blk/idx to retrieve the NVGC */
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if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) {

‎hw/ppc/Kconfig‎

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@@ -44,6 +44,11 @@ config POWERNV
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select SSI_M25P80
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select PNV_SPI
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config PPC405
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bool
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default y
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depends on PPC
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config PPC440
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bool
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default y

‎hw/ppc/meson.build‎

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@@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
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'pnv_n1_chiplet.c',
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))
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# PowerPC 4xx boards
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ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
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'ppe42_machine.c'))
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ppc_ss.add(when: 'CONFIG_PPC440', if_true: files(
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'ppc440_bamboo.c',
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'ppc440_uc.c'))

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