Added fix for ethernet phy reset pin. Updatd README

Author: RomanKSundance

board/microchip/polarberry/program_all.sh

@@ -2,9 +2,9 @@
 
 source ./FLASH_CONFIG.CONF
 
-./Program_HSS_to_eNVM.sh
-./Program_UBOOT_to_eMMC.sh
+./program_hss.sh
+./program_uboot.sh
 
 echo "reset" > $UART_DEVICE
 
-./Program_LINUX_to_eMMC.sh
+./program_linux.sh

board/microchip/som1-soc/README

@@ -1,10 +1,8 @@
-After that in the directory "/home/promwad/microchip_buildroot/buildroot-external-microchip/board/microchip/polarberry" you can find script for board flashing. 
-
 There are 4 scipts:
-1) Program_HSS_to_eNVM.sh
-2) Program_UBOOT_to_eMMC.sh
-3) Program_LINUX_to_eNVM.sh
-4) Program_ALL_to_Polarberry.sh
+1) program_hss.sh
+2) Program_uboot.sh
+3) Program_linux.sh
+4) Program_all.sh
 
 and settings file: FLASH_CONFIG.CONF
 
@@ -37,11 +35,21 @@ IMAGE_NAME		- here you need to set file name with LINUX image that is placed on
                           (default value is "fitimage_polarberry.itb", and this file is built by buildroot and placed in "output/images" directory)
 
 
-To start building images via buildroot you need to run this command in buildrood sources:
-1) "make sundancedsp_polarberry_defconfig  BR2_EXTERNAL=../buildroot-external-microchip"
-   (where BR2_EXTERNAL shall point to the mbuildroot microsemi sources).
+To start building images via buildroot you need:
+
+1) Microchip Softconsole shall be installed (Microchip-SoftConsole-v2022.2-RISC-V-747-linux-x64-installer.run)
+2) Microchip Program Debug tools shall be installed (Program_Debug_PolarFire_v2023.2_SP1.bin)
+
+3) run this command in buildrood sources:
+
+3.1)  "make sundancedsp_polarberry_defconfig  BR2_EXTERNAL=../buildroot-external-microchip"
+   (where BR2_EXTERNAL shall point to the buildroot microsemi sources).
+
+3.2) "make"
+
+
+
 
-2) "make"
     Building will take time. Succesfull building will finish like this:
 
 FIT description: Linux fitImage for Polaberry

board/microchip/som1-soc/uboot/uboot_som1-soc.dts

@@ -183,11 +183,6 @@
 	phy-mode = "sgmii";
 	phy-handle = <&phy5>;
 
-/*	phy4: ethernet-phy@4 {
-		reg = <4>;
-		ti,fifo-depth = <0x01>;
-	};
-*/
 	phy5: ethernet-phy@5 {
 		reg = <5>;
 		ti,fifo-depth = <0x01>;

configs/sundancedsp_polarberry_defconfig

@@ -52,8 +52,8 @@ BR2_PACKAGE_HOST_MTOOLS=y
 BR2_PACKAGE_HART_SOFTWARE_SERVICES=y
 BR2_PACKAGE_HART_SOFTWARE_SERVICES_CONFIG="boards/polarberry/def_config"
 BR2_PACKAGE_HART_SOFTWARE_SERVICES_BOARD="polarberry"
-BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE="MPFS250T_ES"
-BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE="FCVG484"OA
+BR2_PACKAGE_HART_SOFTWARE_SERVICES_DIE="MPFS250T"
+BR2_PACKAGE_HART_SOFTWARE_SERVICES_PACKAGE="FCVG484"
 BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR=y
 BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_CFG="$(BR2_EXTERNAL_MCHP_PATH)/board/microchip/polarberry/payload-config.yaml"
 BR2_PACKAGE_HOST_HSS_PAYLOAD_GENERATOR_SRC="output/images/u-boot.bin"

package/hart-software-services/hss_som1-soc.patch renamed to package/hart-software-services/001-HSS_SOM1-SOC.patch

@@ -0,0 +1,25 @@
+diff -ruN a/boards/som1-soc/hss_board_init.c b/boards/som1-soc/hss_board_init.c
+--- a/boards/som1-soc/hss_board_init.c	2024-01-10 04:21:31.283722794 -0800
++++ b/boards/som1-soc/hss_board_init.c	2024-01-10 04:08:02.513198414 -0800
+@@ -23,6 +23,8 @@
+ #include "ssmb_ipi.h"
+ #include "hss_registry.h"
+ 
++#include "mss_gpio.h"
++
+ #ifndef __IO
+ #  define __IO volatile
+ #endif
+@@ -79,6 +81,12 @@
+ 
+ bool HSS_BoardLateInit(void)
+ {
++    mHSS_PUTS("Clear (set to HIGH\1) Ethernet PHY RESET: GPIO0_LO, PIN13\n");
++
++    MSS_GPIO_init(GPIO0_LO);
++    MSS_GPIO_config(GPIO0_LO, MSS_GPIO_13, MSS_GPIO_OUTPUT_MODE);
++    MSS_GPIO_set_outputs(GPIO0_LO, MSS_GPIO_13_MASK);
++
+     return true;
+ }
+