diff --git a/app/rpi-vpu-bootload/bootloader.c b/app/rpi-vpu-bootload/bootloader.c new file mode 100644 index 0000000000..d63c317433 --- /dev/null +++ b/app/rpi-vpu-bootload/bootloader.c @@ -0,0 +1,19 @@ +#include +#include +#include +#include + +static void bootloader_init(const struct app_descriptor *app) { + printf("bootloader init\n"); +} + +static void bootloader_entry(const struct app_descriptor *app, void *args) { + printf("bootloader entry\n\n"); + otp_pretty_print(); + //sdram_init(); +} + +APP_START(bootloader) + .init = bootloader_init, + .entry = bootloader_entry, +APP_END diff --git a/app/rpi-vpu-bootload/rules.mk b/app/rpi-vpu-bootload/rules.mk new file mode 100644 index 0000000000..5a254d42f4 --- /dev/null +++ b/app/rpi-vpu-bootload/rules.mk @@ -0,0 +1,12 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += \ + platform/bcm28xx/rpi-ddr2 \ + platform/bcm28xx/otp \ + + +MODULE_SRCS += $(LOCAL_DIR)/bootloader.c + +include make/module.mk diff --git a/app/vc4-stage1/rules.mk b/app/vc4-stage1/rules.mk new file mode 100644 index 0000000000..a0310d7977 --- /dev/null +++ b/app/vc4-stage1/rules.mk @@ -0,0 +1,15 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += \ + lib/partition \ + lib/fs \ + lib/fs/ext2 \ + lib/elf \ + +MODULE_SRCS += \ + $(LOCAL_DIR)/stage1.c \ + +include make/module.mk + diff --git a/app/vc4-stage1/stage1.c b/app/vc4-stage1/stage1.c new file mode 100644 index 0000000000..fa0774652e --- /dev/null +++ b/app/vc4-stage1/stage1.c @@ -0,0 +1,212 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define UNCACHED_RAM 0xc0000000 +#define MB (1024*1024) + +static void stage2_dram_init(uint level) { + sdram_init(); + uint32_t start = UNCACHED_RAM | (1 * MB); + uint32_t length = 10 * MB; + novm_add_arena("dram", start, length); +} + +LK_INIT_HOOK(stage1, &stage2_dram_init, LK_INIT_LEVEL_PLATFORM_EARLY + 1); + +static ssize_t fs_read_wrapper(struct elf_handle *handle, void *buf, uint64_t offset, size_t len) { + return fs_read_file(handle->read_hook_arg, buf, offset, len); +} + +static wait_queue_t waiter; + +static int waker_entry(wait_queue_t *waiter) { + char c; + int ret = platform_dgetc(&c, true); + if (ret) { + puts("failed to getc\n"); + return 0; + } + if (c == 'X') { + printf("got char 0x%x\n", c); + THREAD_LOCK(state); + wait_queue_wake_all(waiter, false, c); + THREAD_UNLOCK(state); + } + return 0; +} + +static void *load_and_run_elf(elf_handle_t *stage2_elf) { + int ret = elf_load(stage2_elf); + if (ret) { + printf("failed to load elf: %d\n", ret); + return; + } + elf_close_handle(stage2_elf); + void *entry = stage2_elf->entry; + free(stage2_elf); + return entry; +} + +static void load_stage2(void) { + int ret; + + bdev_t *sd = rpi_sdhost_init(); + partition_publish("sdhost", 0); + //fs_mount("/boot", "fat32", "sdhostp0"); + ret = fs_mount("/root", "ext2", "sdhostp1"); + if (ret) { + printf("mount failure: %d\n", ret); + return; + } + filehandle *stage2; + ret = fs_open_file("/root/lk.elf", &stage2); + if (ret) { + printf("open failed: %d\n", ret); + return; + } + elf_handle_t *stage2_elf = malloc(sizeof(elf_handle_t)); + ret = elf_open_handle(stage2_elf, fs_read_wrapper, stage2, false); + if (ret) { + printf("failed to elf open: %d\n", ret); + return; + } + void *entry = load_and_run_elf(stage2_elf); + fs_close_file(stage2); + arch_chain_load(entry, 0, 0, 0, 0); +} + +struct xmodem_packet { + uint8_t magic; + uint8_t block_num; + uint8_t block_num_invert; + uint8_t payload[128]; + uint8_t checksum; +} __attribute__((packed)); + +//static_assert(sizeof(struct xmodem_packet) == 132, "xmodem packet malformed"); + +static ssize_t read_repeat(io_handle_t *in, void *buf, ssize_t len) { + ssize_t total_read = 0; + ssize_t ret; + while ((ret = io_read(in, buf, len)) > 0) { + //printf("0X%02x %d\n\n", ((uint8_t*)buf)[0], ret); + len -= ret; + total_read += ret; + buf += ret; + if (len <= 0) return total_read; + } + return -1; +} + +static void xmodem_receive(void) { + size_t capacity = 2 * MB; + void *buffer = malloc(capacity); + size_t used = 0; + struct xmodem_packet *packet = malloc(sizeof(struct xmodem_packet)); + ssize_t ret; + int blockNr = 1; + bool success = false; + + io_write(&console_io, "\x15", 1); + while ((ret = io_read(&console_io, packet, 1)) == 1) { + if (packet->magic == 4) { + puts("R: EOF!"); + success = true; + break; + } + ret = read_repeat(&console_io, &packet->block_num, sizeof(struct xmodem_packet) - 1); + if (ret != (sizeof(struct xmodem_packet)-1)) { + puts("read error"); + break; + } + uint8_t checksum = 0; + for (int i=0; i<128; i++) { + checksum += packet->payload[i]; + } + bool fail = true; + if (packet->checksum == checksum) { + if (packet->block_num_invert == (255 - packet->block_num)) { + if (packet->block_num == (blockNr & 0xff)) { + memcpy(buffer + (128 * (blockNr-1)), packet->payload, 128); + blockNr++; + io_write(&console_io, "\6", 1); + fail = false; + } else if (packet->block_num == ((blockNr - 1) & 0xff)) { // ack was lost, just re-ack + io_write(&console_io, "\6", 1); + } else { + io_write(&console_io, "\x15", 1); + } + } else { // block_invert wrong + io_write(&console_io, "\x15", 1); + } + } else { // wrong checksum + io_write(&console_io, "\x15", 1); + } + if (fail) printf("got packet: %d %d %d %d/%d\n", packet->magic, packet->block_num, packet->block_num_invert, packet->checksum, checksum); + } + printf("final ret was %ld\n", ret); + free(packet); + if (success) { + elf_handle_t *stage2_elf = malloc(sizeof(elf_handle_t)); + ret = elf_open_handle_memory(stage2_elf, buffer, blockNr*128); + if (ret) { + printf("failed to elf open: %d\n", ret); + return; + } + void *entry = load_and_run_elf(stage2_elf); + free(buffer); + arch_chain_load(entry, 0, 0, 0, 0); + return; + } + free(buffer); +} + + +static void stage2_init(const struct app_descriptor *app) { + puts("stage2_init"); +} + +static void stage2_entry(const struct app_descriptor *app, void *args) { + puts("stage2 entry\n"); + + puts("press X to stop autoboot and go into xmodem mode..."); + wait_queue_init(&waiter); + + thread_t *waker = thread_create("waker", waker_entry, &waiter, DEFAULT_PRIORITY, ARCH_DEFAULT_STACK_SIZE); + thread_resume(waker); + + THREAD_LOCK(state); + int ret = wait_queue_block(&waiter, 100000); + THREAD_UNLOCK(state); + + printf("wait result: %d\n", ret); + + if (ret == 'X') { + puts("going into xmodem mode"); + uint32_t rsts = *REG32(PM_RSTS); + printf("%x\n", rsts); + xmodem_receive(); + } else { + load_stage2(); + } +} + +APP_START(stage2) + .init = stage2_init, + .entry = stage2_entry, +APP_END diff --git a/app/vc4-stage2/rules.mk b/app/vc4-stage2/rules.mk new file mode 100644 index 0000000000..b0904c2858 --- /dev/null +++ b/app/vc4-stage2/rules.mk @@ -0,0 +1,19 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += \ + lib/partition \ + lib/fs \ + lib/fs/fat32 \ + lib/fs/ext2 \ + lib/debugcommands \ + app/stringtests \ + platform/bcm28xx/dpi \ + app/tests \ + +MODULE_SRCS += \ + $(LOCAL_DIR)/stage2.c \ + +include make/module.mk + diff --git a/app/vc4-stage2/stage2.c b/app/vc4-stage2/stage2.c new file mode 100644 index 0000000000..0b3631915f --- /dev/null +++ b/app/vc4-stage2/stage2.c @@ -0,0 +1,26 @@ +#include +#include +#include +#include +#include +#include + +static void stage2_init(const struct app_descriptor *app) { + printf("stage2 init\n"); + bdev_t *sd = rpi_sdhost_init(); + partition_publish("sdhost", 0); + //fs_mount("/boot", "fat32", "sdhostp0"); + fs_mount("/root", "ext2", "sdhostp0"); +} + +static void stage2_entry(const struct app_descriptor *app, void *args) { + printf("stage2 entry\n"); + cmd_dpi_start(0, NULL); + cmd_dpi_move(0, NULL); + //cmd_dpi_count(0, NULL); +} + +APP_START(stage2) + .init = stage2_init, + .entry = stage2_entry, +APP_END diff --git a/arch/arm/arm/arch.c b/arch/arm/arm/arch.c index ce955c015f..4241706a3a 100644 --- a/arch/arm/arm/arch.c +++ b/arch/arm/arm/arch.c @@ -242,7 +242,7 @@ static void arm_basic_setup(void) { #endif /* set the vector base to our exception vectors so we don't need to double map at 0 */ -#if ARM_ISA_ARMV7 +#if ARM_ISA_ARMV7 || ARM_ISA_ARMV6K arm_write_vbar(KERNEL_BASE + KERNEL_LOAD_OFFSET); #endif } diff --git a/arch/arm/arm/ops.S b/arch/arm/arm/ops.S index ca99f44535..4809bdbf55 100644 --- a/arch/arm/arm/ops.S +++ b/arch/arm/arm/ops.S @@ -8,6 +8,14 @@ #include #include +.macro DMB + mcr p15, 0, r0, c7, c10, 5 +.endm + +.macro DSB + mcr p15, 0, r0, c7, c10, 4 +.endm + .text /* void _arch_enable_ints(void); */ diff --git a/arch/arm/arm/start.S b/arch/arm/arm/start.S index b78fcc2b94..1a088a915e 100644 --- a/arch/arm/arm/start.S +++ b/arch/arm/arm/start.S @@ -31,6 +31,14 @@ platform_reset: .globl arm_reset arm_reset: +#if ARM_WITH_HYP + /* if in HYP mode, move to SVC */ + mrs r12, cpsr + and r12, r12, #0x1f + cmp r12, #0x1a + bleq arm32_hyp_to_svc +#endif // ARM_WITH_HYP + /* do some early cpu setup */ mrc p15, 0, r12, c1, c0, 0 /* i/d cache disable, mmu disabled */ @@ -204,7 +212,7 @@ arm_reset: /* set up the mmu */ bl .Lmmu_setup -#endif // WITH_KERNEL_VM +#endif // ARM_WITH_MMU /* at this point we're running at our final location in virtual memory (if enabled) */ .Lstack_setup: @@ -281,7 +289,7 @@ arm_reset: orr r12, r4, #MMU_TTBRx_FLAGS /* Write ttbr with phys addr of the translation table */ - mcr p15, 0, r12, c2, c0, 0 + mcr p15, 0, r12, c2, c0, 0 // TTBR0 isb /* Write DACR */ @@ -310,7 +318,7 @@ arm_reset: /* Switch to main page table */ mcr p15, 0, r8, c2, c0, 0 isb -#endif +#endif // MMU_WITH_TRAMPOLINE /* Invalidate TLB. The value in r0 is ignored */ mcr p15, 0, r0, c8, c7, 0 @@ -320,7 +328,7 @@ arm_reset: /* assume lr was in physical memory, adjust it before returning */ sub lr, r11 bx lr -#endif +#endif // WITH_KERNEL_VM #if WITH_SMP /* secondary cpu entry point */ @@ -387,11 +395,11 @@ FUNCTION(arm_secondary_setup) /* Calculate pagetable physical addresses */ ldr r4, =tt_trampoline /* r4 = tt_trampoline vaddr */ add r4, r4, r11 /* r4 = tt_trampoline paddr */ -#endif +#endif // MMU_WITH_TRAMPOLINE /* set up the mmu on this cpu and switch to virtual memory */ bl .Lmmu_setup -#endif +#endif // WITH_KERNEL_VM /* stay in supervisor and call into arm arch code to continue setup */ mov r0, r5 @@ -401,7 +409,17 @@ FUNCTION(arm_secondary_setup) unsupported_cpu_trap: wfe b unsupported_cpu_trap -#endif +#endif // WITH_SMP + +#if ARM_WITH_HYP +arm32_hyp_to_svc: + mrs r12, cpsr + bic r12, #0x1f // clear mode bits + orr r12, r12, #0x13 // set mode bits to SVC + msr SPSR_hyp, r12 + msr ELR_hyp, lr + eret // "restore" the mode, and return +#endif // ARM_WITH_HYP .ltorg @@ -410,7 +428,7 @@ unsupported_cpu_trap: .align 14 DATA(tt_trampoline) .skip 16384 -#endif +#endif // WITH_KERNEL_VM && MMU_WITH_TRAMPOLINE .data .align 2 diff --git a/arch/arm/rules.mk b/arch/arm/rules.mk index ba8993fb28..2f4f002aea 100644 --- a/arch/arm/rules.mk +++ b/arch/arm/rules.mk @@ -103,7 +103,9 @@ GLOBAL_DEFINES += \ ARM_WITH_NEON=1 \ ARM_WITH_THUMB=1 \ ARM_WITH_THUMB2=1 \ - ARM_WITH_CACHE=1 + ARM_WITH_CACHE=1 \ + ARM_WITH_FIQ=1 \ + ARM_WITH_HYP=1 HANDLED_CORE := true endif ifeq ($(ARM_CPU),cortex-a15) @@ -173,14 +175,20 @@ GLOBAL_DEFINES += \ HANDLED_CORE := true endif ifeq ($(ARM_CPU),arm1176jzf-s) +WITH_KERNEL_VM = 0 GLOBAL_DEFINES += \ ARM_WITH_CP15=1 \ - ARM_WITH_MMU=1 \ + ARM_WITH_MMU=0 \ ARM_ISA_ARMv6=1 \ - ARM_WITH_VFP=1 \ + ARM_ISA_ARMV6K=1 \ ARM_WITH_THUMB=1 \ ARM_WITH_CACHE=1 \ + ARM_WITH_FIQ=1 \ ARM_CPU_ARM1136=1 +ifneq ($(ARM_WITHOUT_VFP_NEON),true) + GLOBAL_DEFINES += \ + ARM_WITH_VFP=1 +endif HANDLED_CORE := true endif ifeq ($(ARM_CPU),cortex-r4f) diff --git a/arch/arm/toolchain.mk b/arch/arm/toolchain.mk index b42e9c922b..71632a7742 100644 --- a/arch/arm/toolchain.mk +++ b/arch/arm/toolchain.mk @@ -103,7 +103,7 @@ ifeq ($(ARM_CPU),arm1136j-s) ARCH_arm_COMPILEFLAGS += -mcpu=$(ARM_CPU) endif ifeq ($(ARM_CPU),arm1176jzf-s) -ARCH_arm_COMPILEFLAGS += -mcpu=$(ARM_CPU) +ARCH_arm_COMPILEFLAGS += -mcpu=$(ARM_CPU) -mfpu=vfp -march=armv6zk endif ifeq ($(ARM_CPU),cortex-r4f) ARCH_arm_COMPILEFLAGS += -march=armv7-r diff --git a/arch/vpu/arch.c b/arch/vpu/arch.c new file mode 100644 index 0000000000..04854ce611 --- /dev/null +++ b/arch/vpu/arch.c @@ -0,0 +1,130 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int cmd_boot_other_core(int argc, const cmd_args *argv); +static int cmd_testit(int argc, const cmd_args *argv); +static int cmd_jitter(int argc, const cmd_args *argv); + +static char core2_stack[512]; +uint32_t core2_stack_top = 0; + +STATIC_COMMAND_START +STATIC_COMMAND("boot_other_core", "boot the 2nd vpu core", &cmd_boot_other_core) +STATIC_COMMAND("testit", "do some asm tests", &cmd_testit) +//STATIC_COMMAND("jitter", "jitter test", &cmd_jitter) +STATIC_COMMAND_END(arch); + +extern uint8_t _fbss; +extern uint8_t _ebss; + +void zero_bss(void) { + bzero(&_fbss, &_ebss - &_fbss); +} + +void arch_early_init(void) { + uint32_t r28, sp, sr; + __asm__ volatile ("mov %0, r28" : "=r"(r28)); + __asm__ volatile ("mov %0, sp" : "=r"(sp)); + __asm__ volatile ("mov %0, sr" : "=r"(sr)); + //dprintf(INFO, "arch_early_init\nr28: 0x%x\nsp: 0x%x\nsr: 0x%x\n", r28, sp, sr); +} + +void arch_init(void) { + uint32_t r28, sp, cpuid; + __asm__ volatile ("mov %0, r28" : "=r"(r28)); + __asm__ volatile ("mov %0, sp" : "=r"(sp)); + __asm__ volatile ("version %0" : "=r"(cpuid)); + dprintf(INFO, "arch_init\nr28: 0x%x\nsp: 0x%x\ncpuid: %x\n", r28, sp, cpuid); +} + +void arch_idle(void) { + asm volatile("sleep"); +} + +void arch_chain_load(void *entry, ulong arg0, ulong arg1, ulong arg2, ulong arg3) { + puts("flushing uart tx and chainloading...\n"); + uart_flush_tx(0); + __asm__ volatile ("mov r0, %0\nmov r1, %1\nmov r2, %2\nmov r3, %3\nbl %4": + : "r"(arg0) + , "r"(arg1) + , "r"(arg2) + , "r"(arg3) + , "r"(entry)); + panic("chainload somehow returned"); +} + +void arch_sync_cache_range(addr_t start, size_t len) { +} + +void core2_start(void); + +volatile uint32_t foo; + +static int cmd_boot_other_core(int argc, const cmd_args *argv) { + core2_stack_top = (uint32_t)((core2_stack + sizeof(core2_stack)) - 4); + //*REG32(A2W_PLLC_CORE1) = A2W_PASSWORD | 6; // 3ghz/6 == 500mhz + *REG32(IC1_WAKEUP) = (uint32_t)(&core2_start); + for (int i=0; i<20; i++) { + udelay(2); + printf("%d %d\n", i, foo); + } + return 0; +} + +void core2_entry(void) { + dprintf(INFO, "core2 says hello\n"); + for (int i=0; i<300; i++) { + udelay(1); + foo = i; + } + for (;;); +} + +void testit(uint32_t *, uint32_t, uint32_t, uint32_t, uint32_t); + +static int cmd_testit(int argc, const cmd_args *argv) { + uint32_t target[4]; + testit(target, 0x11, 0x22, 0x33, 0x44); + printf("%x %x %x %x\n", target[0], target[1], target[2], target[3]); + return 0; +} + +void toggle18(void); + +static int cmd_jitter(int argc, const cmd_args *argv) { + //__asm__ volatile("di"); + gpio_config(18, 1); + for (int i=0; i < 10000000; i++) { + toggle18(); + //gpio_set(18,1); + //gpio_set(18,0); + } + //__asm__ volatile("ei"); + return 0; +} + +int vc4_atomic_add(volatile int *ptr, int val) { + // TODO + //spin_lock_saved_state_t state; + //arch_interrupt_save(&state, SPIN_LOCK_FLAG_INTERRUPTS); + THREAD_LOCK(state); + int old = *ptr; + *ptr += val; + //arch_interrupt_restore(&state, SPIN_LOCK_FLAG_INTERRUPTS); + THREAD_UNLOCK(state); + return old; +} + +void arch_clean_cache_range(addr_t start, size_t len) { + // TODO +} diff --git a/arch/vpu/include/arch/arch_ops.h b/arch/vpu/include/arch/arch_ops.h new file mode 100644 index 0000000000..0828a2e921 --- /dev/null +++ b/arch/vpu/include/arch/arch_ops.h @@ -0,0 +1,60 @@ +#pragma once + +#include +#include + +static inline void arch_enable_ints(void) { + __asm__ volatile("ei"); +} + +static inline void arch_disable_ints(void) { + __asm__ volatile("di"); +} + +static inline bool arch_ints_disabled(void) { + uint32_t state; + + __asm__ volatile("mov %0, sr": "=r" (state)); + return !(state & 0x40000000); +} + +int vc4_atomic_add(volatile int *ptr, int val); + +static inline int atomic_add(volatile int *ptr, int val) { + return vc4_atomic_add(ptr, val); +} + +static inline int atomic_or(volatile int *ptr, int val) { + return __atomic_fetch_or(ptr, val, __ATOMIC_RELAXED); +} + +static inline int atomic_and(volatile int *ptr, int val) { + return __atomic_fetch_and(ptr, val, __ATOMIC_RELAXED); +} + +static inline int atomic_swap(volatile int *ptr, int val) { + return __atomic_exchange_n(ptr, val, __ATOMIC_RELAXED); +} + +// todo, use global register instead +// register struct thread *current __asm__("r29"); + +static inline struct thread *get_current_thread(void) { + struct thread *thread_reg; + __asm__ volatile("mov %0, r29" : "=r"(thread_reg)); + return thread_reg; +} + +static inline void set_current_thread(struct thread *t) { + __asm__ volatile ("mov r29, %0" : : "r"(t)); +} + +static inline uint32_t arch_cycle_count(void) { return 0; } + +static inline uint arch_curr_cpu_num(void) { + uint32_t cpuid; + __asm__("version %0" : "=r"(cpuid)); + // TODO, one of the bits in the cpuid is the cpu#, dont remember which one + // a pdf for an older ARC model says the cpuid contains a 16bit vendor id, 8bit coreid, and 8bit cpuid + return 0; +} diff --git a/arch/vpu/include/arch/arch_thread.h b/arch/vpu/include/arch/arch_thread.h new file mode 100644 index 0000000000..5e288a88d3 --- /dev/null +++ b/arch/vpu/include/arch/arch_thread.h @@ -0,0 +1,8 @@ +#pragma once + +#include + +struct arch_thread { + uint32_t sp; + uint32_t sr; +}; diff --git a/arch/vpu/include/arch/aspace.h b/arch/vpu/include/arch/aspace.h new file mode 100644 index 0000000000..e8d26ff0d2 --- /dev/null +++ b/arch/vpu/include/arch/aspace.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2016 Travis Geiselbrecht + * + * Use of this source code is governed by a MIT-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/MIT + */ +#pragma once + +#include + +__BEGIN_CDECLS + +struct arch_aspace { + // nothing for now, does not support address spaces other than the kernel +}; + +__END_CDECLS + diff --git a/arch/vpu/include/arch/defines.h b/arch/vpu/include/arch/defines.h new file mode 100644 index 0000000000..999b2c075d --- /dev/null +++ b/arch/vpu/include/arch/defines.h @@ -0,0 +1,8 @@ +#pragma once + +#define PAGE_SIZE 4096 +#define PAGE_SIZE_SHIFT 12 + +#define ARCH_DEFAULT_STACK_SIZE (8*1024) + +#define CACHE_LINE 32 // TODO, confirm diff --git a/arch/vpu/include/arch/spinlock.h b/arch/vpu/include/arch/spinlock.h new file mode 100644 index 0000000000..15ea2ad813 --- /dev/null +++ b/arch/vpu/include/arch/spinlock.h @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2015 Travis Geiselbrecht + * + * Use of this source code is governed by a MIT-style + * license that can be found in the LICENSE file or at + * https://opensource.org/licenses/MIT + */ +#pragma once + +#include +#include + +#if WITH_SMP +#error vc4 does not support SMP +#endif + +#define SPIN_LOCK_INITIAL_VALUE (0) + +typedef unsigned int spin_lock_t; + +typedef unsigned int spin_lock_saved_state_t; +typedef unsigned int spin_lock_save_flags_t; + +static inline void arch_spin_lock(spin_lock_t *lock) { + *lock = 1; +} + +static inline int arch_spin_trylock(spin_lock_t *lock) { + return 0; +} + +static inline void arch_spin_unlock(spin_lock_t *lock) { + *lock = 0; +} + +static inline void arch_spin_lock_init(spin_lock_t *lock) { + *lock = SPIN_LOCK_INITIAL_VALUE; +} + +static inline bool arch_spin_lock_held(spin_lock_t *lock) { + return *lock != 0; +} + +/* default arm flag is to just disable plain irqs */ +#define ARCH_DEFAULT_SPIN_LOCK_FLAG_INTERRUPTS 0 + +enum { + /* private */ + SPIN_LOCK_STATE_RESTORE_IRQ = 1, +}; + +static inline void +arch_interrupt_save(spin_lock_saved_state_t *statep, spin_lock_save_flags_t flags) { + spin_lock_saved_state_t state = 0; + if (!arch_ints_disabled()) { + state |= SPIN_LOCK_STATE_RESTORE_IRQ; + arch_disable_ints(); + } + *statep = state; +} + +static inline void +arch_interrupt_restore(spin_lock_saved_state_t old_state, spin_lock_save_flags_t flags) { + if (old_state & SPIN_LOCK_STATE_RESTORE_IRQ) { + arch_enable_ints(); + } +} + + + + diff --git a/arch/vpu/include/arch/vc4_pcb.h b/arch/vpu/include/arch/vc4_pcb.h new file mode 100644 index 0000000000..c4a1231e90 --- /dev/null +++ b/arch/vpu/include/arch/vc4_pcb.h @@ -0,0 +1,54 @@ +/*============================================================================= +Copyright (C) 2016-2017 Authors of rpi-open-firmware +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +Process control block. + +=============================================================================*/ + +#pragma once + +typedef struct { + uint32_t r23; // 0 + uint32_t r22; + uint32_t r21; + uint32_t r20; + uint32_t r19; + uint32_t r18; + uint32_t r17; + uint32_t r16; + uint32_t r15; + uint32_t r14; + uint32_t r13; + uint32_t r12; + uint32_t r11; + uint32_t r10; + uint32_t r9; + uint32_t r8; + uint32_t r7; + uint32_t r6; // +68 + + uint32_t r5; + uint32_t r4; + uint32_t r3; + uint32_t r2; + uint32_t r1; + uint32_t r0; // +92 + + uint32_t lr; // +96 + + uint32_t sr; // +100 + uint32_t pc; // +104 +} vc4_saved_state_t; + diff --git a/arch/vpu/include/arch/vc4_traps.h b/arch/vpu/include/arch/vc4_traps.h new file mode 100644 index 0000000000..954fc28bb9 --- /dev/null +++ b/arch/vpu/include/arch/vc4_traps.h @@ -0,0 +1,22 @@ +#pragma once + +#include + +void fleh_zero(void); +void fleh_misaligned(void); +void fleh_dividebyzero(void); +void fleh_undefinedinstruction(void); +void fleh_forbiddeninstruction(void); +void fleh_illegalmemory(void); +void fleh_buserror(void); +void fleh_floatingpoint(void); +void fleh_isp(void); +void fleh_dummy(void); +void fleh_icache(void); +void fleh_veccore(void); +void fleh_badl2alias(void); +void fleh_breakpoint(void); +void fleh_unknown(void); +void fleh_irq(void); +void fleh_swi(void); +void print_vpu_state(vc4_saved_state_t* pcb); diff --git a/arch/vpu/intc.c b/arch/vpu/intc.c new file mode 100644 index 0000000000..f74827cb77 --- /dev/null +++ b/arch/vpu/intc.c @@ -0,0 +1,245 @@ +#include +#include +#include +#include +#include +#include +#include + +#include + +struct handlerArgPair { + int_handler h; + void *arg; +}; +typedef void (*irqType)(void); + +struct handlerArgPair irq_handlers[64]; +// when an exception or interrupt occurs, the cpu will make sp into an alias pointing to r28 +// it will then push pc and sr onto the new stack +// it will then read an entry from this vector table, and set the PC to that entry +// if the highest bit on this addr is set, the cpu will switch into supervisor mode +irqType vectorTable[128] __attribute__ ((section(".data.vectorTable"))); + +uint8_t irq_stack0[1024]; + +static const char* g_ExceptionNames[] = { + "Zero", + "Misaligned", + "Division by zero", + "Undefined instruction", + "Forbidden instruction", + "Illegal memory", + "Bus error", + "Floating point exception", + "ISP", + "Dummy", + "ICache", + "Vector core exception", + "Bad L2 alias", + "Breakpoint" +}; + +void set_interrupt(int intno, bool enable, int core) { + uint32_t base = (core == 0) ? IC0_BASE : IC1_BASE; + + int offset = 0x10 + ((intno >> 3) << 2); + uint32_t slot = 0xF << ((intno & 7) << 2); + + uint32_t v = *REG32(base + offset) & ~slot; + *REG32(base + offset) = enable ? v | slot : v; +} + +void intc_init(void) { + // TODO + for (int i=0; i<64; i++) { + irq_handlers[0].h = 0; // is this needed? maybe .bss already took care of it? + } + // rather then call set_interrupt for each bit in each byte, just blanket clear all + // this will disable every hardware irq + volatile uint32_t *maskreg = (uint32_t*)(IC0_BASE + 0x10); + for (int i=0; i<8; i++) maskreg[i] = 0; + maskreg = (uint32_t*)(IC1_BASE + 0x10); + for (int i=0; i<8; i++) maskreg[i] = 0; + + // https://github.com/hermanhermitage/videocoreiv/wiki/VideoCore-IV-Programmers-Manual#interrupts + // processor internal exceptions + vectorTable[0] = fleh_zero; + vectorTable[1] = fleh_misaligned; + vectorTable[2] = fleh_dividebyzero; + vectorTable[3] = fleh_undefinedinstruction; + vectorTable[4] = fleh_forbiddeninstruction; + vectorTable[5] = fleh_illegalmemory; + vectorTable[6] = fleh_buserror; + vectorTable[7] = fleh_floatingpoint; + vectorTable[8] = fleh_isp; + vectorTable[9] = fleh_dummy; + vectorTable[10] = fleh_icache; + vectorTable[11] = fleh_veccore; + vectorTable[12] = fleh_badl2alias; + vectorTable[13] = fleh_breakpoint; + for (int i=14; i<=31; i++) { + vectorTable[i] = fleh_unknown; + } + // swi opcode handler + for (int i=32; i<=63; i++) { + vectorTable[i] = fleh_swi; + } + // external interrupts + for (int i=64; i<=127; i++) { + vectorTable[i] = (irqType)((uint32_t)fleh_irq | 1); + } + + uint32_t irq_sp = (uint32_t)((irq_stack0 + sizeof(irq_stack0)) - 4); + + __asm__ volatile ("mov r28, %0": :"r"(irq_sp)); + + *REG32(IC0_VADDR) = (uint32_t)vectorTable; + *REG32(IC1_VADDR) = (uint32_t)vectorTable; + + if (((void *)*REG32(IC0_VADDR)) != vectorTable) { + printf("vector table now at 0x%08x 0x%08x\n", *REG32(IC0_VADDR), (uint32_t)vectorTable); + panic("vector table failed to install\n"); + } +} + +#define REGISTER_FORMAT_STRING(prefix) \ + prefix " r0: 0x%08x r1: 0x%08x r2: 0x%08x r3: 0x%08x\n" \ + prefix " r4: 0x%08x r5: 0x%08x r6: 0x%08x r7: 0x%08x\n" \ + prefix " r8: 0x%08x r9: 0x%08x r10: 0x%08x r11: 0x%08x\n" \ + prefix " r12: 0x%08x r13: 0x%08x r14: 0x%08x r15: 0x%08x\n" \ + prefix " pc: 0x%08x lr: 0x%08x sr: 0x%08x\n" + +void print_vpu_state(vc4_saved_state_t* pcb) { + printf("VPU registers:\n"); + + printf( + REGISTER_FORMAT_STRING(" "), + pcb->r0, + pcb->r1, + pcb->r2, + pcb->r3, + pcb->r4, + pcb->r5, + pcb->r6, + pcb->r7, + pcb->r8, + pcb->r9, + pcb->r10, + pcb->r11, + pcb->r12, + pcb->r13, + pcb->r14, + pcb->r15, + pcb->pc, + pcb->lr, + pcb->sr + ); + + printf("Exception info (IC0):\n"); + + printf( + " src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n" + " C: 0x%08x S: 0x%08x\n", + *REG32(IC0_SRC0), + *REG32(IC0_SRC1), + *REG32(IC0_VADDR), + *REG32(IC0_C), + *REG32(IC0_S) + ); + + printf("Exception info (IC1):\n"); + + printf( + " src0: 0x%08x src1: 0x%08x vaddr: 0x%08x\n" + " C: 0x%08x S: 0x%08x\n", + *REG32(IC1_SRC0), + *REG32(IC1_SRC1), + *REG32(IC1_VADDR), + *REG32(IC1_C), + *REG32(IC1_S) + ); +} + +void register_int_handler(unsigned int vector, int_handler handler, void *arg) { + assert(vector < 64); + + spin_lock_saved_state_t state; + arch_interrupt_save(&state, 0); + + irq_handlers[vector].h = handler; + irq_handlers[vector].arg = arg; + + arch_interrupt_restore(state, 0); +} + +status_t unmask_interrupt(unsigned int vector) { + assert(vector < 64); + set_interrupt(vector, true, 0); + return NO_ERROR; +} + +static const char* exception_name(uint32_t n) { + if (n >= (sizeof(g_ExceptionNames)/4)) return "unknown"; + return g_ExceptionNames[n]; +} + +// c mode handlers, called by interrupt.S + +void sleh_fatal(vc4_saved_state_t* pcb, uint32_t n) { + printf("Fatal VPU Exception: %s\n", exception_name(n)); + + print_vpu_state(pcb); + + printf("We are hanging here ...\n"); + + while(true) __asm__ volatile ("nop"); +} + +// upon entry to this function(before its prologue runs), sp and r0 point to a `struct vc4_saved_state_t` +// r0 (which lands in pcb) contains a copy of that sp from before the prologue +// some common values and offsets: +// r0 + 0: r23 +// ... +// r0 + 92: r0 +// r0 + 96: lr +// r0 + 100: sr +// r0 + 104: pc +void sleh_irq(vc4_saved_state_t* pcb, uint32_t tp) { + uint32_t status = *REG32(IC0_S); + uint32_t source = status & 0xFF; + enum handler_return ret = INT_NO_RESCHEDULE; + + //uint32_t sp, sr; + //__asm__ volatile ("mov %0, sp" : "=r"(sp)); + //__asm__ volatile ("mov %0, sr" : "=r"(sr)); + //dprintf(INFO, "sleh_irq\nsp: 0x%x\nsr: 0x%x\n", sp, sr); + + //dprintf(INFO, "VPU Received interrupt from source %d\n", source); + + switch (source) { + case 64: // timer0 + case 73: // dwc2 + case 106: // pv2 + case 121: // uart + assert(irq_handlers[source - 64].h); + ret = irq_handlers[source - 64].h(irq_handlers[source - 64].arg); + if (ret == INT_RESCHEDULE) { + //dprintf(INFO, "pre-emptying\n"); + thread_preempt(); + //dprintf(INFO, "done preempt\n"); + } + break; + case INTERRUPT_ARM: + // fired when the arm cpu writes to the arm->vpu mailbox + break; + default: + print_vpu_state(pcb); + panic("unknown interrupt source!"); + } +} + +void sleh_swi(vc4_saved_state_t* pcb) { + dprintf(INFO, "got SWI\n"); + print_vpu_state(pcb); +} diff --git a/arch/vpu/interrupt.S b/arch/vpu/interrupt.S new file mode 100644 index 0000000000..2343721341 --- /dev/null +++ b/arch/vpu/interrupt.S @@ -0,0 +1,79 @@ +.macro SaveRegsLower + stm lr, (--sp) + nop + nop + nop + nop + stm r0-r5, (--sp) + nop + nop + nop + nop +.endm + +.macro SaveRegsUpper + stm r6-r15, (--sp) + stm r16-r23, (--sp) +.endm + +.macro SaveRegsAll + SaveRegsLower + SaveRegsUpper +.endm + +.macro ExceptionHandler label, exception_number +.global fleh_\label +fleh_\label: + SaveRegsLower + mov r1, \exception_number + b irq_fatal +.endm + +.text +irq_fatal: + SaveRegsUpper + mov r0, sp + b sleh_fatal + + ExceptionHandler zero, #0 + ExceptionHandler misaligned, #1 + ExceptionHandler dividebyzero, #2 + ExceptionHandler undefinedinstruction, #3 + ExceptionHandler forbiddeninstruction, #4 + ExceptionHandler illegalmemory, #5 + ExceptionHandler buserror, #6 + ExceptionHandler floatingpoint, #7 + ExceptionHandler isp, #8 + ExceptionHandler dummy, #9 + ExceptionHandler icache, #10 + ExceptionHandler veccore, #11 + ExceptionHandler badl2alias, #12 + ExceptionHandler breakpoint, #13 + ExceptionHandler unknown, #14 + +.global fleh_irq +fleh_irq: + SaveRegsAll + mov r0, sp + mov r1, r29 + bl sleh_irq +return_from_exception: + ldm r16-r23, (sp++) + ldm r6-r15, (sp++) + ldm r0-r5, (sp++) + ld lr, (sp++) + rti + +.global fleh_swi +fleh_swi: + stm lr, (--sp) + stm r0-r5, (--sp) + stm r6-r15, (--sp) + stm r16-r23, (--sp) + mov r0, sp + bl sleh_swi + ldm r16-r23, (sp++) + ldm r6-r15, (sp++) + ldm r0-r5, (sp++) + ld lr, (sp++) + rti diff --git a/arch/vpu/rules.mk b/arch/vpu/rules.mk new file mode 100644 index 0000000000..afc37f7f17 --- /dev/null +++ b/arch/vpu/rules.mk @@ -0,0 +1,27 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +TOOLCHAIN_PREFIX := vc4-elf- + +$(BUILDDIR)/system-onesegment.ld: $(LOCAL_DIR)/start.ld + @echo generating $@ + @$(MKDIR) + echo TODO: properly template the linker script + cp $< $@ + +# TODO, fix the linker flags +ARCH_LDFLAGS += -L/nix/store/cwpy4q0qvdwdif1zfwnfg5gi50c6j9w8-vc4-elf-stage-final-gcc-debug-6.5.0/lib/gcc/vc4-elf/6.2.1/ + +MODULE_SRCS += \ + $(LOCAL_DIR)/arch.c \ + $(LOCAL_DIR)/thread.c \ + $(LOCAL_DIR)/intc.c \ + $(LOCAL_DIR)/start.S \ + $(LOCAL_DIR)/thread_asm.S \ + $(LOCAL_DIR)/interrupt.S \ + +MODULE_DEPS += dev/timer/vc4 +GLOBAL_DEFINES += VC4_TIMER_CHANNEL=0 + +include make/module.mk diff --git a/arch/vpu/start.S b/arch/vpu/start.S new file mode 100644 index 0000000000..b81d1a621d --- /dev/null +++ b/arch/vpu/start.S @@ -0,0 +1,87 @@ +#include + +#define MANUAL_UART + +.section .text.start +FUNCTION(_start) +.global _start +_start: + di + mov sp, _fstack +#ifdef MANUAL_UART + bl manual_uart_cfg +#endif + bl zero_bss + bl lk_main +loop: + b loop + +.global core2_start +core2_start: + mov r0, core2_stack_top + ld sp, (r0) + mov r0, 0 + mov r1, 'A' + bl uart_putc + bl core2_entry +loop2: + b loop2 + +.global testit +testit: + st r1, (r0) + st r2, (r0+4) + st r3, (r0+8) + st r4, (r0+12) + rts + +.global toggle18 +toggle18: + mov r0, 0x7e20001c // set + mov r1, 0x7e200028 // clear + mov r2, 1<<18 + mov r3, 100000000 +loop18: + st r2, (r0) // high + mov r4, 1 + addcmpbne r4, -1, 0, 0 // delay + + st r2, (r1) // low + mov r4, 1 + addcmpbne r4, -1, 0, 0 // delay + + addcmpbne r3,-1,0x0,loop18 // repeat + rts + +#ifdef MANUAL_UART +manual_uart_cfg: + mov r0, 0x7e200004 // GP_FSEL1 + mov r1, 0x00004000 + st r1, (r0) + mov r0, 0x7e1010f4 // CM_UARTDIV + //mov r1, 0x5a003900 //19.2mhz divisor + mov r1, 0x5a00a050 // 54mhz divisor + st r1, (r0) + mov r0, 0x7e1010f0 // CM_UARTCTL + mov r1, 0x5a000211 + st r1, (r0) + mov r0, 0x7e201044 + mov r1, 0x000007ff + st r1, (r0) + mov r0, 0x7e20102c + mov r1, 0x00000070 + st r1, (r0) + mov r0, 0x7e201024 + mov r1, 0x00000002 + st r1, (r0) + mov r0, 0x7e201028 + mov r1, 0x0000003b + st r1, (r0) + mov r0, 0x7e201030 + mov r1, 0x00000301 + st r1, (r0) + mov r0, 0x7e201000 + mov r1, 'U' + st r1, (r0) + rts +#endif diff --git a/arch/vpu/startup.c b/arch/vpu/startup.c new file mode 100644 index 0000000000..52cef6d0d9 --- /dev/null +++ b/arch/vpu/startup.c @@ -0,0 +1,3 @@ +void vc4_start() { + lk_main(); +} diff --git a/arch/vpu/thread.c b/arch/vpu/thread.c new file mode 100644 index 0000000000..459937af22 --- /dev/null +++ b/arch/vpu/thread.c @@ -0,0 +1,61 @@ +#include +#include + +void vc4_context_switch(struct arch_thread *oldsp, struct arch_thread *newsp); + +void arch_context_switch(thread_t *oldthread, thread_t *newthread) { + uint32_t r28, sp; + __asm__ volatile ("mov %0, r28" : "=r"(r28)); + __asm__ volatile ("mov %0, sp" : "=r"(sp)); + //dprintf(INFO, "arch_context_switch\nr28: 0x%x\nsp: 0x%x\n", r28, sp); + //dprintf(INFO, "switching (%s) -> %p(%s)\n", oldthread->name, newthread->arch.sp, newthread->name); + //dprintf(INFO, "old: %p %s\nSP: 0x%x\nSR: 0x%x\n", oldthread, oldthread->name, oldthread->arch.sp, oldthread->arch.sr); + //dprintf(INFO, "new: %p %s\nSP: 0x%x\nSR: 0x%x\n", newthread, newthread->name, newthread->arch.sp, newthread->arch.sr); + vc4_context_switch(&oldthread->arch, &newthread->arch); + //dprintf(INFO, "switched\n\n"); +} + +static inline void push(thread_t *t, uint32_t val) { + // SP always points to the last valid value in the stack + t->arch.sp -= 4; + volatile uint32_t *ram32 = 0; + ram32[t->arch.sp/4] = val; +} + +static void initial_thread_func(void) __NO_RETURN; +static void initial_thread_func(void) { + thread_t *ct = get_current_thread(); + //uint32_t own_sp; + + //__asm__ volatile ("mov %0, sp": "=r"(own_sp)); + //dprintf(INFO, "thread %p(%s) starting with sp near 0x%x\n", ct, ct->name, own_sp); + spin_unlock(&thread_lock); + arch_enable_ints(); + + int ret = ct->entry(ct->arg); + + thread_exit(ret); +} + +void arch_thread_initialize(thread_t *t) { + //printf("thread %p(%s) has a stack of %p+0x%x\n", t, t->name, t->stack, t->stack_size); + t->arch.sp = (uint32_t)((t->stack + t->stack_size) - 4); + __asm__ volatile ("mov %0, sr": "=r"(t->arch.sr)); + t->arch.sr &= ~0x40000000; // disable irq in the new thread + //printf("initial sr: 0x%x\n", t->arch.sr); + push(t, (uint32_t)(&initial_thread_func)); // lr + for (int i=6; i<=23; i++) { + push(t, 0); // r${i} + } +} + +void arch_dump_thread(thread_t *t) { + if (t->state != THREAD_RUNNING) { + dprintf(INFO, "\tarch: sp 0x%x\n\t sr: 0x%x\n", t->arch.sp, t->arch.sr); + } + /* else if (t->state == THREAD_RUNNING) { + uint32_t sp; + __asm__ volatile ("mov %0, sp" : "=r"(sp)); + dprintf(INFO, "\tarch: sp ~0x%x\n", sp); + }*/ +} diff --git a/arch/vpu/thread_asm.S b/arch/vpu/thread_asm.S new file mode 100644 index 0000000000..fdcbe39732 --- /dev/null +++ b/arch/vpu/thread_asm.S @@ -0,0 +1,44 @@ +.text +.global vc4_context_switch +// r0 is address of the old arch_thread +// r1 is address of the new arch_thread +vc4_context_switch: + // save all state that is caller saved + stm lr, (--sp) + stm r6-r15, (--sp) + stm r16-r23, (--sp) + + + // swap stacks + st sp, (r0) + mov r2, sr + st r2, (r0+4) + + ld sp, (r1) + mov r3, sp + //swi 0 + + // restore all state from stack + ldm r16-r23, (sp++) + ldm r6-r15, (sp++) + ldm r0, (sp++) + mov lr, r0 + + lea r0, vc4_context_switch_finish + st r0, (--sp) + ld r1, (r1+4) // load saved SR + st r1, (--sp) + rti + +oldvc4_context_switch: + stm lr, (--sp) + stm r6-r15, (--sp) + stm r16-r23, (--sp) + st sp, (r0) + mov sp, r1 + ldm r16-r23, (sp++) + ldm r6-r15, (sp++) + ldm pc,(sp++) + +vc4_context_switch_finish: + rts diff --git a/default.nix b/default.nix new file mode 100644 index 0000000000..122b7124ec --- /dev/null +++ b/default.nix @@ -0,0 +1,93 @@ +let + sources = import ./nix/sources.nix; + pkgs = import (builtins.fetchTarball https://github.com/input-output-hk/nixpkgs/archive/0ee0489d42e.tar.gz) {}; + lib = pkgs.lib; + overlay = self: super: { + littlekernel = self.stdenv.mkDerivation { + name = "littlekernel"; + src = lib.cleanSource ./.; + #nativeBuildInputs = [ x86_64.uart-manager ]; + nativeBuildInputs = [ x86_64.python x86_64.imagemagick x86_64.qemu ]; + hardeningDisable = [ "format" ]; + }; + uart-manager = self.stdenv.mkDerivation { + name = "uart-manager"; + src = sources.rpi-open-firmware + "/uart-manager"; + }; + }; + vc4 = pkgs.pkgsCross.vc4.extend overlay; + x86_64 = pkgs.extend overlay; + arm7 = pkgs.pkgsCross.arm-embedded.extend overlay; +in lib.fix (self: { + shell = pkgs.stdenv.mkDerivation { + name = "shell"; + buildInputs = with pkgs; [ + pkgsCross.arm-embedded.stdenv.cc + pkgsCross.i686-embedded.stdenv.cc + pkgsCross.vc4.stdenv.cc + pkgsCross.aarch64-embedded.stdenv.cc + pkgsCross.riscv32-embedded.stdenv.cc + pkgsCross.riscv64-embedded.stdenv.cc + python + qemu + imagemagick + ]; + ARCH_x86_TOOLCHAIN_PREFIX = "i686-elf-"; + ARCH_x86_TOOLCHAIN_INCLUDED = true; + ARCH_arm64_TOOLCHAIN_PREFIX = "aarch64-none-elf-"; + }; + arm7 = { + inherit (arm7) littlekernel; + }; + arm = { + rpi1-test = arm7.callPackage ./lk.nix { project = "rpi1-test"; }; + rpi2-test = arm7.callPackage ./lk.nix { project = "rpi2-test"; }; + rpi3-test = pkgs.pkgsCross.aarch64-embedded.callPackage ./lk.nix { project = "rpi3-test"; }; + }; + vc4 = { + shell = vc4.littlekernel; + rpi3.bootcode = vc4.callPackage ./lk.nix { project = "rpi3-bootcode"; }; + rpi3.start = vc4.callPackage ./lk.nix { project = "rpi3-start"; }; + rpi4.start4 = vc4.callPackage ./lk.nix { project = "rpi4-start4"; }; + vc4.stage1 = vc4.callPackage ./lk.nix { project = "vc4-stage1"; }; + vc4.stage2 = vc4.callPackage ./lk.nix { project = "vc4-stage2"; }; + }; + x86_64 = { + inherit (x86_64) uart-manager; + }; + testcycle = pkgs.writeShellScript "testcycle" '' + set -e + scp ${self.vc4.rpi3.bootcode}/lk.bin root@router.localnet:/tftproot/open-firmware/bootcode.bin + exec ${x86_64.uart-manager}/bin/uart-manager + ''; + disk_image = pkgs.vmTools.runInLinuxVM (pkgs.runCommand "disk-image" { + buildInputs = with pkgs; [ utillinux dosfstools e2fsprogs mtools libfaketime ]; + preVM = '' + mkdir -p $out + diskImage=$out/disk-image.img + truncate $diskImage -s 64m + ''; + postVM = '' + ''; + } '' + sfdisk /dev/vda < +#include +#include +#include +#include +#include +#include + +static enum handler_return timer0_irq(void *arg); +static void vc4_timer_init(uint level); + +static platform_timer_callback timer_cb = 0;; +static void *timer_arg = 0;; + +LK_INIT_HOOK(vc4_timer, &vc4_timer_init, LK_INIT_LEVEL_PLATFORM); + +lk_bigtime_t current_time_hires(void) { + //TODO, deal with rollover + return ( ((lk_bigtime_t)*REG32(ST_CHI)) << 32) | *REG32(ST_CLO); +} + +lk_time_t current_time(void) { + return current_time_hires(); +} + +static void vc4_timer_init(uint level) { +#if VC4_TIMER_CHANNEL == 0 + // TODO, only register the interrupt handler once + register_int_handler(0, timer0_irq, NULL); + unmask_interrupt(0); +#elif VC4_TIMER_CHANNEL == 1 + register_int_handler(1, timer0_irq, NULL); + unmask_interrupt(1); +#else +#error unsupported timer channel +#endif +} + +status_t platform_set_oneshot_timer (platform_timer_callback callback, void *arg, lk_time_t interval) { + timer_cb = callback; + timer_arg = arg; + //printf("platform_set_oneshot_timer(..., ..., %d)\n", interval); +#if VC4_TIMER_CHANNEL == 0 + *REG32(ST_C0) = *REG32(ST_CLO) + (interval * 1000); +#elif VC4_TIMER_CHANNEL == 1 + *REG32(ST_C1) = *REG32(ST_CLO) + (interval * 1000); +#else +#error unsupported timer channel +#endif + return NO_ERROR; +} + +void platform_stop_timer(void) { +} + +static enum handler_return timer0_irq(void *arg) { + uint32_t cs = *REG32(ST_CS); + *REG32(ST_CS) = cs; // ack the event so the irq signal clears + assert(timer_cb); + return timer_cb(timer_arg, current_time()); +} diff --git a/kernel/novm/novm.c b/kernel/novm/novm.c index ba664ee241..04a41bc2bb 100644 --- a/kernel/novm/novm.c +++ b/kernel/novm/novm.c @@ -299,6 +299,7 @@ static void novm_dump_arena(struct novm_arena *n) { mutex_acquire(&n->lock); printf("name '%s', %zu pages, each %zdk (%zdk in all)\n", n->name, n->pages, (size_t)PAGE_SIZE >> 10, (size_t)(PAGE_SIZE * n->pages) >> 10); printf(" range: %p-%p\n", (void *)n->base, (char *)n->base + n->size); + printf(" size: 0x%x\n", n->size); printf(" unaligned range: %p-%p\n", n->unaligned_area, n->unaligned_area + n->unaligned_size); unsigned i; size_t in_use = 0; diff --git a/kernel/thread.c b/kernel/thread.c index 5588ecd742..e46b4e0b99 100644 --- a/kernel/thread.c +++ b/kernel/thread.c @@ -461,6 +461,8 @@ void thread_resched(void) { thread_t *current_thread = get_current_thread(); uint cpu = arch_curr_cpu_num(); + //dprintf(INFO, "thread_resched called on thread %p(%s) on core %d\n", current_thread, current_thread->name, cpu); + DEBUG_ASSERT(arch_ints_disabled()); DEBUG_ASSERT(spin_lock_held(&thread_lock)); DEBUG_ASSERT(current_thread->state != THREAD_RUNNING); @@ -601,6 +603,8 @@ void thread_yield(void) { THREAD_STATS_INC(yields); + //dprintf(INFO, "thread_yield\n"); + /* we are yielding the cpu, so stick ourselves into the tail of the run queue and reschedule */ current_thread->state = THREAD_READY; current_thread->remaining_quantum = 0; diff --git a/lib/cbuf/cbuf.c b/lib/cbuf/cbuf.c index 50fb963c16..7e2f523bbb 100644 --- a/lib/cbuf/cbuf.c +++ b/lib/cbuf/cbuf.c @@ -219,6 +219,7 @@ size_t cbuf_read_char(cbuf_t *cbuf, char *c, bool block) { DEBUG_ASSERT(c); retry: + DEBUG_ASSERT(cbuf->event.magic == EVENT_MAGIC); if (block) event_wait(&cbuf->event); diff --git a/lib/debug/debug.c b/lib/debug/debug.c index cc117ca50c..52aed9a11f 100644 --- a/lib/debug/debug.c +++ b/lib/debug/debug.c @@ -25,6 +25,7 @@ void spin(uint32_t usecs) { } void _panic(void *caller, const char *fmt, ...) { + arch_disable_ints(); printf("panic (caller %p): ", caller); va_list ap; diff --git a/lib/debugcommands/debugcommands.c b/lib/debugcommands/debugcommands.c index a23a66ab12..17b9581055 100644 --- a/lib/debugcommands/debugcommands.c +++ b/lib/debugcommands/debugcommands.c @@ -310,6 +310,8 @@ static int cmd_crash(int argc, const cmd_args *argv) { volatile uint32_t *ptr = (void *)1; *ptr = 1; + volatile int a = 1 / 0; + /* if it didn't, panic the system */ panic("crash"); diff --git a/lib/elf/elf.c b/lib/elf/elf.c index 5163419f44..d4c1825224 100644 --- a/lib/elf/elf.c +++ b/lib/elf/elf.c @@ -154,6 +154,10 @@ static int verify_eheader(const void *header) { #elif ARCH_MICROBLAZE if (eheader->e_machine != EM_MICROBLAZE) return ERR_NOT_FOUND; +#elif ARCH_VPU + printf("%d %d\n", eheader->e_machine, EM_VC4); + if (eheader->e_machine != EM_VC4) + return ERR_NOT_FOUND; #else #error find proper EM_ define for your machine #endif diff --git a/lib/elf/include/lib/elf_defines.h b/lib/elf/include/lib/elf_defines.h index d6e26712e3..5dd475094c 100644 --- a/lib/elf/include/lib/elf_defines.h +++ b/lib/elf/include/lib/elf_defines.h @@ -40,6 +40,7 @@ #define EM_IA_64 50 #define EM_X86_64 62 #define EM_OR1K 92 +#define EM_VC4 137 #define EM_AARCH64 183 #define EM_MICROBLAZE 189 #define EM_ALPHA 0x9026 diff --git a/lib/gfx/gfx.c b/lib/gfx/gfx.c index 9b1e31d8f9..91a22a69ac 100644 --- a/lib/gfx/gfx.c +++ b/lib/gfx/gfx.c @@ -556,6 +556,7 @@ gfx_surface *gfx_create_surface(void *ptr, uint width, uint height, uint stride, surface->height = height; surface->stride = stride; surface->alpha = MAX_ALPHA; + surface->flush = NULL; // set up some function pointers switch (format) { diff --git a/lib/libc/string/arch/vpu/rules.mk b/lib/libc/string/arch/vpu/rules.mk new file mode 100644 index 0000000000..7a97451a6d --- /dev/null +++ b/lib/libc/string/arch/vpu/rules.mk @@ -0,0 +1,2 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + diff --git a/lib/tga/rules.mk b/lib/tga/rules.mk index 3c63f5fd3f..27a4f6f9ca 100644 --- a/lib/tga/rules.mk +++ b/lib/tga/rules.mk @@ -5,4 +5,7 @@ MODULE := $(LOCAL_DIR) MODULE_SRCS += \ $(LOCAL_DIR)/tga.c +MODULES += \ + lib/gfx \ + include make/module.mk diff --git a/lk.nix b/lk.nix new file mode 100644 index 0000000000..6420df8d63 --- /dev/null +++ b/lk.nix @@ -0,0 +1,28 @@ +{ stdenv, project, which, imagemagick, python }: + +stdenv.mkDerivation { + name = "littlekernel-${project}"; + src = builtins.path { + filter = stdenv.lib.cleanSourceFilter; + path = ./.; + name = "lk-src"; + }; + makeFlags = [ "PROJECT=${project}" ]; + hardeningDisable = [ "format" ]; + nativeBuildInputs = [ + which + imagemagick.__spliced.buildBuild # work around a bug in nixpkgs + python + ]; + installPhase = '' + mkdir -p $out/nix-support + cp -r build-${project}/{config.h,lk.*} $out + cat < $out/nix-support/hydra-metrics + lk.bin $(stat --printf=%s $out/lk.bin) bytes + lk.elf $(stat --printf=%s $out/lk.elf) bytes + EOF + echo "file binary-dist $out/lk.bin" >> $out/nix-support/hydra-build-products + echo "file binary-dist $out/lk.elf" >> $out/nix-support/hydra-build-products + ''; + ARCH_arm64_TOOLCHAIN_PREFIX = "aarch64-none-elf-"; +} diff --git a/nix/sources.json b/nix/sources.json new file mode 100644 index 0000000000..1687272a5d --- /dev/null +++ b/nix/sources.json @@ -0,0 +1,38 @@ +{ + "niv": { + "branch": "master", + "description": "Easy dependency management for Nix projects", + "homepage": "https://github.com/nmattia/niv", + "owner": "nmattia", + "repo": "niv", + "rev": "61b61d1e5f8096fe65fb825bec23f33e861c51d0", + "sha256": "1dwfkd942wisccpsv0kf47abl0n17d9v4zasv4bm8lvy1dhv82ia", + "type": "tarball", + "url": "https://github.com/nmattia/niv/archive/61b61d1e5f8096fe65fb825bec23f33e861c51d0.tar.gz", + "url_template": "https://github.com///archive/.tar.gz" + }, + "nixpkgs": { + "branch": "nixos-19.03", + "description": "A read-only mirror of NixOS/nixpkgs tracking the released channels. Send issues and PRs to", + "homepage": "https://github.com/NixOS/nixpkgs", + "owner": "NixOS", + "repo": "nixpkgs-channels", + "rev": "c8db7a8a16ee9d54103cade6e766509e1d1c8d7b", + "sha256": "1b3h4mwpi10blzpvgsc0191k4shaw3nw0qd2p82hygbr8vv4g9dv", + "type": "tarball", + "url": "https://github.com/NixOS/nixpkgs-channels/archive/c8db7a8a16ee9d54103cade6e766509e1d1c8d7b.tar.gz", + "url_template": "https://github.com///archive/.tar.gz" + }, + "rpi-open-firmware": { + "branch": "master", + "description": "Open source VPU side bootloader for Raspberry Pi.", + "homepage": null, + "owner": "cleverca22", + "repo": "rpi-open-firmware", + "rev": "b2d019aca2cc788a8f656ea28ca91c0df9ff7291", + "sha256": "1kiimh0gbjai6nbd1i06kbk1ymvhyr4xqd0196048hq8a9wf8kdb", + "type": "tarball", + "url": "https://github.com/cleverca22/rpi-open-firmware/archive/b2d019aca2cc788a8f656ea28ca91c0df9ff7291.tar.gz", + "url_template": "https://github.com///archive/.tar.gz" + } +} diff --git a/nix/sources.nix b/nix/sources.nix new file mode 100644 index 0000000000..d4ac577f25 --- /dev/null +++ b/nix/sources.nix @@ -0,0 +1,93 @@ +# This file has been generated by Niv. + +# A record, from name to path, of the third-party packages +with rec +{ + pkgs = + if hasNixpkgsPath + then + if hasThisAsNixpkgsPath + then import (builtins_fetchTarball { inherit (sources_nixpkgs) url sha256; }) {} + else import {} + else + import (builtins_fetchTarball { inherit (sources_nixpkgs) url sha256; }) {}; + + sources_nixpkgs = + if builtins.hasAttr "nixpkgs" sources + then sources.nixpkgs + else abort + '' + Please specify either (through -I or NIX_PATH=nixpkgs=...) or + add a package called "nixpkgs" to your sources.json. + ''; + + # fetchTarball version that is compatible between all the versions of Nix + builtins_fetchTarball = + { url, sha256 }@attrs: + let + inherit (builtins) lessThan nixVersion fetchTarball; + in + if lessThan nixVersion "1.12" then + fetchTarball { inherit url; } + else + fetchTarball attrs; + + # fetchurl version that is compatible between all the versions of Nix + builtins_fetchurl = + { url, sha256 }@attrs: + let + inherit (builtins) lessThan nixVersion fetchurl; + in + if lessThan nixVersion "1.12" then + fetchurl { inherit url; } + else + fetchurl attrs; + + # A wrapper around pkgs.fetchzip that has inspectable arguments, + # annoyingly this means we have to specify them + fetchzip = { url, sha256 }@attrs: pkgs.fetchzip attrs; + + # A wrapper around pkgs.fetchurl that has inspectable arguments, + # annoyingly this means we have to specify them + fetchurl = { url, sha256 }@attrs: pkgs.fetchurl attrs; + + hasNixpkgsPath = (builtins.tryEval ).success; + hasThisAsNixpkgsPath = + (builtins.tryEval ).success && == ./.; + + sources = builtins.fromJSON (builtins.readFile ./sources.json); + + mapAttrs = builtins.mapAttrs or + (f: set: with builtins; + listToAttrs (map (attr: { name = attr; value = f attr set.${attr}; }) (attrNames set))); + + # borrowed from nixpkgs + functionArgs = f: f.__functionArgs or (builtins.functionArgs f); + callFunctionWith = autoArgs: f: args: + let auto = builtins.intersectAttrs (functionArgs f) autoArgs; + in f (auto // args); + + getFetcher = spec: + let fetcherName = + if builtins.hasAttr "type" spec + then builtins.getAttr "type" spec + else "builtin-tarball"; + in builtins.getAttr fetcherName { + "tarball" = fetchzip; + "builtin-tarball" = builtins_fetchTarball; + "file" = fetchurl; + "builtin-url" = builtins_fetchurl; + }; +}; +# NOTE: spec must _not_ have an "outPath" attribute +mapAttrs (_: spec: + if builtins.hasAttr "outPath" spec + then abort + "The values in sources.json should not have an 'outPath' attribute" + else + if builtins.hasAttr "url" spec && builtins.hasAttr "sha256" spec + then + spec // + { outPath = callFunctionWith spec (getFetcher spec) { }; } + else spec + ) sources diff --git a/notes.txt b/notes.txt new file mode 100644 index 0000000000..bc33fab04b --- /dev/null +++ b/notes.txt @@ -0,0 +1,18 @@ +0xc0261e40 bootstrap2 stack +0xc0263820 shell stack +0xc15ffe8e stray pc +0xc15fffcc primary stack + + +# build LK +[nix-shell:~/apps/rpi/lk]$ make PROJECT=rpi4-recovery +# sign LK +[nix-shell:~/apps/rpi/rpi-eeprom/firmware/beta]$ node ~/apps/rpi-open-firmware/sign.js ~/apps/rpi/lk/build-rpi4-recovery/lk.bin recovery.bin +# transfer to other pc +[clever@amd-nixos:~/apps/rpi/usbboot]$ scp system76:/home/clever/apps/rpi/rpi-eeprom/firmware/beta/recovery.bin lk/bootcode.bin +# host over usb +[clever@amd-nixos:~/apps/rpi/usbboot]$ sudo ./rpiboot -v -d ./lk/ +# launch everything +[nix-shell:~/apps/rpi/lk]$ uart-manager +Uuart early init done + diff --git a/platform/bcm28xx/arm/arm.c b/platform/bcm28xx/arm/arm.c new file mode 100644 index 0000000000..97a99d3b50 --- /dev/null +++ b/platform/bcm28xx/arm/arm.c @@ -0,0 +1,182 @@ +#include +#include +#include +#include +#include +#include +#include + +extern uint8_t arm_payload_start, arm_payload_end; + +void mapBusToArm(uint32_t busAddr, uint32_t armAddr); +void setupClock(void); +void bridgeStart(bool cycleBrespBits); + +#define ARM_CONTROL0 (ARM_BASE+0x000) +#define ARM_C0_SIZ1G 0x00000003 +#define ARM_C0_BRESP1 0x00000004 +#define ARM_C0_BRESP2 0x00000008 +#define ARM_C0_FULLPERI 0x00000040 +#define ARM_C0_APROTPASS 0x0000A000 // Translate 1:1 +#define ARM_C0_APROTMSK 0x0000F000 +#define ARM_TRANSLATE (ARM_BASE+0x100) +#define ARM_CONTROL1 (ARM_BASE+0x440) +#define ARM_C1_PERSON 0x00000100 // peripherals on +#define ARM_C1_REQSTOP 0x00000200 // ASYNC bridge request stop +#define ARM_ERRHALT (ARM_BASE + 0x448) +#define ARM_ID (ARM_BASE + 0x44C) + +#define PM_PROC_ARMRSTN_CLR 0xffffffbf + +static const uint8_t g_BrespTab[] = { + 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x18, 0x0, + 0x10, 0x14, 0x10, 0x1C, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x10, 0x1C, 0x18, 0x1C, 0x10, 0x14, 0x18, 0x1C, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x0, + 0x10, 0x14, 0x18, 0x14, 0x18, 0x14, 0x10, 0x14, 0x10, 0x14, 0x10, 0x14, 0x18, 0x0 +}; + +static void printregs(void) { + printf("C0: 0x%x, C1: 0x%x, ERRHALT: 0x%x\n", *REG32(ARM_CONTROL0), *REG32(ARM_CONTROL1), *REG32(ARM_ERRHALT)); + printf("CM_LOCK: 0x%x\n", *REG32(CM_LOCK)); +} + +static void arm_init(const struct app_descriptor *app) { + power_arm_start(); + printregs(); + printf("arm starting...\n"); + memcpy((void*)0xc0000000, &arm_payload_start, &arm_payload_end - &arm_payload_start); + mapBusToArm(0xc0000000, 0); + printf("armid 0x%x, C0 0x%x\n", *REG32(ARM_ID), *REG32(ARM_CONTROL0)); + /* + * enable peripheral access, map arm secure bits to axi secure bits 1:1 and + * set the mem size for who knows what reason. + */ + *REG32(ARM_CONTROL0) |= + ARM_C0_BRESP2 + | ARM_C0_SIZ1G + | ARM_C0_APROTPASS | ARM_C0_APROTMSK // allow both kernel and userland to access mmio + | ARM_C0_FULLPERI // allow access to all peripherals + | (0x8 << 20) // ARM_C0_PRIO_PER + | (0x5 << 24) // ARM_C0_PRIO_L2 + | (0xa << 28); // ARM_C0_PRIO_UC + // | ARM_C0_AARCH64; + *REG32(ARM_CONTROL1) |= ARM_C1_PERSON; + + printregs(); + + setupClock(); + printregs(); + power_arm_start(); + printregs(); + bridgeStart(true); + printregs(); +} + +// maps a 16mb chunk of ram +// the bus address has a resolution of 2mb +// the arm addr has a resolution of 16mb +// the entire mapping is 16mb long +// comments say there are 32 slots in the list (512mb mapped) an another 32 spare (1gig mapped) +void mapBusToArm(uint32_t busAddr, uint32_t armAddr) { + volatile uint32_t* tte = (volatile uint32_t*)ARM_TRANSLATE; + + uint32_t index = armAddr >> 24; // div by 16mb + uint32_t pte = busAddr >> 21; // div by 2mb + printf("mapBusToArm index:%x, pte:%x\n", index, pte); + + tte[index] = pte; +} + +void setupClock(void) { + puts("initializing PLLB ..."); + + /* oscillator->pllb */ + *REG32(A2W_XOSC_CTRL) |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLBEN_SET; + + *REG32(A2W_PLLB_FRAC) = A2W_PASSWORD | 0xeaaa8; // out of 0x100000 + *REG32(A2W_PLLB_CTRL) = A2W_PASSWORD | 48 | 0x1000; + + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET; + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET; + + *REG32(A2W_PLLB_ANA3) = A2W_PASSWORD | 0x100; + *REG32(A2W_PLLB_ANA2) = A2W_PASSWORD | 0x0; + *REG32(A2W_PLLB_ANA1) = A2W_PASSWORD | 0x140000; + *REG32(A2W_PLLB_ANA0) = A2W_PASSWORD | 0x0; + + *REG32(CM_PLLB) = CM_PASSWORD | 0xAA; // hold all divider taps + + uint32_t dig0 = *REG32(A2W_PLLB_DIG0), + dig1 = *REG32(A2W_PLLB_DIG1), + dig2 = *REG32(A2W_PLLB_DIG2), + dig3 = *REG32(A2W_PLLB_DIG3); + + *REG32(A2W_PLLB_DIG3) = A2W_PASSWORD | dig3; + *REG32(A2W_PLLB_DIG2) = A2W_PASSWORD | (dig2 & 0xFFEFFBFE); + *REG32(A2W_PLLB_DIG1) = A2W_PASSWORD | (dig1 & ~(1 << 14)); + *REG32(A2W_PLLB_DIG0) = A2W_PASSWORD | dig0; + + *REG32(A2W_PLLB_CTRL) |= A2W_PASSWORD | 0x20000; + + dig3 |= 0x42; + + *REG32(A2W_PLLB_DIG3) = A2W_PASSWORD | dig3; + *REG32(A2W_PLLB_DIG2) = A2W_PASSWORD | dig2; + *REG32(A2W_PLLB_DIG1) = A2W_PASSWORD | dig1; + *REG32(A2W_PLLB_DIG0) = A2W_PASSWORD | dig0; + + + *REG32(A2W_PLLB_ARM) = A2W_PASSWORD | 2; + + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET | CM_PLLB_LOADARM_SET; + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLLB_DIGRST_SET | CM_PLLB_ANARST_SET | CM_PLLB_HOLDARM_SET; + *REG32(CM_PLLB) = CM_PASSWORD; + + *REG32(CM_ARMCTL) = CM_PASSWORD | 4 | CM_ARMCTL_ENAB_SET; + + printf("KAIP = 0x%X\n", *REG32(A2W_PLLB_ANA_KAIP)); /* 0x228 */ + printf("MULTI = 0x%X\n", *REG32(A2W_PLLB_ANA_MULTI)); /* 0x613277 */ + + puts("ARM clock succesfully initialized!"); +} + +void bridgeWriteBresp(uint8_t bits) { + //printf("bits: 0x%x\n", bits); + *REG32(ARM_CONTROL0) = (*REG32(ARM_CONTROL0) & ~(ARM_C0_BRESP1|ARM_C0_BRESP2)) | bits; + udelay(30); +} + +void bridgeCycleBresp(void) { + puts("cycling through bresp bits ..."); + for (unsigned int i = 0; i < sizeof(g_BrespTab)/sizeof(g_BrespTab[0]); i++) { + bridgeWriteBresp(g_BrespTab[i]); + } +} + +void bridgeStart(bool cycleBrespBits) { + puts("setting up async bridge ..."); + + if (cycleBrespBits) { + *REG32(PM_PROC) |= PM_PASSWORD | ~PM_PROC_ARMRSTN_CLR; + bridgeCycleBresp(); + *REG32(PM_PROC) |= PM_PASSWORD | ~PM_PROC_ARMRSTN_CLR; + + udelay(300); + } + + puts("starting async bridge now!"); + *REG32(ARM_CONTROL1) &= ~ARM_C1_REQSTOP; + udelay(300); + + if (!cycleBrespBits) { + *REG32(PM_PROC) |= PM_PASSWORD | ~PM_PROC_ARMRSTN_CLR; + } + + printf("bridge init done, PM_PROC is now: 0x%X!\n", *REG32(PM_PROC)); +} + +APP_START(arm) + .init = arm_init, +// .entry = arm_entry, +APP_END diff --git a/platform/bcm28xx/arm/payload.S b/platform/bcm28xx/arm/payload.S new file mode 100644 index 0000000000..7f32120f21 --- /dev/null +++ b/platform/bcm28xx/arm/payload.S @@ -0,0 +1,6 @@ +.data +.global arm_payload_start +arm_payload_start: +.incbin "../../../armstart.bin" +.global arm_payload_end +arm_payload_end: diff --git a/platform/bcm28xx/arm/rules.mk b/platform/bcm28xx/arm/rules.mk new file mode 100644 index 0000000000..2660ef6691 --- /dev/null +++ b/platform/bcm28xx/arm/rules.mk @@ -0,0 +1,7 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) +MODULE := $(LOCAL_DIR) +MODULE_SRCS += $(LOCAL_DIR)/arm.c $(LOCAL_DIR)/payload.S + +MODULES += platform/bcm28xx/power + +include make/module.mk diff --git a/platform/bcm28xx/bootcode.ld b/platform/bcm28xx/bootcode.ld new file mode 100644 index 0000000000..751026b59a --- /dev/null +++ b/platform/bcm28xx/bootcode.ld @@ -0,0 +1,52 @@ +MEMORY { + ram (rwx) : ORIGIN = 0x80000000, LENGTH = 128K +} +GROUP(-lgcc) +SECTIONS { + _start = .; + .vectorTable : { + . = 0x0; + *(.data.vectorTable) + } + .text : { + _text = .; + *(.text.start) + *(.text) + *(.text.*) + *(.gnu.warning) + _etext = .; + } + + .rodata : { + *(.rodata) + *(.rodata.*) + _erodata = .; + } + + .init_array : { + . = ALIGN(16); + PROVIDE(__ctor_list = .); + KEEP(*(.init_array)) + KEEP(*(.init_array.*)) + KEEP(*(.ctors)) + KEEP(*(.ctors.*)) + __ctor_end = .; + } + + .data : { + *(.data) + _edata = .; + } + + .bss : { + . = ALIGN(4); + _fbss = .; + *(.bss) + *(COMMON) + . = ALIGN(4); + _ebss = .; + _end = .; + } + _fstack = ORIGIN(ram) + LENGTH(ram) - 4; +} +/* ASSERT((_end - _start) <= LENGTH(ram), "bss wont fit within L2") */ diff --git a/platform/bcm28xx/dpi/dpi.c b/platform/bcm28xx/dpi/dpi.c new file mode 100644 index 0000000000..b633faea95 --- /dev/null +++ b/platform/bcm28xx/dpi/dpi.c @@ -0,0 +1,230 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int cmd_dpi_start(int argc, const cmd_args *argv); +int cmd_dpi_count(int argc, const cmd_args *argv); +int cmd_dpi_move(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("dpi_start", "start DPI interface", &cmd_dpi_start) +STATIC_COMMAND("dpi_count", "begin counting on framebuffer", &cmd_dpi_count) +STATIC_COMMAND("dpi_move", "move a pixel on the frame", &cmd_dpi_move) +STATIC_COMMAND_END(dpi); + +gfx_surface *framebuffer; +int width; +int height; +int stride; +timer_t updater; +uint8_t count; +uint32_t count2; + +#define HYPERPIXEL + +int cmd_dpi_start(int argc, const cmd_args *argv) { + hvs_initialize(); + + struct pv_timings t; +#ifdef HYPERPIXEL + t.vfp = 15; + t.vsync = 113; + t.vbp = 15; + t.vactive = 800; + + t.hfp = 10; + t.hsync = 16; + t.hbp = 59; + t.hactive = 480; +#else + t.vfp = 0; + t.vsync = 1; + t.vbp = 0; + t.vactive = 10; + + t.hfp = 0; + t.hsync = 1; + t.hbp = 0; + t.hactive = 10; +#endif + + if (!framebuffer) { + width = t.hactive; + height = t.vactive; + stride = t.hactive; + framebuffer = gfx_create_surface(NULL, width, height, width, GFX_FORMAT_ARGB_8888); + } + for (int x=0; x< height; x++) { + for (int y=0; y < width; y++) { + gfx_putpixel(framebuffer, x, y, (0xff<<24) | (y << 16) | (y << 8) | y); + } + } + hvs_configure_channel(0, width, height, true); + + int list_start = display_slot; + hvs_add_plane(framebuffer, 0, 0, false); + hvs_terminate_list(); + + *REG32(SCALER_DISPLIST0) = list_start; + *REG32(SCALER_DISPLIST1) = list_start; + *REG32(SCALER_DISPLIST2) = list_start; + + + // 0x200 means clock/2 +#ifdef HYPERPIXEL + *REG32(CM_DPIDIV) = CM_PASSWORD | (0xe00 << 4); + *REG32(CM_DPICTL) = CM_PASSWORD | CM_DPICTL_KILL_SET | CM_SRC_PLLC_CORE0; + while (*REG32(CM_DPICTL) & CM_DPICTL_BUSY_SET) {}; + *REG32(CM_DPICTL) = CM_PASSWORD | CM_DPICTL_ENAB_SET | CM_SRC_PLLC_CORE0; + while (*REG32(CM_DPICTL) & CM_DPICTL_BUSY_SET) {}; +#else + *REG32(CM_DPIDIV) = CM_PASSWORD | (0xf00 << 4); + *REG32(CM_DPICTL) = CM_PASSWORD | CM_DPICTL_KILL_SET | CM_SRC_OSC; + while (*REG32(CM_DPICTL) & CM_DPICTL_BUSY_SET) {}; + *REG32(CM_DPICTL) = CM_PASSWORD | CM_DPICTL_ENAB_SET | CM_SRC_OSC; + while (*REG32(CM_DPICTL) & CM_DPICTL_BUSY_SET) {}; +#endif + printf("DPI clock set\n"); + int rate = measure_clock(17); + printf("DPI clock measured at %d\n", rate); + + + setup_pixelvalve(&t, 0); + + int dpi_output_format; +#ifdef HYPERPIXEL + dpi_output_format = 0x7f226; +#else + dpi_output_format = 0x6; +#endif + int format = (dpi_output_format & 0xf) - 1; + int rgb_order = (dpi_output_format >> 4) & 0xf; + + int output_enable_mode = (dpi_output_format >> 8) & 0x1; + int invert_pixel_clock = (dpi_output_format >> 9) & 0x1; + + int hsync_disable = (dpi_output_format >> 12) & 0x1; + int vsync_disable = (dpi_output_format >> 13) & 0x1; + int output_enable_disable = (dpi_output_format >> 14) & 0x1; + + int hsync_polarity = (dpi_output_format >> 16) & 0x1; + int vsync_polarity = (dpi_output_format >> 17) & 0x1; + int output_enable_polarity = (dpi_output_format >> 18) & 0x1; + + int hsync_phase = (dpi_output_format >> 20) & 0x1; + int vsync_phase = (dpi_output_format >> 21) & 0x1; + int output_enable_phase = (dpi_output_format >> 22) & 0x1; + + uint32_t control_word = DPI_ENABLE; + + printf("format: %d\n", format); + control_word |= FORMAT(format); + + printf("rgb order: %d\n", rgb_order); + control_word |= ORDER(rgb_order); + + if (output_enable_mode) { + puts("output enable mode"); + control_word |= DPI_OUTPUT_ENABLE_MODE; + } + if (invert_pixel_clock) { + puts("invert pixel clock"); + control_word |= DPI_PIXEL_CLK_INVERT; + } + if (hsync_disable) { + puts("hsync disable"); + control_word |= DPI_HSYNC_DISABLE; + } + if (vsync_disable) { + puts("vsync disable"); + control_word |= DPI_VSYNC_DISABLE; + } + if (output_enable_disable) { + puts("output_enable_disable"); + } + if (hsync_polarity) { + puts("hsync polarity"); + } + if (vsync_polarity) { + puts("vsync polarity"); + } + if (output_enable_polarity) { + puts("output_enable_polarity"); + } + if (hsync_phase) { + puts("hsync_phase"); + } + if (vsync_phase) { + puts("vsync_phase"); + } + if (output_enable_phase) { + puts("output_enable_phase"); + } + + + *REG32(DPI_C) = control_word; +#ifdef HYPERPIXEL + for (int x=0; x<26; x++) { + if (x == 10) {} + else if (x == 11) {} + else if (x == 18) {} + else if (x == 19) {} + else gpio_config(x, kBCM2708Pinmux_ALT2); + } +#elif defined(AUTO) + for (int x=0; x<28; x++) { + if ((x == 2) && vsync_disable) {} + else if ((x == 3) && hsync_disable) {} + else if (x == 14) {} + else gpio_config(x, kBCM2708Pinmux_ALT2); + } +#else + gpio_config(0, kBCM2708Pinmux_ALT2); // pixel-clock + gpio_config(2, kBCM2708Pinmux_ALT2); // vsync + gpio_config(3, kBCM2708Pinmux_ALT2); // hsync + gpio_config(4, kBCM2708Pinmux_ALT2); // D0 + gpio_config(5, kBCM2708Pinmux_ALT2); // D1 +#endif + return 0; +} + +static enum handler_return updater_entry(struct timer *t, lk_time_t now, void *arg) { + for (int y=0; y +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define logf(fmt, ...) { print_timestamp(); printf("[DWC2:%s]: "fmt, __FUNCTION__, ##__VA_ARGS__); } + +static void dwc_mdio_write(uint8_t reg, uint16_t val) { + //printf("usb MDIO 0x%x <- 0x%x\n", reg, val); + *REG32(USB_GMDIOGEN) = 0xffffffff; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} + + *REG32(USB_GMDIOGEN) = (reg & 0x1f) << 18 | 0x50020000 | val; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} + + *REG32(USB_GMDIOGEN) = 0; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} +} + +static uint16_t dwc_mdio_read(uint8_t reg) { + *REG32(USB_GMDIOGEN) = 0xffffffff; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} + + *REG32(USB_GMDIOGEN) = (reg & 0x1f) << 18 | 0x60020000; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} + + *REG32(USB_GMDIOGEN) = 0; + while ((*REG32(USB_GMDIOCSR) & 0x80000000) != 0) {} + + uint16_t val = *REG32(USB_GMDIOCSR) & 0xffff; + //printf("usb MDIO 0x%x -> 0x%x\n", reg, val); + return val; +} + +static void dwc_configure_phy(void) { + puts("phy configure"); + *REG32(USB_GMDIOCSR) = 0x40000; + dwc_mdio_write(0x19, 4); + dwc_mdio_write(0x18, 0x342); + dwc_mdio_write(0x1d, 4); + dwc_mdio_write(0x15, 0x111); + + int a, b; + if (true) { + // "fast" crystal (19.2mhz) + a = 0x32; + b = 1; + } else { + // "slow" crystal + a = 0x140; + b = 9; + } + dwc_mdio_write(0x17, b << 12 | 0x600 | a); + while ((dwc_mdio_read(0x1b) & 0x80) == 0) {} + *REG32(USB_GVBUSDRV) &= 0xffffff7f; + + dwc_mdio_write(0x1e, 0x8000); + dwc_mdio_write(0x1d, 0x4000); + dwc_mdio_write(0x19, 0xc004); + dwc_mdio_write(0x20, 0x1c2f); + dwc_mdio_write(0x22, 0x100); + dwc_mdio_write(0x24, 0x10); +} + +static void dwc_start(void) { + puts("usb reset"); + + // core soft reset + *REG32(USB_GRSTCTL) = BIT(0); + while ((*REG32(USB_GRSTCTL) & BIT(0)) != 0) {} + + // hclk soft reset + *REG32(USB_GRSTCTL) = BIT(1); + while ((*REG32(USB_GRSTCTL) & BIT(1)) != 0) {} + + // flush tx fifo 1 + *REG32(USB_GRSTCTL) = 0x420; + while ((*REG32(USB_GRSTCTL) & 0x20) != 0) {} + + // flush rx fifo + *REG32(USB_GRSTCTL) = 0x10; + while ((*REG32(USB_GRSTCTL) & 0x10) != 0) {} + + *REG32(USB_GAHBCFG) = BIT(0); + *REG32(USB_GUSBCFG) = 0x40402740; + *REG32(USB_DOEPCTL0) = 0x80000000; + *REG32(USB_DIEPCTL0) = 0x80000000; +} + +static void dwc_clear_fifo(void) { + volatile uint32_t *reg = REG32(USB_DFIFO0); + for (int i=0; i<0x1000; i++) { + reg[i] = 0; + } + + uint32_t config3 = *REG32(USB_GHWCFG3); + uint32_t a = config3 >> 16; + uint32_t b = a; + while (b = b>>1, b != 0) { + a |= b; + } + uint32_t c = a+1; + reg = REG32(0x7e9a0000); + for (unsigned int i=0; ipayload = buffer; + pkt->payload_size = bytes; + pkt->start = 0; + pkt->next = NULL; + pkt->cb = cb; + pkt->has_0byte_tail = (bytes % 64) == 0; + + int do_tx = false; + if (state->in[epNr].packet_queue_head == NULL) { + // no pending packets, can tx right away + do_tx = true; + state->in[epNr].packet_queue_head = pkt; + } + if (state->in[epNr].packet_queue_tail) { + state->in[epNr].packet_queue_tail->next = pkt; + } + state->in[epNr].packet_queue_tail = pkt; + if (do_tx) { + ep_write_in(state, epNr); + } +} + +void ep_write_in(struct dwc_state_t *state, int epNr) { + endpoint_control *ep = GET_IN(epNr); + //printf("control: 0x%x\n", ep->control); + while (ep->control & (1<<31)) {} + int maxPacketSize = 64; // TODO + packet_queue_t *pkt = state->in[epNr].packet_queue_head; + assert(pkt); + //printf("packet(%x): 0x%x+(0x%x/0x%x)\n", (uint32_t)pkt, (uint32_t)pkt->payload, pkt->start, pkt->payload_size); + int bytes = pkt->payload_size - pkt->start; + if ((bytes <= 0) && !pkt->has_0byte_tail) { + //puts("IN packet sent"); + pkt->cb(state, pkt); + packet_queue_t *next = pkt->next; + state->in[epNr].packet_queue_head = next; + if (state->in[epNr].packet_queue_tail == pkt) state->in[epNr].packet_queue_tail = NULL; + free(pkt); + if (next) return ep_write_in(state, epNr); + return; + } + assert(bytes >= 0); + int fullPackets = bytes / maxPacketSize; + int partialPacketSize = bytes - (fullPackets*maxPacketSize); + int packets = fullPackets + ((partialPacketSize==0) ? 0 : 1); + int words = ROUNDUP(bytes,4)/4; + //printf("sending %d full packets and a %d byte partial, %d total, %d words\n", fullPackets, partialPacketSize, packets, words); + if (bytes == 0) pkt->has_0byte_tail = false; + if (epNr == 0) { + packets = 1; + bytes = MIN(maxPacketSize, bytes); + //printf("capped to 1 packet of %d bytes\n", bytes); + } + uint32_t x = (3 << 29) | (packets<<19) | bytes; + + ep->size = x; + ep->control = (1<<31) | // endpoint enable + (1 << 26) | // clear nak + (0 << 22) | // fifo# + (1 << 15) | // USB active endpoint + (0 & 0x3); // max packet size + //dump_endpoint(ep, true); + //ack_ep(ep); + + uint32_t *packet = (uint32_t*)(pkt->payload + pkt->start); + int bytes_sent = 0; + for (int i = 0; i < MIN(maxPacketSize/4, words); i++) { + *REG32(USB_DFIFO0) = packet[i]; + //printf("%d: posted 0x%08x to fifo\n", i, packet[i]); + bytes_sent += 4; + } + pkt->start += bytes_sent; + //printf("%d bytes sent, start now %d\n", bytes_sent, pkt->start); +} + +static fileServerRequest req; // TODO, put on heap + +static void handle_setup_status_out(struct dwc_state_t *state, packet_queue_t *pkt) { + endpoint_control *ep_in = GET_IN(0); + endpoint_control *ep_out = GET_OUT(0); + //puts("setup data IN stage done, on to status OUT..."); + ep_in->size = (3 << 29); + + //puts("\nOUT 0"); + //dump_endpoint(ep_out, false); + ep_out->control |= (1<<31) | // enable OUT0 + (1<<26); // clear NAK + + //puts("IN 0"); + //dump_endpoint(ep, true); + ack_ep(ep_in); + //udelay(5); + //puts("\nIN 0"); + //dump_endpoint(ep, true); + ack_ep(ep_in); + //udelay(5); + + //puts("\nOUT 0"); + //dump_endpoint(ep_out, false); + ack_ep(ep_out); + //dump_endpoint(ep_out, false); +} + +void dwc2_out_cb_free(struct dwc_state_t *state, packet_queue_t *pkt) { + free(pkt->payload); + //puts("nop"); + endpoint_control *ep_out = GET_OUT(0); + ep_out->control |= (1<<31) | // enable OUT0 + (1<<26); // clear NAK +} + +void dwc2_out_cb(struct dwc_state_t *state, packet_queue_t *pkt) { + //puts("nop"); + endpoint_control *ep_out = GET_OUT(0); + ep_out->control |= (1<<31) | // enable OUT0 + (1<<26); // clear NAK +} + +void dwc2_in_cb(struct dwc_state_t *state, packet_queue_t *pkt) { + //puts("in done"); +} + +static void handle_incoming_setup(struct dwc_state_t *state, uint8_t *buf, int size) { + setupData *s = (setupData*)buf; + bool dump = false; + if ((s->bmRequestType == 0x00) && (s->bRequest == 5)) { // set address + *REG32(USB_DCFG) = ((s->wValue & 0x3f) << 4) | (*REG32(USB_DCFG) & 0xfffff80f); + dwc2_ep_queue_in(state, 0, NULL, 0, &dwc2_in_cb); + logf("i am device %d\n", s->wValue); + } else if ((s->bmRequestType == 0x00) && (s->bRequest == 9)) { // set configuration + dwc2_ep_queue_in(state, 0, NULL, 0, &dwc2_in_cb); + logf("set configuration\n"); + } else if ((s->bmRequestType == 0xc0) && (s->wLength == 0x104)) { + endpoint_control *ep_in = GET_IN(0); + endpoint_control *ep_out = GET_OUT(0); + //dump_endpoint(ep, true); + ack_ep(ep_in); + ack_ep(ep_out); + memset(&req, 0, sizeof(req)); + req.cmd = 2; + dwc2_ep_queue_in(state, 0, &req, sizeof(req), &handle_setup_status_out); + } else if (s->bmRequestType == 0x80) { // control-in + //puts("\n\n"); + switch (s->bRequest) { + case 0: // GET STATUS + puts("GET STATUS"); + break; + case 6: { // GET DESCRIPTOR + //puts("GET DESCRIPTOR"); + getDescriptorRequest *req = (getDescriptorRequest*)buf; + switch (req->bDescriptorType) { + case 1: // device descriptor + { + int size = sizeof(defaultDeviceDescriptor); + if (size > req->wLength) size = req->wLength; + dwc2_ep_queue_in(state, 0, &defaultDeviceDescriptor, size, &dwc2_out_cb); + } + break; + case 2: // configuration descriptor + { + int size = state->mainConfigurationDescriptorSize; + if (size > req->wLength) size = req->wLength; + dwc2_ep_queue_in(state, 0, state->mainConfigurationDescriptor, size, &dwc2_out_cb); + } + break; + case 3: // string descriptor + switch (req->wLanguageId) { // language id + case 0: { + uint8_t *reply = malloc(4); + reply[0] = 4; // length + reply[1] = 3; // type string + reply[2] = 0x09; + reply[3] = 0x04; // english us + dwc2_ep_queue_in(state, 0, reply, 4, &dwc2_out_cb_free); + break; + } + case 0x0409:{ + int string_index = req->bDescriptorIndex; + if ((string_index >= 1) && (string_index <= 2)) { + uint8_t *reply = malloc(string_lengths[string_index] + 2); + reply[0] = string_lengths[string_index] + 2; + reply[1] = 3; + memcpy(reply+2, strings[string_index], string_lengths[string_index]); + dwc2_ep_queue_in(state, 0, reply, string_lengths[string_index] + 2, &dwc2_out_cb_free); + } + break; + } + } + break; + } + break; + } + default: + dump = true; + } + } else { + dump = true; + } + if (dump) { + printf("bmRequestType: 0x%x\n", s->bmRequestType); + printf("bRequest: 0x%x\n", s->bRequest); + printf("wValue: 0x%x\n", s->wValue); + printf("wIndex: 0x%x\n", s->wIndex); + printf("wLength: 0x%x\n", s->wLength); + } +} + +static void dump_endpoint(endpoint_control *ep, bool in) { + if (ep->control) { + uint32_t ctl = ep->control; + printf(" CTL: 0x%08x\n", ctl); + if ((ctl >> 15) & 1) puts(" Active"); + if ((ctl >> 17) & 1) puts(" NAK'ing"); + if ((ctl >> 31) & 1) puts(" Enabled"); + uint32_t irq = ep->interrupt; + printf(" INT: 0x%08x\n", irq); + if (irq & 1) puts(" XFERCOMPL"); + if ((irq >> 4) & 1) puts(" INTKNTXFEMP IN Token Received When TxFIFO is Empty"); + if ((irq >> 6) & 1) puts(" INEPNAKEFF IN Endpoint NAK Effective"); + if ((irq >> 13) & 1) puts(" NAKINTRPT NAK Interrupt"); + if (in) { + if ((irq >> 3) & 1) puts(" TIMEOUT"); + if ((irq >> 7) & 1) puts(" TX FIFO empty"); + } else { + if ((irq >> 3) & 1) puts(" SETUP"); + } + printf(" TSIZ: 0x%08x\n", ep->size); + printf(" TXFSTS: 0x%08x\n", ep->fifo_status); + } +} + +static void ack_ep(endpoint_control *ep) { + uint32_t irq = ep->interrupt; + ep->interrupt = irq; + //printf("ACK'd interrupt 0x%x\n", irq); +} + +static void dwc_check_interrupt(struct dwc_state_t *state) { + uint32_t interrupt_status = *REG32(USB_GINTSTS); + //printf("irq: 0x%x\n", interrupt_status & *REG32(USB_GINTMSK)); + if (interrupt_status & BIT(13)) { // enumeration done + *REG32(USB_GINTSTS) = BIT(13); + logf("enumeration done\n"); + GET_OUT(0)->size = (1 << 29) | // 1 setup + (2<<18) | // packet count + 8; // bytes + GET_OUT(0)->control = BIT(31) | BIT(26) | BIT(15); // enable and active + //dumpreg(USB_DSTS); // 808 + interrupt_status = *REG32(USB_GINTSTS); + } + if (interrupt_status & BIT(12)) { // usb reset + *REG32(USB_GINTSTS) = BIT(12); + interrupt_status = *REG32(USB_GINTSTS); + + for (int epNr = 0; epNr < 5; epNr++) { + endpoint_control *ep = GET_OUT(epNr); + ep->control = BIT(31); // enable + } + GET_OUT(0)->size = (1 << 29) | // 1 setup + (2<<18) | // packet count + 8; // bytes + GET_OUT(0)->control = BIT(31) | BIT(26) | BIT(15); // enable and active + + // flush tx fifo 1 + *REG32(USB_GRSTCTL) = 0x420; + while ((*REG32(USB_GRSTCTL) & 0x20) != 0) {} + + // flush rx fifo + *REG32(USB_GRSTCTL) = 0x10; + while ((*REG32(USB_GRSTCTL) & 0x10) != 0) {} + + *REG32(USB_DAINTMSK) = BIT(16) | BIT(0); // allow irq on in0 and out0 + *REG32(USB_DOEPMSK) = BIT(3) | BIT(0); // allow irq on xfer complete and timeout + *REG32(USB_DIEPMSK) = BIT(3) | BIT(0); // allow irq on xfer complete and timeout + + GET_IN(0)->control = BIT(30); // disable IN-0, no data to send yet + } + if (interrupt_status & BIT(11)) { // usb suspend + *REG32(USB_GINTSTS) = BIT(11); + interrupt_status = *REG32(USB_GINTSTS); + //puts("suspend"); + } + while (interrupt_status & USB_GINTSTS_RXFLVL) { + uint32_t receive_status = *REG32(USB_GRXSTSP); + //printf("USB_GRXSTSP:\t 0x%x\n", receive_status); + //printf(" CHEPNUM: %d\n", receive_status & 0xf); + int packet_size = (receive_status >> 4) & 0x7ff; + //printf(" BCNT: %d\n", packet_size); + //printf(" DPID: %d\n", (receive_status >> 15) & 0x3); + int packet_status = (receive_status >> 17) & 0xf; + //printf(" PKTSTS: %d %s\n", packet_status, packet_status_names[packet_status]); + //printf(" FN: %d\n", (receive_status >> 21) & 0xf); + + int words = ROUNDUP(packet_size, 4) / 4; + uint32_t *dest = (uint32_t*)packet_buffer; + for (int i=0; i> i) & 1) { + //printf("IN %d irq\n", i); + ep = GET_IN(i); + //dump_endpoint(ep, true); + uint32_t irq = ep->interrupt; + //printf("acking irq bits 0x%x\n", irq); + ep->interrupt = irq; + if (irq & 1) { + ep_write_in(state, i); + } + } + } + for (int i=16; i<32; i++) { + if ((daint >> i) & 1) { + ep = (endpoint_control*)((USB_BASE + 0x0b00) + (i-16) * 0x20); + //printf("OUT %d irq\n", i - 16); + //dump_endpoint(ep, false); + uint32_t irq = ep->interrupt; + //printf("acking irq bits 0x%x\n", irq); + ep->interrupt = irq; + } + } + daint = *REG32(USB_DAINT); + } +} + +static int cmd_dwc_dump(int argc, const cmd_args *argv) { + uint32_t t; + endpoint_control *ep = 0; + + dumpreg(USB_GOTGCTL); // 0 + if (t & BIT(16)) puts(" 16: B-device mode"); + if (t & BIT(18)) puts(" 18: A-session valid (host only)"); + if (t & BIT(19)) puts(" 19: B-session valid (device only)"); + dumpreg(USB_GAHBCFG); // 8 + dumpreg(USB_GUSBCFG); // c + dumpreg(USB_GINTSTS); // 14 + printf(" CURMOD: %d\n", t & 1); + printf(" MODEMIS: %d\n", (t >> 1) & 1); + printf(" OTGINT: %d\n", (t >> 2) & 1); + printf(" SOF: %d\n", (t >> 3) & 1); + printf(" RXFLVL: %d\n", (t >> 4) & 1); + printf(" NPTXFEMP: %d\n", (t >> 5) & 1); + printf(" GINNAKEFF: %d\n", (t >> 6) & 1); + printf(" GOUTNAKEFF: %d\n", (t >> 7) & 1); + printf(" unused: %d\n", (t >> 8) & 0x3); + printf(" ERLYSUSP: %d\n", (t >> 10) & 1); + printf(" USBSUSP: %d\n", (t >> 11) & 1); + printf(" USBRST: %d\n", (t >> 12) & 1); + printf(" ENUMDONE: %d\n", (t >> 13) & 1); + printf(" ISOOUTDROP: %d\n", (t >> 14) & 1); + printf(" EOPF: %d\n", (t >> 15) & 1); + printf(" unparsed: %d\n", (t >> 16) & 0xffff); + dumpreg(USB_GINTMSK); // 18 + printf("masked irq's: 0x%x\n", *REG32(USB_GINTSTS) & ~(*REG32(USB_GINTMSK))); + dumpreg(USB_GHWCFG1); + dumpreg(USB_GHWCFG2); + dumpreg(USB_GHWCFG3); + dumpreg(USB_GHWCFG4); + if ((t >> 25) & 1) puts(" dedicated transmit fifo enabled"); + dumpreg(USB_DCFG); // 800 + dumpreg(USB_DCTL); // 804 + dumpreg(USB_DSTS); // 808 + dumpreg(USB_DIEPMSK); // 810 + dumpreg(USB_DOEPMSK); // 814 + dumpreg(USB_DAINT); // 818 + dumpreg(USB_DAINTMSK); // 81c + for (int i=0; i<3; i++) { + printf("IN%d\n", i); + ep = (endpoint_control*)((USB_BASE + 0x0900) + i * 0x20); + dump_endpoint(ep, true); + } + for (int i=0; i<3; i++) { + printf("OUT%d\n", i); + ep = (endpoint_control*)((USB_BASE + 0x0b00) + i * 0x20); + dump_endpoint(ep, false); + } + return 0; +} + +static enum handler_return dwc_irq(struct dwc_state_t *state) { + lk_bigtime_t start = current_time_hires(); + //logmsg("dwc irq"); + dwc_check_interrupt(state); + lk_bigtime_t end = current_time_hires(); + lk_bigtime_t spent = end - start; + //logmsg("done"); + if (spent > 20) logf("irq time: %lld\n", spent); + return INT_NO_RESCHEDULE; +} + +static struct dwc_state_t dwc_state; + +static void dwc2_init(const struct app_descriptor *app) { + uint32_t t; + logf("dwc2_init\n"); + power_up_usb(); + + memset(&dwc_state, 0, sizeof(dwc_state)); + dwc_state.mainConfigurationDescriptorSize = sizeof(defaultConfigurationDescriptor) + sizeof(defaultInterfaceDescriptor) + sizeof(ep0Descriptor) + sizeof(ep1Descriptor); + dwc_state.mainConfigurationDescriptor = malloc(dwc_state.mainConfigurationDescriptorSize); + + int pos = 0; + memcpy(dwc_state.mainConfigurationDescriptor + pos, &defaultConfigurationDescriptor, sizeof(defaultConfigurationDescriptor)); + pos += sizeof(defaultConfigurationDescriptor); + + memcpy(dwc_state.mainConfigurationDescriptor + pos, &defaultInterfaceDescriptor, sizeof(defaultInterfaceDescriptor)); + pos += sizeof(defaultInterfaceDescriptor); + + memcpy(dwc_state.mainConfigurationDescriptor + pos, &ep0Descriptor, sizeof(ep0Descriptor)); + pos += sizeof(ep0Descriptor); + + memcpy(dwc_state.mainConfigurationDescriptor + pos, &ep1Descriptor, sizeof(ep1Descriptor)); + pos += sizeof(ep1Descriptor); + assert(pos == dwc_state.mainConfigurationDescriptorSize); + + register_int_handler(DWC_IRQ, dwc_irq, &dwc_state); + unmask_interrupt(DWC_IRQ); + + dwc_configure_phy(); + dwc_clear_fifo(); + dwc_start(); + + //dumpreg(USB_GAHBCFG); + *REG32(USB_GINTMSK) = + BIT(19) | BIT(18) | BIT(17) | + BIT(13) | BIT(12) | BIT(11) | BIT(4) + | BIT(2) + ; + *REG32(USB_DIEPMSK) = (1<<4) | (1<<3) | (1<<0); + + *REG32(USB_DCFG) = (1 << 18) | // in endpoint mismatch count + (1 << 11) | // periodic frame interval interrupt + 3; // full speed + //0; // high speed 2.0 + + *REG32(USB_GRXFSIZ) = 0x200; + + volatile uint32_t *reg = REG32(USB_DIEPTXF1); + int start = 0x300; + for (int i = 0; i< 7; i++) { + t = start | (0x100 << 16); + start = start + 0x100; + reg[i] = t; + } +} + +static void dwc2_entry(const struct app_descriptor *app, void *args) { +} + +APP_START(dwc2) + .init = dwc2_init, + .entry = dwc2_entry, +APP_END diff --git a/platform/bcm28xx/dwc2/include/platform/bcm28xx/dwc2.h b/platform/bcm28xx/dwc2/include/platform/bcm28xx/dwc2.h new file mode 100644 index 0000000000..5ed1ea0adb --- /dev/null +++ b/platform/bcm28xx/dwc2/include/platform/bcm28xx/dwc2.h @@ -0,0 +1,61 @@ +#pragma once + +#define USB_BASE (BCM_PERIPH_BASE_VIRT + 0x980000) + +#define USB_GOTGCTL (USB_BASE + 0x0000) +#define USB_GAHBCFG (USB_BASE + 0x0008) +#define USB_GUSBCFG (USB_BASE + 0x000c) +#define USB_GRSTCTL (USB_BASE + 0x0010) +#define USB_GINTSTS (USB_BASE + 0x0014) +#define USB_GINTSTS_RXFLVL (1 << 4) +#define USB_GINTMSK (USB_BASE + 0x0018) +#define USB_GRXSTSP (USB_BASE + 0x0020) +#define USB_GRXFSIZ (USB_BASE + 0x0024) +#define USB_GHWCFG1 (USB_BASE + 0x0044) +#define USB_GHWCFG2 (USB_BASE + 0x0048) +#define USB_GHWCFG3 (USB_BASE + 0x004c) +#define USB_GHWCFG4 (USB_BASE + 0x0050) +#define USB_GMDIOCSR (USB_BASE + 0x0080) +#define USB_GMDIOGEN (USB_BASE + 0x0084) +#define USB_GVBUSDRV (USB_BASE + 0x0088) +#define USB_DIEPTXF1 (USB_BASE + 0x0104) +#define USB_DCFG (USB_BASE + 0x0800) +#define USB_DCTL (USB_BASE + 0x0804) +#define USB_DSTS (USB_BASE + 0x0808) +#define USB_DIEPMSK (USB_BASE + 0x0810) +#define USB_DOEPMSK (USB_BASE + 0x0814) +#define USB_DAINT (USB_BASE + 0x0818) +#define USB_DAINTMSK (USB_BASE + 0x081c) + +#define USB_DIEPCTL0 (USB_BASE + 0x0900) +#define USB_DIEPINT0 (USB_BASE + 0x0908) + +#define USB_DIEPCTL1 (USB_BASE + 0x0920) +#define USB_DIEPINT1 (USB_BASE + 0x0928) + +#define USB_DIEPCTL2 (USB_BASE + 0x0940) + +#define USB_DOEPCTL0 (USB_BASE + 0x0b00) +#define USB_DOEPINT0 (USB_BASE + 0x0b08) + +#define USB_DOEPCTL1 (USB_BASE + 0x0b20) +#define USB_DOEPINT1 (USB_BASE + 0x0b28) + +#define USB_DOEPCTL2 (USB_BASE + 0x0b40) +#define USB_DOEPINT2 (USB_BASE + 0x0b48) + +#define USB_DOEPCTL3 (USB_BASE + 0x0b60) +#define USB_DOEPINT3 (USB_BASE + 0x0b68) + +#define USB_DOEPCTL4 (USB_BASE + 0x0b80) +#define USB_DOEPINT4 (USB_BASE + 0x0b88) +#define USB_DOEPINT5 (USB_BASE + 0x0ba8) +#define USB_DOEPINT6 (USB_BASE + 0x0bc8) +#define USB_DOEPINT7 (USB_BASE + 0x0be8) +#define USB_DOEPINT8 (USB_BASE + 0x0c08) +#define USB_DOEPINT9 (USB_BASE + 0x0c28) + +#define USB_DFIFO0 (USB_BASE + 0x1000) +#define USB_DFIFO1 (USB_BASE + 0x2000) + +#define DWC_IRQ 9 diff --git a/platform/bcm28xx/dwc2/rules.mk b/platform/bcm28xx/dwc2/rules.mk new file mode 100644 index 0000000000..2cc809da8f --- /dev/null +++ b/platform/bcm28xx/dwc2/rules.mk @@ -0,0 +1,13 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/dwc2.c \ + +# for 16bit chars in usb +GLOBAL_CFLAGS += -fshort-wchar + +MODULES += platform/bcm28xx/power + +include make/module.mk diff --git a/platform/bcm28xx/genet.c b/platform/bcm28xx/genet.c new file mode 100644 index 0000000000..a49ab780a4 --- /dev/null +++ b/platform/bcm28xx/genet.c @@ -0,0 +1,27 @@ +// based on drivers/net/ethernet/broadcom/genet/bcmgenet.c from linux +// for PHY control, look at the cmd_bits variable in drivers/net/ethernet/broadcom/genet/bcmmii.c + +#include +#include +#include +#include +#include + +static int cmd_genet_dump(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("dump_genet", "print genet information", &cmd_genet_dump) +STATIC_COMMAND_END(genet); + +#define SYS_REV_CTRL (GENET_BASE + 0x0) + +static int cmd_genet_dump(int argc, const cmd_args *argv) { + uint32_t reg = *REG32(SYS_REV_CTRL); + uint8_t major = (reg >> 24 & 0x0f); + if (major == 6) major = 5; + else if (major == 5) major = 4; + else if (major == 0) major = 1; + + dprintf(INFO, "found GENET controller version %d\n", major); + return 0; +} diff --git a/platform/bcm28xx/gpio.c b/platform/bcm28xx/gpio.c index bc736f9610..94bcfed7de 100644 --- a/platform/bcm28xx/gpio.c +++ b/platform/bcm28xx/gpio.c @@ -9,6 +9,11 @@ #include #include #include +#include +#include +#include +#include +#include #define NUM_PINS 54 #define BITS_PER_REG 32 @@ -16,6 +21,18 @@ #define PINS_PER_REG (BITS_PER_REG / BITS_PER_PIN) #define GPIOREG(base, nr) (REG32(base) + (nr / BITS_PER_REG)) +static int cmd_gpio_mode(int argc, const cmd_args *argv); +static int cmd_gpio_write(int argc, const cmd_args *argv); +static int cmd_gpio_dump_state(int argc, const cmd_args *argv); +static int cmd_gpio_test(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("gpio_mode", "set the gpio alt mode", &cmd_gpio_mode) +STATIC_COMMAND("gpio_write", "set gpio output", &cmd_gpio_write) +STATIC_COMMAND("gpio_dump_state", "dump current gpio state", &cmd_gpio_dump_state) +STATIC_COMMAND("gpio_test", "test gpio pullup/down", &cmd_gpio_test) +STATIC_COMMAND_END(gpio); + int gpio_config(unsigned nr, unsigned flags) { unsigned mask = 0x7; if (nr >= NUM_PINS || flags & ~mask) @@ -28,6 +45,17 @@ int gpio_config(unsigned nr, unsigned flags) { return 0; } +int gpio_get_config(unsigned nr) { + unsigned mask = 0x7; + if (nr >= NUM_PINS) + return -EINVAL; + unsigned register_number = nr / PINS_PER_REG; + unsigned offset = (nr % PINS_PER_REG) * BITS_PER_PIN; + unsigned shifted_mask = mask << offset; + volatile uint32_t *reg = REG32(GPIO_GPFSEL0) + register_number; + return (*reg & shifted_mask) >> offset; +} + void gpio_set(unsigned nr, unsigned on) { unsigned offset = nr % BITS_PER_REG; *GPIOREG(on ? GPIO_GPSET0 : GPIO_GPCLR0, nr) = 1 << offset; @@ -37,3 +65,129 @@ int gpio_get(unsigned nr) { unsigned offset = nr % BITS_PER_REG; return (*GPIOREG(GPIO_GPLEV0, nr) & (1 << offset)) >> offset; } + +#ifndef RPI4 +// rpi1-3 models +void gpio_set_pull(unsigned nr, enum pull_mode mode) { +} +void gpio_apply_batch(struct gpio_pull_batch *batch) { + for (enum pull_mode mode = 0; mode <=2; mode++) { + if (batch->bank[mode][0] | batch->bank[mode][1]) { + *REG32(GPIO_GPPUD) = mode; + udelay(500); + *REG32(GPIO_GPPUDCLK0) = batch->bank[mode][0]; + *REG32(GPIO_GPPUDCLK1) = batch->bank[mode][1]; + udelay(500); + *REG32(GPIO_GPPUDCLK0) = 0; + *REG32(GPIO_GPPUDCLK1) = 0; + *REG32(GPIO_GPPUD) = 0; + udelay(500); + } + } +} +#else +// rpi4 +int gpio_get_pull(unsigned nr) { + unsigned offset = (nr % 16) * 2; + volatile uint32_t *pull_cfg = REG32(GPIO_2711_PULL); + return (pull_cfg[nr / 16] >> offset) & 0x3; +} +#endif + +static int cmd_gpio_mode(int argc, const cmd_args *argv) { + if (argc != 3) { + printf("usage: gpio_mode 42 (in|out|alt0|alt1|alt2|alt3|alt4|alt5)\n"); + return -1; + } + int mode = 0; + if (strcmp(argv[2].str, "in") == 0) { + mode = 0; + } else if (strcmp(argv[2].str, "out") == 0) { + mode = 1; + } else if (strcmp(argv[2].str, "alt0") == 0) { + mode = 4; + } else if (strcmp(argv[2].str, "alt1") == 0) { + mode = 5; + } else if (strcmp(argv[2].str, "alt2") == 0) { + mode = 6; + } else if (strcmp(argv[2].str, "alt3") == 0) { + mode = 7; + } else if (strcmp(argv[2].str, "alt4") == 0) { + mode = 3; + } else if (strcmp(argv[2].str, "alt5") == 0) { + mode = 2; + } else { + printf("unknown mode %s\n", argv[2].str); + return -1; + } + gpio_config(argv[1].u, mode); + printf("done\n"); + return 0; +} + +static int cmd_gpio_write(int argc, const cmd_args *argv) { + if (argc != 3) { + printf("usage: gpio_write 42 1\n"); + return -1; + } + gpio_set(argv[1].u, argv[2].u); + printf("done\n"); + return 0; +} + + +const char *mode_names[] = { + [kBCM2708PinmuxIn] = "IN", + [kBCM2708PinmuxOut] = "OUT", + [kBCM2708Pinmux_ALT5] = "ALT5", + [kBCM2708Pinmux_ALT4] = "ALT4", + [kBCM2708Pinmux_ALT0] = "ALT0", + [kBCM2708Pinmux_ALT1] = "ALT1", + [kBCM2708Pinmux_ALT2] = "ALT2", + [kBCM2708Pinmux_ALT3] = "ALT3", + [8] = "" +}; + +const char *levels[] = { "LOW", "HIGH" }; + +const char *pull_names[] = { "--", "^^", "\\/", "invalid", "" }; + +static int cmd_gpio_dump_state(int argc, const cmd_args *argv) { + for (int i=0; i<32; i++) { + int lflags, rflags = 8; + lflags = gpio_get_config(i); + int l_level = gpio_get(i); + int r_level = gpio_get(i+32); + if ((i+32) < NUM_PINS) rflags = gpio_get_config(i+32); + +#if RPI4 + int l_pull = gpio_get_pull(i); + int r_pull = gpio_get_pull(i+32); +#else + int l_pull = 4, r_pull = 4; +#endif + + printf("GPIO%02d %4s %s %4s | %4s %s %4s GPIO%02d\n", i, mode_names[lflags], pull_names[l_pull], levels[l_level], + levels[r_level], pull_names[r_pull], mode_names[rflags], i+32); + } + return 0; +} + +static int cmd_gpio_test(int argc, const cmd_args *argv) { + uint8_t pins[] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27 }; + for (unsigned int i=0; i +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include + +static int cmd_hvs_dance(int argc, const cmd_args *argv); +static int cmd_hvs_limit(int argc, const cmd_args *argv); +static int cmd_hvs_delay(int argc, const cmd_args *argv); +static int cmd_dance_update(int argc, const cmd_args *argv); +static int cmd_dance_list(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("dance", "make the HVS dance in another direction", &cmd_hvs_dance) +STATIC_COMMAND("l", "limit sprites", &cmd_hvs_limit) +STATIC_COMMAND("d", "delay updates", &cmd_hvs_delay) +STATIC_COMMAND("u", "update", &cmd_dance_update) +STATIC_COMMAND("dance_list", "list", &cmd_dance_list) +STATIC_COMMAND_END(hvs_dance); + +gfx_surface *fb; +void (*background)(void); + +struct item { + signed int x, y; + signed int xd, yd; +}; + +#define ITEMS 580 +struct item items[ITEMS]; +uint32_t sprite_limit = 2; +int delay = 0; + +int32_t screen_width, screen_height; + +#define SCALED + +void do_frame_update(int frame) { + if (delay != 0) { + if ((frame % delay) != 0) return; + } + if ((display_slot + (sprite_limit * 14) + 1) > 4096) { + //printf("early dlist loop %d\n", display_slot); + display_slot = 0; + } + + int w,h; +#ifdef SCALED + w = 100; + h = 100; +#else + w = fb->width; + h = fb->height; +#endif + + int start = display_slot; + background(); + for (unsigned int i=0; i < sprite_limit; i++) { + struct item *it = &items[i]; + if (it->x > (screen_width - w)) it->xd *= -1; + if (it->y > (screen_height - h)) it->yd *= -1; + + it->x += it->xd; + it->y += it->yd; + + if (it->x < 0) { + it->x *= -1; + it->xd *= -1; + } + if (it->y < 0) { + it->y *= -1; + it->yd *= -1; + } + if (it->x > screen_width) { + it->x -= screen_width; + it->xd *= -1; + } + if (it->y > screen_height) { + it->y -= screen_height; + it->yd *= -1; + } + +#if 0 + if (it->x < 0) { + it->x = it->x * -1; + it->xd *= -1; + } + if (it->y < 0) { + it->y = it->y * -1; + it->yd *= -1; + } +#endif +#ifdef SCALED + hvs_add_plane_scaled(fb, it->x, it->y, w, h, false); +#else + hvs_add_plane(fb, it->x, it->y, false); +#endif + } + hvs_terminate_list(); + + if (display_slot > 4096) { + printf("dlist overflow!!!: %d\n", display_slot); + display_slot = 0; + do_frame_update(frame); + return; + } + + *REG32(SCALER_DISPLIST1) = start; + + if (display_slot > 4000) { + display_slot = 0; + //puts("dlist loop"); + } +} + +static int cmd_dance_list(int argc, const cmd_args *argv) { + for (unsigned int i=0; i < sprite_limit; i++) { + struct item *it = &items[i]; + printf("%d: %dx%d, rate %dx%d\n", i, it->x, it->y, it->xd, it->yd); + } + return 0; +} + +static int cmd_dance_update(int argc, const cmd_args *argv) { + do_frame_update(0); + return 0; +} + +uint32_t hsync, hbp, hact, hfp, vsync, vbp, vfps, last_vfps; + +static enum handler_return pv_irq(void *pvnr) { + uint32_t t = *REG32(ST_CLO); + struct hvs_channel *hvs_channels = (struct hvs_channel*)REG32(SCALER_DISPCTRL0); + struct pixel_valve *rawpv = getPvAddr((int)pvnr); + uint32_t stat = rawpv->int_status; + uint32_t ack = 0; + uint32_t stat1 = hvs_channels[1].dispstat; + if (stat & PV_INTEN_HSYNC_START) { + ack |= PV_INTEN_HSYNC_START; + hsync = t; + if ((SCALER_STAT_LINE(stat1) % 5) == 0) { + //hvs_set_background_color(1, 0x0000ff); + } else { + //hvs_set_background_color(1, 0xffffff); + } + } + if (stat & PV_INTEN_HBP_START) { + ack |= PV_INTEN_HBP_START; + hbp = t; + } + if (stat & PV_INTEN_HACT_START) { + ack |= PV_INTEN_HACT_START; + hact = t; + }; + if (stat & PV_INTEN_HFP_START) { + ack |= PV_INTEN_HFP_START; + hfp = t; + } + if (stat & PV_INTEN_VSYNC_START) { + ack |= PV_INTEN_VSYNC_START; + vsync = t; + } + if (stat & PV_INTEN_VBP_START) { + ack |= PV_INTEN_VBP_START; + vbp = t; + } + if (stat & PV_INTEN_VACT_START) { + ack |= PV_INTEN_VACT_START; + } + if (stat & PV_INTEN_VFP_START) { + ack |= PV_INTEN_VFP_START; + last_vfps = vfps; + vfps = t; + hvs_set_background_color(1, 0xff0000); + do_frame_update((stat1 >> 12) & 0x3f); + //printf("line: %d frame: %2d start: %4d ", stat1 & 0xfff, (stat1 >> 12) & 0x3f, *REG32(SCALER_DISPLIST1)); + //uint32_t idle = *REG32(SD_IDL); + //uint32_t total = *REG32(SD_CYC); + //*REG32(SD_IDL) = 0; + //uint64_t idle_percent = ((uint64_t)idle * 100) / ((uint64_t)total); + //printf("sdram usage: %d %d, %lld\n", idle, total, idle_percent); + //printf("HSYNC:%5d HBP:%d HACT:%d HFP:%d VSYNC:%5d VBP:%5d VFPS:%d FRAME:%d\n", t - vsync, t-hbp, t-hact, t-hfp, t-vsync, t-vbp, t-vfps, t-last_vfps); + hvs_set_background_color(1, 0xffffff); + } + if (stat & PV_INTEN_VFP_END) { + ack |= PV_INTEN_VFP_END; + } + if (stat & PV_INTEN_IDLE) { + ack |= PV_INTEN_IDLE; + } + rawpv->int_status = ack; + return INT_NO_RESCHEDULE; +} + +static void dance_scramble(void) { + int w,h; +#ifdef SCALED + w = 100; + h = 100; +#else + w = fb->width; + h = fb->height; +#endif + for (int i=0; ix = (unsigned int)rand() % screen_width; + it->y = (unsigned int)rand() % screen_height; + it->xd = (rand() % 5)+1; + it->yd = (rand() % 5)+1; + if (it->x > (screen_width - w)) it->x = screen_width - fb->width; + if (it->y > (screen_height - h)) it->y = screen_height - fb->height; + } + + items[0].x = 40; + items[0].y = 100; + items[0].xd = 0; + items[0].yd = 0; + +#if 0 + items[1].x = 140; + items[1].y = 0; + items[1].xd = 0; + items[1].yd = 1; +#endif +} + +static int cmd_hvs_dance(int argc, const cmd_args *argv) { + dance_scramble(); + return 0; +} + +static int cmd_hvs_limit(int argc, const cmd_args *argv) { + if (argc == 2) sprite_limit = argv[1].u; + if (sprite_limit > ITEMS) sprite_limit = ITEMS; + return 0; +} + +static int cmd_hvs_delay(int argc, const cmd_args *argv) { + if (argc == 2) delay = argv[1].u; + return 0; +} + +void dance_start(gfx_surface* fbin, int hvs_channel, void (*backgroundcb)(void)) { + fb = fbin; + background = backgroundcb; + gfx_flush(fb); + + hvs_set_background_color(hvs_channel, 0xffffff); + screen_width = (hvs_channels[hvs_channel].dispctrl >> 12) & 0xfff; + screen_height = (hvs_channels[hvs_channel].dispctrl & 0xfff); + printf("detected a %dx%d screen\n", screen_width, screen_height); + + srand(*REG32(ST_CLO)); + dance_scramble(); + if (true) { + puts("setting up pv interrupt"); + int pvnr = 2; + struct pixel_valve *rawpv = getPvAddr(pvnr); + rawpv->int_enable = 0; + rawpv->int_status = 0xff; + setup_pv_interrupt(pvnr, pv_irq, (void*)pvnr); + rawpv->int_enable = PV_INTEN_VFP_START | 0x3f; + //hvs_setup_irq(); + puts("done"); + } +} + +static void dance_init(const struct app_descriptor *app) { +#if 0 + if (!fb) { + fb = gfx_create_surface(NULL, 10, 10, 10, GFX_FORMAT_ARGB_8888); + for (unsigned int i=0; iwidth; i++) { + int r = 0; + if ((i%2) == 0) r = 255; + for (unsigned int j=0; jheight; j++) { + int g = 0; + if ((j%2) == 0) g = 255; + gfx_putpixel(fb, i, j, 0xff000000 | (g << 8) | r); + } + } + } + fb->flush = 0; +#endif + screen_width = 0x500; + screen_height = 0x400; +} + +static void dance_entry(const struct app_descriptor *app, void *args) { + +} + +APP_START(hvs_dance) + .init = dance_init, + .entry = dance_entry, +APP_END diff --git a/platform/bcm28xx/hvs-dance/include/dance.h b/platform/bcm28xx/hvs-dance/include/dance.h new file mode 100644 index 0000000000..02a1506d07 --- /dev/null +++ b/platform/bcm28xx/hvs-dance/include/dance.h @@ -0,0 +1,5 @@ +#pragma once + +#include + +void dance_start(gfx_surface* fbin, int hvs_channel, void (*background)(void)); diff --git a/platform/bcm28xx/hvs-dance/rules.mk b/platform/bcm28xx/hvs-dance/rules.mk new file mode 100644 index 0000000000..472facf336 --- /dev/null +++ b/platform/bcm28xx/hvs-dance/rules.mk @@ -0,0 +1,15 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += \ + platform/bcm28xx/hvs \ + platform/bcm28xx/pixelvalve + +MODULE_SRCS += \ + $(LOCAL_DIR)/dance.c + +GLOBAL_INCLUDES += $(BUILDDIR)/$(LOCAL_DIR) +MODULE_CFLAGS := -O2 + +include make/module.mk diff --git a/platform/bcm28xx/hvs/hvs.c b/platform/bcm28xx/hvs/hvs.c new file mode 100644 index 0000000000..3472f0bce5 --- /dev/null +++ b/platform/bcm28xx/hvs/hvs.c @@ -0,0 +1,351 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// note, 4096 slots total +volatile uint32_t* dlist_memory = REG32(SCALER_LIST_MEMORY); +volatile struct hvs_channel *hvs_channels = (volatile struct hvs_channel*)REG32(SCALER_DISPCTRL0); +int display_slot = 0; +int scaled_layer_count = 0; +timer_t ddr2_monitor; + +enum scaling_mode { + none, + PPF, // upscaling? + TPZ // downscaling? +}; + +struct hvs_channel_config channels[3]; + +static int cmd_hvs_dump(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("hvs_dump", "dump hvs state", &cmd_hvs_dump) +STATIC_COMMAND_END(hvs); + +static uint32_t gfx_to_hvs_pixel_format(gfx_format fmt) { + switch (fmt) { + case GFX_FORMAT_RGB_565: + return HVS_PIXEL_FORMAT_RGB565; + case GFX_FORMAT_RGB_332: + return HVS_PIXEL_FORMAT_RGB332; + case GFX_FORMAT_ARGB_8888: + case GFX_FORMAT_RGB_x888: + return HVS_PIXEL_FORMAT_RGBA8888; + default: + printf("warning, unsupported pixel format: %d\n", fmt); + return 0; + } +} + +void hvs_add_plane(gfx_surface *fb, int x, int y, bool hflip) { + assert(fb); + //printf("rendering FB of size %dx%d at %dx%d\n", fb->width, fb->height, x, y); + dlist_memory[display_slot++] = CONTROL_VALID + | CONTROL_WORDS(7) + | CONTROL_PIXEL_ORDER(HVS_PIXEL_ORDER_ABGR) +// | CONTROL0_VFLIP // makes the HVS addr count down instead, pointer word must be last line of image + | (hflip ? CONTROL0_HFLIP : 0) + | CONTROL_UNITY + | CONTROL_FORMAT(gfx_to_hvs_pixel_format(fb->format)); + dlist_memory[display_slot++] = POS0_X(x) | POS0_Y(y) | POS0_ALPHA(0xff); + dlist_memory[display_slot++] = POS2_H(fb->height) | POS2_W(fb->width); + dlist_memory[display_slot++] = 0xDEADBEEF; // dummy for HVS state + dlist_memory[display_slot++] = (uint32_t)fb->ptr | 0xc0000000; + dlist_memory[display_slot++] = 0xDEADBEEF; // dummy for HVS state + dlist_memory[display_slot++] = fb->stride * fb->pixelsize; +} + +static void write_tpz(unsigned int source, unsigned int dest) { + uint32_t scale = (1<<16) * source / dest; + uint32_t recip = ~0 / scale; + dlist_memory[display_slot++] = scale << 8; + dlist_memory[display_slot++] = recip; +} + +void hvs_add_plane_scaled(gfx_surface *fb, int x, int y, unsigned int width, unsigned int height, bool hflip) { + assert(fb); + if ((x < 0) || (y < 0)) printf("rendering FB of size %dx%d at %dx%d, scaled down to %dx%d\n", fb->width, fb->height, x, y, width, height); + enum scaling_mode xmode, ymode; + if (fb->width > width) xmode = TPZ; + else if (fb->width < width) xmode = PPF; + else xmode = none; + + if (fb->height > height) ymode = TPZ; + else if (fb->height < height) ymode = PPF; + else ymode = none; + + int scl0; + switch ((xmode << 2) | ymode) { + case (PPF << 2) | PPF: + scl0 = SCALER_CTL0_SCL_H_PPF_V_PPF; + break; + case (TPZ << 2) | PPF: + scl0 = SCALER_CTL0_SCL_H_TPZ_V_PPF; + break; + case (PPF << 2) | TPZ: + scl0 = SCALER_CTL0_SCL_H_PPF_V_TPZ; + break; + case (TPZ << 2) | TPZ: + scl0 = SCALER_CTL0_SCL_H_TPZ_V_TPZ; + break; + default: + puts("unsupported scale combonation"); + } + + int start = display_slot; + dlist_memory[display_slot++] = 0 // CONTROL_VALID +// | CONTROL_WORDS(14) + | CONTROL_PIXEL_ORDER(HVS_PIXEL_ORDER_ABGR) +// | CONTROL0_VFLIP // makes the HVS addr count down instead, pointer word must be last line of image + | (hflip ? CONTROL0_HFLIP : 0) + | CONTROL_FORMAT(gfx_to_hvs_pixel_format(fb->format)) + | (scl0 << 5) + | (scl0 << 8); // SCL1 + dlist_memory[display_slot++] = POS0_X(x) | POS0_Y(y) | POS0_ALPHA(0xff); // position word 0 + dlist_memory[display_slot++] = width | (height << 16); // position word 1 + dlist_memory[display_slot++] = POS2_H(fb->height) | POS2_W(fb->width); // position word 2 + dlist_memory[display_slot++] = 0xDEADBEEF; // position word 3, dummy for HVS state + dlist_memory[display_slot++] = (uint32_t)fb->ptr | 0x80000000; // pointer word 0 + dlist_memory[display_slot++] = 0xDEADBEEF; // pointer context word 0 dummy for HVS state + dlist_memory[display_slot++] = fb->stride * fb->pixelsize; // pitch word 0 + dlist_memory[display_slot++] = (scaled_layer_count * 720); // LBM base addr + scaled_layer_count++; + +#if 0 + bool ppf = false; + if (ppf) { + uint32_t xscale = (1<<16) * fb->width / width; + uint32_t yscale = (1<<16) * fb->height / height; + + dlist_memory[display_slot++] = SCALER_PPF_AGC | (xscale << 8); + dlist_memory[display_slot++] = SCALER_PPF_AGC | (yscale << 8); + dlist_memory[display_slot++] = 0xDEADBEEF; //scaling context + } +#endif + + if (xmode == PPF) { + puts("unfinished"); + } + + if (ymode == PPF) { + puts("unfinished"); + } + + if (xmode == TPZ) { + write_tpz(fb->width, width); + } + + if (ymode == TPZ) { + write_tpz(fb->height, height); + dlist_memory[display_slot++] = 0xDEADBEEF; // context for scaling + } + + //printf("entry size: %d, spans 0x%x-0x%x\n", display_slot - start, start, display_slot); + dlist_memory[start] |= CONTROL_VALID | CONTROL_WORDS(display_slot - start); +} + +void hvs_terminate_list(void) { + dlist_memory[display_slot++] = CONTROL_END; + scaled_layer_count = 0; +} + +static enum handler_return hvs_irq(void *unused) { + puts("hvs interrupt"); + return INT_NO_RESCHEDULE; +} + +//#define SD_IDL 0x7ee00018 +//#define SD_CYC 0x7ee00030 + +static void check_sdram_usage(void) { + static float last_time = 1; + uint64_t idle = *REG32(SD_IDL); + uint64_t total = *REG32(SD_CYC); + *REG32(SD_IDL) = 0; + uint32_t idle_percent = (idle * 100) / (total); + float time = ((float)*REG32(ST_CLO)) / 1000000; + uint32_t clock = total / (time - last_time) / 1000 / 1000; + last_time = time; + printf("[%f] DDR2 was idle 0x%x / 0x%x cycles (%d%%) %dMHz\n", time, (uint32_t)idle, (uint32_t)total, idle_percent, clock); +} + +static enum handler_return ddr2_checker(struct timer *unused1, unsigned int unused2, void *unused3) { + check_sdram_usage(); + return INT_NO_RESCHEDULE; +} + +void hvs_initialize() { + timer_initialize(&ddr2_monitor); + //timer_set_periodic(&ddr2_monitor, 500, ddr2_checker, NULL); + *REG32(SCALER_DISPCTRL) &= ~SCALER_DISPCTRL_ENABLE; // disable HVS + *REG32(SCALER_DISPCTRL) = SCALER_DISPCTRL_ENABLE | 0x9a0dddff; // re-enable HVS + for (int i=0; i<3; i++) { + hvs_channels[i].dispctrl = SCALER_DISPCTRLX_RESET; + hvs_channels[i].dispctrl = 0; + hvs_channels[i].dispbkgnd = 0x1020202; // bit 24 + } + + hvs_channels[2].dispbase = BASE_BASE(0) | BASE_TOP(0x7f0); + hvs_channels[1].dispbase = BASE_BASE(0xf10) | BASE_TOP(0x50f0); + hvs_channels[0].dispbase = BASE_BASE(0x800) | BASE_TOP(0xf00); + + hvs_wipe_displaylist(); + + *REG32(SCALER_DISPEOLN) = 0x40000000; +} + +void hvs_setup_irq() { + register_int_handler(33, hvs_irq, NULL); + unmask_interrupt(33); +} + +void hvs_configure_channel(int channel, int width, int height, bool interlaced) { + channels[channel].width = width; + channels[channel].height = height; + channels[channel].interlaced = interlaced; + + hvs_channels[channel].dispctrl = SCALER_DISPCTRLX_RESET; + hvs_channels[channel].dispctrl = SCALER_DISPCTRLX_ENABLE | SCALER_DISPCTRL_W(width) | SCALER_DISPCTRL_H(height); + + hvs_channels[channel].dispbkgnd = SCALER_DISPBKGND_AUTOHS | 0x020202 + | (channels[channel].interlaced ? SCALER_DISPBKGND_INTERLACE : 0); + // the SCALER_DISPBKGND_INTERLACE flag makes the HVS alternate between sending even and odd scanlines +} + +void hvs_wipe_displaylist(void) { + for (int i=0; i<1024; i++) { + dlist_memory[i] = CONTROL_END; + } + display_slot = 0; +} + +static bool bcm_host_is_model_pi4(void) { + return false; +} + +void hvs_print_position0(uint32_t w) { + printf("position0: 0x%x\n", w); + if (bcm_host_is_model_pi4()) { + printf(" x: %d y: %d\n", w & 0x3fff, (w >> 16) & 0x3fff); + } else { + printf(" x: %d y: %d\n", w & 0xfff, (w >> 12) & 0xfff); + } +} +void hvs_print_control2(uint32_t w) { + printf("control2: 0x%x\n", w); + printf(" alpha: 0x%x\n", (w >> 4) & 0xffff); + printf(" alpha mode: %d\n", (w >> 30) & 0x3); +} +void hvs_print_word1(uint32_t w) { + printf(" word1: 0x%x\n", w); +} +void hvs_print_position2(uint32_t w) { + printf("position2: 0x%x\n", w); + printf(" width: %d height: %d\n", w & 0xffff, (w >> 16) & 0xfff); +} +void hvs_print_position3(uint32_t w) { + printf("position3: 0x%x\n", w); +} +void hvs_print_pointer0(uint32_t w) { + printf("pointer word: 0x%x\n", w); +} +void hvs_print_pointerctx0(uint32_t w) { + printf("pointer context word: 0x%x\n", w); +} +void hvs_print_pitch0(uint32_t w) { + printf("pitch word: 0x%x\n", w); +} + +static int cmd_hvs_dump(int argc, const cmd_args *argv) { + printf("SCALER_DISPCTRL: 0x%x\n", *REG32(SCALER_DISPCTRL)); + printf("SCALER_DISPSTAT: 0x%x\n", *REG32(SCALER_DISPSTAT)); + printf("SCALER_DISPEOLN: 0x%08x\n", *REG32(SCALER_DISPEOLN)); + printf("SCALER_DISPLIST0: 0x%x\n", *REG32(SCALER_DISPLIST0)); + uint32_t list1 = *REG32(SCALER_DISPLIST1); + printf("SCALER_DISPLIST1: 0x%x\n", list1); + printf("SCALER_DISPLIST2: 0x%x\n\n", *REG32(SCALER_DISPLIST2)); + for (int i=0; i<3; i++) { + printf("SCALER_DISPCTRL%d: 0x%x\n", i, hvs_channels[i].dispctrl); + printf(" width: %d\n", (hvs_channels[i].dispctrl >> 12) & 0xfff); + printf(" height: %d\n", hvs_channels[i].dispctrl & 0xfff); + printf("SCALER_DISPBKGND%d: 0x%x\n", i, hvs_channels[i].dispbkgnd); + uint32_t stat = hvs_channels[i].dispstat; + printf("SCALER_DISPSTAT%d: 0x%x\n", i, stat); + printf("mode: %d\n", (stat >> 30) & 0x3); + if (stat & (1<<29)) puts("full"); + if (stat & (1<<28)) puts("empty"); + printf("unknown: 0x%x\n", (stat >> 18) & 0x3ff); + printf("frame count: %d\n", (stat >> 12) & 0x3f); + printf("line: %d\n", SCALER_STAT_LINE(stat)); + uint32_t base = hvs_channels[i].dispbase; + printf("SCALER_DISPBASE%d: base 0x%x top 0x%x\n\n", i, base & 0xffff, base >> 16); + } + for (uint32_t i=list1; i<(list1+64); i++) { + printf("dlist[%x]: 0x%x\n", i, dlist_memory[i]); + if (dlist_memory[i] & BV(31)) { + puts("(31)END"); + break; + } + if (dlist_memory[i] & BV(30)) { + int x = i; + int words = (dlist_memory[i] >> 24) & 0x3f; + for (unsigned int index=i; index < (i+words); index++) { + printf("raw dlist[%d] == 0x%x\n", index-i, dlist_memory[index]); + } + bool unity; + printf(" (3:0)format: %d\n", dlist_memory[i] & 0xf); + if (dlist_memory[i] & (1<<4)) puts(" (4)unity"); + printf(" (7:5)SCL0: %d\n", (dlist_memory[i] >> 5) & 0x7); + printf(" (10:8)SCL1: %d\n", (dlist_memory[i] >> 8) & 0x7); + if (false) { // is bcm2711 + if (dlist_memory[i] & (1<<11)) puts(" (11)rgb expand"); + if (dlist_memory[i] & (1<<12)) puts(" (12)alpha expand"); + } else { + printf(" (12:11)rgb expand: %d\n", (dlist_memory[i] >> 11) & 0x3); + } + printf(" (14:13)pixel order: %d\n", (dlist_memory[i] >> 13) & 0x3); + if (false) { // is bcm2711 + unity = dlist_memory[i] & (1<<15); + } else { + unity = dlist_memory[i] & (1<<4); + if (dlist_memory[i] & (1<<15)) puts(" (15)vflip"); + if (dlist_memory[i] & (1<<16)) puts(" (16)hflip"); + } + printf(" (18:17)key mode: %d\n", (dlist_memory[i] >> 17) & 0x3); + if (dlist_memory[i] & (1<<19)) puts(" (19)alpha mask"); + printf(" (21:20)tiling mode: %d\n", (dlist_memory[i] >> 20) & 0x3); + printf(" (29:24)words: %d\n", words); + x++; + hvs_print_position0(dlist_memory[x++]); + if (bcm_host_is_model_pi4()) { + hvs_print_control2(dlist_memory[x++]); + } + if (unity) { + puts("unity scaling"); + } else { + hvs_print_word1(dlist_memory[x++]); + } + hvs_print_position2(dlist_memory[x++]); + hvs_print_position3(dlist_memory[x++]); + hvs_print_pointer0(dlist_memory[x++]); + hvs_print_pointerctx0(dlist_memory[x++]); + hvs_print_pitch0(dlist_memory[x++]); + if (words > 1) { + i += words - 1; + } + } + } + return 0; +} + +__WEAK status_t display_get_framebuffer(struct display_framebuffer *fb) { + // TODO, have a base layer exposed via this + return -1; +} diff --git a/platform/bcm28xx/hvs/include/platform/bcm28xx/hvs.h b/platform/bcm28xx/hvs/include/platform/bcm28xx/hvs.h new file mode 100644 index 0000000000..4d646a41ca --- /dev/null +++ b/platform/bcm28xx/hvs/include/platform/bcm28xx/hvs.h @@ -0,0 +1,133 @@ +#pragma once + +#include +#include + +#define SCALER_BASE (BCM_PERIPH_BASE_VIRT + 0x400000) + +#define SCALER_DISPCTRL (SCALER_BASE + 0x00) +#define SCALER_DISPSTAT (SCALER_BASE + 0x04) +#define SCALER_DISPCTRL_ENABLE (1<<31) +#define SCALER_DISPEOLN (SCALER_BASE + 0x18) +#define SCALER_DISPLIST0 (SCALER_BASE + 0x20) +#define SCALER_DISPLIST1 (SCALER_BASE + 0x24) +#define SCALER_DISPLIST2 (SCALER_BASE + 0x28) + +struct hvs_channel { + volatile uint32_t dispctrl; + volatile uint32_t dispbkgnd; + volatile uint32_t dispstat; + // 31:30 mode + // 29 full + // 28 empty + // 17:12 frame count + // 11:0 line + volatile uint32_t dispbase; +}; + +extern volatile struct hvs_channel *hvs_channels; + +struct hvs_channel_config { + uint32_t width; + uint32_t height; + bool interlaced; +}; + +extern struct hvs_channel_config channels[3]; + +#define SCALER_STAT_LINE(n) ((n) & 0xfff) + +#define SCALER_DISPCTRL0 (SCALER_BASE + 0x40) +#define SCALER_DISPCTRLX_ENABLE (1<<31) +#define SCALER_DISPCTRLX_RESET (1<<30) +#define SCALER_DISPCTRL_W(n) ((n & 0xfff) << 12) +#define SCALER_DISPCTRL_H(n) (n & 0xfff) +#define SCALER_DISPBKGND_AUTOHS (1<<31) +#define SCALER_DISPBKGND_INTERLACE (1<<30) +#define SCALER_DISPBKGND_GAMMA (1<<29) +#define SCALER_DISPBKGND_FILL (1<<24) + +#define BASE_BASE(n) (n & 0xffff) +#define BASE_TOP(n) ((n & 0xffff) << 16) + + +#define SCALER_LIST_MEMORY (BCM_PERIPH_BASE_VIRT + 0x402000) + + +#define CONTROL_FORMAT(n) (n & 0xf) +#define CONTROL_END (1<<31) +#define CONTROL_VALID (1<<30) +#define CONTROL_WORDS(n) (((n) & 0x3f) << 24) +#define CONTROL0_FIXED_ALPHA (1<<19) +#define CONTROL0_HFLIP (1<<16) +#define CONTROL0_VFLIP (1<<15) +#define CONTROL_PIXEL_ORDER(n) ((n & 3) << 13) +#define CONTROL_UNITY (1<<4) + +enum hvs_pixel_format { + /* 8bpp */ + HVS_PIXEL_FORMAT_RGB332 = 0, + /* 16bpp */ + HVS_PIXEL_FORMAT_RGBA4444 = 1, + HVS_PIXEL_FORMAT_RGB555 = 2, + HVS_PIXEL_FORMAT_RGBA5551 = 3, + HVS_PIXEL_FORMAT_RGB565 = 4, + /* 24bpp */ + HVS_PIXEL_FORMAT_RGB888 = 5, + HVS_PIXEL_FORMAT_RGBA6666 = 6, + /* 32bpp */ + HVS_PIXEL_FORMAT_RGBA8888 = 7, + + HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, + HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, + HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, + HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, + HVS_PIXEL_FORMAT_H264 = 12, + HVS_PIXEL_FORMAT_PALETTE = 13, + HVS_PIXEL_FORMAT_YUV444_RGB = 14, + HVS_PIXEL_FORMAT_AYUV444_RGB = 15, + HVS_PIXEL_FORMAT_RGBA1010102 = 16, + HVS_PIXEL_FORMAT_YCBCR_10BIT = 17, +}; + +#define HVS_PIXEL_ORDER_RGBA 0 +#define HVS_PIXEL_ORDER_BGRA 1 +#define HVS_PIXEL_ORDER_ARGB 2 +#define HVS_PIXEL_ORDER_ABGR 3 + +#define HVS_PIXEL_ORDER_XBRG 0 +#define HVS_PIXEL_ORDER_XRBG 1 +#define HVS_PIXEL_ORDER_XRGB 2 +#define HVS_PIXEL_ORDER_XBGR 3 + +#define SCALER_CTL0_SCL_H_PPF_V_PPF 0 +#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 +#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 +#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 +#define SCALER_CTL0_SCL_H_PPF_V_NONE 4 +#define SCALER_CTL0_SCL_H_NONE_V_PPF 5 +#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 +#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 + +#define POS0_X(n) (n & 0xfff) +#define POS0_Y(n) ((n & 0xfff) << 12) +#define POS0_ALPHA(n) ((n & 0xff) << 24) + +#define POS2_W(n) (n & 0xffff) +#define POS2_H(n) ((n & 0xffff) << 16) + +extern int display_slot; +extern volatile uint32_t* dlist_memory; + +void hvs_add_plane(gfx_surface *fb, int x, int y, bool hflip); +void hvs_add_plane_scaled(gfx_surface *fb, int x, int y, unsigned int width, unsigned int height, bool hflip); +void hvs_terminate_list(void); +void hvs_wipe_displaylist(void); +void hvs_initialize(void); +void hvs_configure_channel(int channel, int width, int height, bool interlaced); +void hvs_setup_irq(void); + +inline __attribute__((always_inline)) void hvs_set_background_color(int channel, uint32_t color) { + hvs_channels[channel].dispbkgnd = SCALER_DISPBKGND_FILL | SCALER_DISPBKGND_AUTOHS | color + | (channels[channel].interlaced ? SCALER_DISPBKGND_INTERLACE : 0); +} diff --git a/platform/bcm28xx/hvs/rules.mk b/platform/bcm28xx/hvs/rules.mk new file mode 100644 index 0000000000..7b445ecfee --- /dev/null +++ b/platform/bcm28xx/hvs/rules.mk @@ -0,0 +1,11 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += \ + lib/gfx \ + +MODULE_SRCS += \ + $(LOCAL_DIR)/hvs.c + +include make/module.mk diff --git a/platform/bcm28xx/i2c.c b/platform/bcm28xx/i2c.c new file mode 100644 index 0000000000..5bb9f4f7aa --- /dev/null +++ b/platform/bcm28xx/i2c.c @@ -0,0 +1,179 @@ +#include +#include +#include +#include +#include +#include + +struct i2c_regs { + uint32_t ctrl; + uint32_t stat; + uint32_t dlen; + uint32_t addr; + uint32_t fifo; + uint32_t div; + uint32_t del; + uint32_t clkt; +}; + +static int cmd_i2c_set_rate(int argc, const cmd_args *argv); +static int cmd_i2c_xfer(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("i2c_xfer", "I2C transfer", &cmd_i2c_xfer) +STATIC_COMMAND("i2c_set_rate", "Set I2C rate", &cmd_i2c_set_rate) +STATIC_COMMAND_END(i2c); + +static int unhex(char c) { + if (c >= '0' && c <= '9') + return c - '0'; + else if (c >= 'a' && c <= 'f') + return c - 'a' + 10; + else if (c >= 'A' && c <= 'F') + return c - 'A' + 10; + return -1; +} + +static uint32_t i2c_base[] = { + I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, + I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, +}; + +void i2c_set_rate(unsigned busnum, unsigned long rate) +{ + volatile struct i2c_regs *regs = (struct i2c_regs*) i2c_base[busnum]; + uint32_t base_freq = get_vpu_per_freq(); + uint32_t div = base_freq / rate; + if (div >= (1UL << 16)) + div = 0xffff; + uint32_t fedl = (div >> 4) ?: 1; + uint32_t redl = (div >> 2) ?: 1; + regs->div = div & 0xffffUL; + regs->del = (fedl << 16) | redl; +} + +static int cmd_i2c_set_rate(int argc, const cmd_args *argv) { + if (argc != 3) { + printf("usage: i2c_set_rate \n"); + return -1; + } + unsigned busnum = argv[1].u; + unsigned long rate = argv[2].u; + i2c_set_rate(busnum, rate); + return 0; +} + +static void i2c_clear_fifo(unsigned busnum) { + volatile struct i2c_regs *regs = (struct i2c_regs*) i2c_base[busnum]; + regs->ctrl |= I2C_C_CLEAR0 | I2C_C_CLEAR1; +} + +int i2c_xfer(unsigned busnum, unsigned addr, + char *sendbuf, size_t sendsz, + char *recvbuf, size_t recvsz) { + int ret = 0; + + if (busnum > 7) + return -1; + + volatile struct i2c_regs *regs = (struct i2c_regs*) i2c_base[busnum]; + + regs->ctrl = I2C_C_I2CEN; + regs->stat = I2C_S_CLKT | I2C_S_ERR | I2C_S_DONE; + i2c_clear_fifo(busnum); + regs->addr = addr; + + // Send bytes + if (sendsz) { + regs->dlen = sendsz; + regs->ctrl |= I2C_C_ST; + while (!(regs->stat & (I2C_S_ERR | I2C_S_TA))) + ; + + while(sendsz--) { + while (!(regs->stat & (I2C_S_CLKT | I2C_S_ERR | I2C_S_TXD))) + ; + if (regs->stat & (I2C_S_CLKT | I2C_S_ERR)) { + regs->stat = I2C_S_CLKT | I2C_S_ERR | I2C_S_DONE; + return -1; + } + regs->fifo = *sendbuf++; + } + + while (!(regs->stat & ( (I2C_S_CLKT | I2C_S_ERR | I2C_S_DONE)))) + ; + if ((regs->stat & (I2C_S_CLKT | I2C_S_ERR))) { + while ((regs->stat & I2C_S_TA)) + ; + dprintf(INFO, "Write failed, status 0x%08x\n", regs->stat); + recvsz = 0; + ret = -1; + } + } + + // Receive bytes + if (recvsz) { + regs->dlen = recvsz; + regs->ctrl |= I2C_C_ST | I2C_C_READ; + while (!(regs->stat & (I2C_S_ERR | I2C_S_DONE | I2C_S_TA))) + ; + + while(!(regs->stat & I2C_S_ERR)) { + if ((regs->stat & I2C_S_RXD)) { + *recvbuf++ = regs->fifo; + if (--recvsz == 0) + break; + } + } + if (!recvsz && !regs->dlen) { + while (!(regs->stat & I2C_S_DONE)) + ; + } else { + dprintf(INFO, "Read failed, status 0x%08x\n", regs->stat); + ret = -1; + } + } + + if ((regs->stat & (I2C_S_CLKT | I2C_S_ERR))) { + while ((regs->stat & I2C_S_TA) && !(regs->stat & I2C_S_RXD)) + ; + } + + regs->stat = I2C_S_CLKT | I2C_S_ERR | I2C_S_DONE; + i2c_clear_fifo(busnum); + regs->ctrl = 0; + return ret; +} + +static int cmd_i2c_xfer(int argc, const cmd_args *argv) { + if (argc != 5) { + printf("usage: i2c_xfer \n"); + return -1; + } + unsigned busnum = argv[1].u; + unsigned addr = argv[2].u; + char send_buf[strlen(argv[3].str) / 2]; + size_t recv_len = argv[4].u; + char recv_buf[recv_len]; + const char *p; + char *q; + for (p = argv[3].str, q = send_buf; *p; p += 2) { + if (!p[1]) { + printf("Hex string must have an even number of digits!\n"); + return -1; + } + *q++ = (unhex(p[0]) << 4) | unhex(p[1]); + } + int status = i2c_xfer(busnum, addr, send_buf, q - send_buf, + recv_buf, recv_len); + if (status < 0) { + printf("Transfer failed: %d\n", status); + return -1; + } else { + for (p = recv_buf; p < recv_buf + recv_len; ++p) { + printf("%02x ", *p); + } + printf("\n"); + } + return 0; +} diff --git a/platform/bcm28xx/include/platform/bcm28xx.h b/platform/bcm28xx/include/platform/bcm28xx.h index f4b06f06e9..466c387bf3 100644 --- a/platform/bcm28xx/include/platform/bcm28xx.h +++ b/platform/bcm28xx/include/platform/bcm28xx.h @@ -7,16 +7,31 @@ */ #pragma once +#ifdef __cplusplus +extern "C" { +#endif +void print_timestamp(void); +#ifdef __cplusplus +} +#endif + +#define BV(n) (1 << n) #define SDRAM_BASE 0 -/* Note: BCM2836/BCM2837 use different peripheral base than BCM2835 */ -#define BCM_PERIPH_BASE_PHYS (0x3f000000U) +#ifdef ARCH_VPU + #define BCM_PERIPH_BASE_PHYS (0x7e000000U) +#else + /* Note: BCM2836/BCM2837 use different peripheral base than BCM2835 */ + #define BCM_PERIPH_BASE_PHYS (0x3f000000U) +#endif #define BCM_PERIPH_SIZE (0x01100000U) -#if BCM2836 -#define BCM_PERIPH_BASE_VIRT (0xe0000000U) +#ifdef MMIO_BASE_VIRT + #define BCM_PERIPH_BASE_VIRT (MMIO_BASE_VIRT) #elif BCM2837 -#define BCM_PERIPH_BASE_VIRT (0xffffffffc0000000ULL) -#define MEMORY_APERTURE_SIZE (1024 * 1024 * 1024) + #define BCM_PERIPH_BASE_VIRT (0xffffffffc0000000ULL) + #define MEMORY_APERTURE_SIZE (1024 * 1024 * 1024) +#elif ARCH_VPU + #define BCM_PERIPH_BASE_VIRT (0x7e000000U) #else #error Unknown BCM28XX Variant #endif @@ -28,11 +43,12 @@ #define BCM_LOCAL_PERIPH_BASE_VIRT (BCM_PERIPH_BASE_VIRT + 0x01000000) #define IC0_BASE (BCM_PERIPH_BASE_VIRT + 0x2000) +#define IC1_BASE (BCM_PERIPH_BASE_VIRT + 0x2800) #define ST_BASE (BCM_PERIPH_BASE_VIRT + 0x3000) #define MPHI_BASE (BCM_PERIPH_BASE_VIRT + 0x6000) #define DMA_BASE (BCM_PERIPH_BASE_VIRT + 0x7000) #define ARM_BASE (BCM_PERIPH_BASE_VIRT + 0xB000) -#define PM_BASE (BCM_PERIPH_BASE_VIRT + 0x100000) +#define CM_BASE (BCM_PERIPH_BASE_VIRT + 0x101000) #define PCM_CLOCK_BASE (BCM_PERIPH_BASE_VIRT + 0x101098) #define RNG_BASE (BCM_PERIPH_BASE_VIRT + 0x104000) #define GPIO_BASE (BCM_PERIPH_BASE_VIRT + 0x200000) @@ -41,14 +57,40 @@ #define I2S_BASE (BCM_PERIPH_BASE_VIRT + 0x203000) #define SPI0_BASE (BCM_PERIPH_BASE_VIRT + 0x204000) #define BSC0_BASE (BCM_PERIPH_BASE_VIRT + 0x205000) +#define OTP_BASE (BCM_PERIPH_BASE_VIRT + 0x20f000) #define AUX_BASE (BCM_PERIPH_BASE_VIRT + 0x215000) #define MINIUART_BASE (BCM_PERIPH_BASE_VIRT + 0x215040) #define EMMC_BASE (BCM_PERIPH_BASE_VIRT + 0x300000) #define SMI_BASE (BCM_PERIPH_BASE_VIRT + 0x600000) #define BSC1_BASE (BCM_PERIPH_BASE_VIRT + 0x804000) #define USB_BASE (BCM_PERIPH_BASE_VIRT + 0x980000) +#define SD_BASE (BCM_PERIPH_BASE_VIRT + 0xe00000) +#define GENET_BASE (0x7d580000) // TODO, this is before the normal BCM_PERIPH_BASE_VIRT bank #define MCORE_BASE (BCM_PERIPH_BASE_VIRT + 0x0000) +#define SD_IDL (SD_BASE + 0x18) +#define SD_CYC (SD_BASE + 0x30) + +#define ST_CS (ST_BASE + 0x0) +#define ST_CLO (ST_BASE + 0x4) +#define ST_CHI (ST_BASE + 0x8) +#define ST_C0 (ST_BASE + 0xc) +#define ST_C1 (ST_BASE + 0x10) + +#define IC0_C (IC0_BASE + 0x0) +#define IC0_S (IC0_BASE + 0x4) +#define IC0_SRC0 (IC0_BASE + 0x8) +#define IC0_SRC1 (IC0_BASE + 0xc) +#define IC0_VADDR (IC0_BASE + 0x30) +#define IC0_WAKEUP (IC0_BASE + 0x34) + +#define IC1_C (IC1_BASE + 0x0) +#define IC1_S (IC1_BASE + 0x4) +#define IC1_SRC0 (IC1_BASE + 0x8) +#define IC1_SRC1 (IC1_BASE + 0xc) +#define IC1_VADDR (IC1_BASE + 0x30) +#define IC1_WAKEUP (IC1_BASE + 0x34) + #define ARMCTRL_BASE (ARM_BASE + 0x000) #define ARMCTRL_INTC_BASE (ARM_BASE + 0x200) #define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) @@ -204,3 +246,17 @@ #define GPIO_GPPUD (GPIO_BASE + 0x94) #define GPIO_GPPUDCLK0 (GPIO_BASE + 0x98) #define GPIO_GPPUDCLK1 (GPIO_BASE + 0x9C) +#define GPIO_2711_PULL (GPIO_BASE + 0xe4) +// 2 bits per reg, 16 pins per reg, 4 regs total +// 0=none, 1=up, 2=down + +#define OTP_BOOTMODE (OTP_BASE + 0x00) +#define OTP_CONFIG (OTP_BASE + 0x04) +#define OTP_CTRL_LO (OTP_BASE + 0x08) +#define OTP_CTRL_HI (OTP_BASE + 0x0c) +#define OTP_STATUS (OTP_BASE + 0x10) +#define OTP_BITSEL (OTP_BASE + 0x14) +#define OTP_DATA (OTP_BASE + 0x18) +#define OTP_ADDR (OTP_BASE + 0x1c) +#define OTP_WRITE_DATA_READ (OTP_BASE + 0x20) +#define OTP_INIT_STATUS (OTP_BASE + 0x24) diff --git a/platform/bcm28xx/include/platform/bcm28xx/dpi.h b/platform/bcm28xx/include/platform/bcm28xx/dpi.h new file mode 100644 index 0000000000..37a8109f1d --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/dpi.h @@ -0,0 +1,36 @@ +#pragma once + +#include +#include + +int cmd_dpi_start(int argc, const cmd_args *argv); +int cmd_dpi_move(int argc, const cmd_args *argv); +int cmd_dpi_count(int argc, const cmd_args *argv); + +#define DPI_C (BCM_PERIPH_BASE_VIRT + 0x208000) + +#define BIT(b) (1 << b) + +#define FORMAT(n) ((n & 0x7) << 11) +#define ORDER(n) ((n & 0x3) << 14) + +// copied from linux/drivers/gpu/drm/vc4/vc4_dpi.c +# define DPI_OUTPUT_ENABLE_MODE BIT(16) +/* Reverses the polarity of the corresponding signal */ +# define DPI_PIXEL_CLK_INVERT BIT(10) +# define DPI_HSYNC_INVERT BIT(9) +# define DPI_VSYNC_INVERT BIT(8) +# define DPI_OUTPUT_ENABLE_INVERT BIT(7) + +/* Outputs the signal the falling clock edge instead of rising. */ +# define DPI_HSYNC_NEGATE BIT(6) +# define DPI_VSYNC_NEGATE BIT(5) +# define DPI_OUTPUT_ENABLE_NEGATE BIT(4) + +/* Disables the signal */ +# define DPI_HSYNC_DISABLE BIT(3) +# define DPI_VSYNC_DISABLE BIT(2) +# define DPI_OUTPUT_ENABLE_DISABLE BIT(1) + +/* Power gate to the device, full reset at 0 -> 1 transition */ +# define DPI_ENABLE BIT(0) diff --git a/platform/bcm28xx/include/platform/bcm28xx/gpio.h b/platform/bcm28xx/include/platform/bcm28xx/gpio.h new file mode 100644 index 0000000000..d93ea7f234 --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/gpio.h @@ -0,0 +1,49 @@ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +enum BCM2708PinmuxSetting { + kBCM2708PinmuxIn = 0, + kBCM2708PinmuxOut = 1, + kBCM2708Pinmux_ALT5 = 2, + kBCM2708Pinmux_ALT4 = 3, + kBCM2708Pinmux_ALT0 = 4, + kBCM2708Pinmux_ALT1 = 5, + kBCM2708Pinmux_ALT2 = 6, + kBCM2708Pinmux_ALT3 = 7 +}; + +enum pull_mode { + kPullOff = 0, + kPullDown = 1, + kPullUp = 2 +}; + +#ifndef RPI4 +struct gpio_pull_batch { + uint32_t bank[3][2]; +}; + +#define GPIO_PULL_CLEAR(batch) { bzero(&batch, sizeof(batch)); } +#define GPIO_PULL_SET(batch, pin, mode) { batch.bank[mode][pin / 32] |= 1 << (pin % 32); } + +void gpio_apply_batch(struct gpio_pull_batch *batch); +#else +struct gpio_pull_batch { + uint32_t bank[4]; + uint32_t mask[4]; +}; +#define GPIO_PULL_CLEAR(batch) +#define GPIO_PULL_SET(batch, pin, mode) +static inline void gpio_apply_batch(struct gpio_pull_batch *batch) {} +#endif + +void gpio_set_pull(unsigned nr, enum pull_mode mode); + +#ifdef __cplusplus +} +#endif diff --git a/platform/bcm28xx/include/platform/bcm28xx/i2c.h b/platform/bcm28xx/include/platform/bcm28xx/i2c.h new file mode 100644 index 0000000000..f158102822 --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/i2c.h @@ -0,0 +1,36 @@ +#pragma once + +#include + +#define I2C0_BASE (BCM_PERIPH_BASE_VIRT + 0x205000) +#define I2C1_BASE (BCM_PERIPH_BASE_VIRT + 0x804000) +#define I2C2_BASE (BCM_PERIPH_BASE_VIRT + 0x805000) +#define I2C3_BASE (BCM_PERIPH_BASE_VIRT + 0x205600) +#define I2C4_BASE (BCM_PERIPH_BASE_VIRT + 0x205800) +#define I2C5_BASE (BCM_PERIPH_BASE_VIRT + 0x205a00) +#define I2C6_BASE (BCM_PERIPH_BASE_VIRT + 0x205c00) +#define I2C7_BASE (BCM_PERIPH_BASE_VIRT + 0x205e00) + +#define I2C_C_READ 0x00000001 +#define I2C_C_CLEAR0 0x00000010 +#define I2C_C_CLEAR1 0x00000020 +#define I2C_C_ST 0x00000080 +#define I2C_C_I2CEN 0x00008000 + +#define I2C_S_TA 0x00000001 +#define I2C_S_DONE 0x00000002 +#define I2C_S_TXD 0x00000010 +#define I2C_S_RXD 0x00000020 +#define I2C_S_ERR 0x00000100 +#define I2C_S_CLKT 0x00000200 + +#ifdef __cplusplus +extern "C" { +#endif +void i2c_set_rate(unsigned busnum, unsigned long rate); +int i2c_xfer(unsigned busnum, unsigned addr, + char *sendbuf, size_t sendsz, + char *recvbuf, size_t recvsz); +#ifdef __cplusplus +} +#endif diff --git a/platform/bcm28xx/include/platform/bcm28xx/otp.h b/platform/bcm28xx/include/platform/bcm28xx/otp.h new file mode 100644 index 0000000000..fb2d809abd --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/otp.h @@ -0,0 +1,10 @@ +#pragma once + +uint32_t otp_read(uint8_t addr); +void otp_pretty_print(void); + +#define OTP_ERR_PROGRAM -1 +#define OTP_ERR_ENABLE -2 +#define OTP_ERR_DISABLE -3 + +int otp_write(uint8_t addr, uint32_t val); diff --git a/platform/bcm28xx/include/platform/bcm28xx/pll.h b/platform/bcm28xx/include/platform/bcm28xx/pll.h new file mode 100644 index 0000000000..7a52d06cfd --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/pll.h @@ -0,0 +1,305 @@ +#pragma once + +#include + +#define MHZ_TO_HZ(f) ((f)*1000*1000) + +enum pll { + PLL_A, + PLL_B, + PLL_C, + PLL_D, + PLL_H, + + PLL_NUM, +}; + +struct pll_def { + char name[8]; + volatile uint32_t *ana; + volatile uint32_t *dig; + uint32_t enable_bit; // the bit to enable it within A2W_XOSC_CTRL + volatile uint32_t *frac; + volatile uint32_t *ctrl; + uint32_t ndiv_mask; + unsigned short ana1_prescale_bit; + unsigned short cm_flock_bit; + volatile uint32_t *cm_pll; + volatile uint32_t *ana_kaip; + volatile uint32_t *ana_vco; +}; + +extern const struct pll_def pll_def[PLL_NUM]; + +enum pll_chan { + PLL_CHAN_ACORE, + PLL_CHAN_APER, + PLL_CHAN_ADSI0, + PLL_CHAN_ACCP2, + + PLL_CHAN_BARM, + PLL_CHAN_BSP0, + PLL_CHAN_BSP1, + PLL_CHAN_BSP2, + + PLL_CHAN_CCORE0, + PLL_CHAN_CCORE1, + PLL_CHAN_CCORE2, + PLL_CHAN_CPER, + + PLL_CHAN_DCORE, + PLL_CHAN_DPER, + PLL_CHAN_DDSI0, + PLL_CHAN_DDSI1, + + PLL_CHAN_HPIX, + PLL_CHAN_HRCAL, + PLL_CHAN_HAUX, + + PLL_CHAN_NUM, +}; + +struct pll_chan_def { + char name[12]; + volatile uint32_t *ctrl; + int chenb_bit; + uint32_t div_mask; + enum pll pll; +}; + +extern uint32_t xtal_freq; +extern const struct pll_chan_def pll_chan_def[PLL_CHAN_NUM]; + +void setup_pllc(uint64_t freq, int core0_div, int per_div); +void switch_vpu_to_src(int src); + + +#define CM_SRC_OSC 1 +#define CM_SRC_PLLC_CORE0 5 + +#define CM_PASSWORD 0x5a000000 + +#define CM_VPUCTL (CM_BASE + 0x008) +#define CM_VPUCTL_FRAC_SET 0x00000200 +#define CM_VPUCTL_BUSY_SET 0x00000080 +#define CM_VPUCTL_GATE_SET 0x00000040 +#define CM_VPUDIV (CM_BASE + 0x00c) + +#define CM_PERIICTL (CM_BASE + 0x020) +#define CM_PERIIDIV (CM_BASE + 0x024) + +#define CM_DPICTL (CM_BASE + 0x068) +#define CM_DPICTL_KILL_SET 0x20 +#define CM_DPICTL_BUSY_SET 0x80 +#define CM_DPICTL_ENAB_SET 0x00000010 +#define CM_DPIDIV (CM_BASE + 0x06c) + +#define CM_TIMERCTL (CM_BASE + 0x0e8) +#define CM_TIMERDIV (CM_BASE + 0x0ec) + +#define CM_TCNTCTL (CM_BASE + 0x0c0) +#define CM_TCNTCNT (CM_BASE + 0x0c4) + +#define CM_UARTCTL (CM_BASE + 0x0f0) +#define CM_UARTCTL_FRAC_SET 0x00000200 +#define CM_UARTCTL_ENAB_SET 0x00000010 +#define CM_UARTDIV (CM_BASE + 0x0f4) + +#define CM_VECCTL (CM_BASE + 0x0f8) +#define CM_VECCTL_ENAB_SET 0x00000010 +#define CM_VECDIV (CM_BASE + 0x0fc) + +#define CM_OSCCOUNT (CM_BASE + 0x100) + +#define CM_PLLA (CM_BASE + 0x104) +#define CM_PLLC (CM_BASE + 0x108) +#define CM_PLLC_DIGRST_SET 0x00000200 +#define CM_PLLC_ANARST_SET 0x00000100 +#define CM_PLLC_HOLDPER_SET 0x00000080 +#define CM_PLLC_HOLDCORE2_SET 0x00000020 +#define CM_PLLC_HOLDCORE1_SET 0x00000008 +#define CM_PLLC_HOLDCORE0_SET 0x00000002 +#define CM_PLLC_LOADCORE0_SET 0x00000001 +#define CM_PLLD (CM_BASE + 0x10C) +#define CM_PLLH (CM_BASE + 0x110) + +#define CM_LOCK (CM_BASE + 0x114) +#define CM_LOCK_FLOCKA_BIT 8 +#define CM_LOCK_FLOCKB_BIT 9 +#define CM_LOCK_FLOCKC_BIT 10 +#define CM_LOCK_FLOCKD_BIT 11 +#define CM_LOCK_FLOCKH_BIT 12 + +#define CM_PLLB (CM_BASE + 0x170) +#define CM_PLLB_LOADARM_SET 0x00000001 +#define CM_PLLB_HOLDARM_SET 0x00000002 + +// Common CM_PLL bits +#define CM_PLL_ANARST 0x00000100 +#define CM_PLL_DIGRST 0x00000200 + +#define CM_ARMCTL (CM_BASE + 0x1b0) +#define CM_ARMCTL_ENAB_SET 0x00000010 + + +#define A2W_XOSC_CTRL (A2W_BASE + 0x190) +#define A2W_XOSC_CTRL_DDREN_SET 0x00000010 +#define A2W_XOSC_CTRL_PLLAEN_SET 0x00000040 +#define A2W_XOSC_CTRL_PLLBEN_SET 0x00000080 +#define A2W_XOSC_CTRL_PLLCEN_SET 0x00000001 +#define A2W_XOSC_CTRL_PLLDEN_SET 0x00000020 + +#define A2W_BASE (BCM_PERIPH_BASE_VIRT + 0x102000) + +#define A2W_PASSWORD 0x5a000000 + +#define A2W_PLLA_DIG0 (A2W_BASE + 0x000) +#define A2W_PLLC_DIG0 (A2W_BASE + 0x020) +#define A2W_PLLD_DIG0 (A2W_BASE + 0x040) +#define A2W_PLLH_DIG0 (A2W_BASE + 0x060) +#define A2W_PLLB_DIG0 (A2W_BASE + 0x0e0) + +#define A2W_PLLC_DIG1 (A2W_BASE + 0x024) +#define A2W_PLLC_DIG2 (A2W_BASE + 0x028) +#define A2W_PLLC_DIG3 (A2W_BASE + 0x02c) +#define A2W_PLLC_ANA1 (A2W_BASE + 0x034) +#define A2W_PLLC_ANA2 (A2W_BASE + 0x038) +#define A2W_PLLC_ANA3 (A2W_BASE + 0x03c) + +#define A2W_PLLB_DIG0 (A2W_BASE + 0x0e0) +#define A2W_PLLB_DIG1 (A2W_BASE + 0x0e4) +#define A2W_PLLB_DIG2 (A2W_BASE + 0x0e8) +#define A2W_PLLB_DIG3 (A2W_BASE + 0x0ec) + +#define A2W_PLLB_ANA1 (A2W_BASE + 0x0f4) +#define A2W_PLLB_ANA2 (A2W_BASE + 0x0f8) +#define A2W_PLLB_ANA3 (A2W_BASE + 0x0fc) +#define CM_PLLB_ANARST_SET 0x00000100 +#define CM_PLLB_DIGRST_SET 0x00000200 +#define A2W_PLLB_ANA_MULTI (A2W_BASE + 0xff0) + +#define A2W_PLL_ANA3_KA_LSB 7 +#define A2W_PLL_ANA3_KA_MASK (BIT_MASK(3) << A2W_PLL_ANA3_KA_LSB) +#define A2W_PLL_ANA1_KI_LSB 19 +#define A2W_PLL_ANA1_KI_MASK (BIT_MASK(3) << A2W_PLL_ANA1_KI_LSB) +#define A2W_PLL_ANA1_KP_LSB 15 +#define A2W_PLL_ANA1_KP_MASK (BIT_MASK(4) << A2W_PLL_ANA1_KP_LSB) + +// PLLH is special +#define A2W_PLLH_ANA0_KA_LSB 19 +#define A2W_PLLH_ANA0_KA_MASK (BIT_MASK(3) << A2W_PLLH_ANA0_KA_LSB) +#define A2W_PLLH_ANA0_KI_LO_LSB 22 +#define A2W_PLLH_ANA1_KI_LO_BITS 2 +#define A2W_PLLH_ANA0_KI_LO_MASK (BIT_MASK(A2W_PLLH_ANA1_KI_LO_BITS) \ + << A2W_PLLH_ANA0_KI_LO_LSB) +#define A2W_PLLH_ANA1_KI_HI_LSB 0 +#define A2W_PLLH_ANA1_KI_HI_MASK (BIT_MASK(1) << A2W_PLLH_ANA1_KI_HI_LSB) +#define A2W_PLLH_ANA1_KP_LSB 1 +#define A2W_PLLH_ANA1_KP_MASK (BIT_MASK(4) << A2W_PLLH_ANA1_KP_LSB) + +#define A2W_PLLA_ANA0 (A2W_BASE + 0x010) +#define A2W_PLLC_ANA0 (A2W_BASE + 0x030) +#define A2W_PLLD_ANA0 (A2W_BASE + 0x050) +#define A2W_PLLH_ANA0 (A2W_BASE + 0x070) +#define A2W_PLLB_ANA0 (A2W_BASE + 0x0f0) + +#define A2W_PLLA_FRAC (A2W_BASE + 0x200) +#define A2W_PLLC_FRAC (A2W_BASE + 0x220) +#define A2W_PLLD_FRAC (A2W_BASE + 0x240) +#define A2W_PLLH_FRAC (A2W_BASE + 0x260) +#define A2W_PLLB_FRAC (A2W_BASE + 0x2e0) +#define A2W_PLL_FRAC_MASK 0x000fffff + +// Common A2W_PLL_CTRL bits +#define A2W_PLL_CTRL_PDIV_MASK 0x00007000 +#define A2W_PLL_CTRL_PDIV_LSB 12 +#define A2W_PLL_CTRL_PWRDN 0x00010000 +#define A2W_PLL_CTRL_PRSTN 0x00020000 + +#define A2W_PLLA_CTRL (A2W_BASE + 0x100) +#define A2W_PLLA_CTRL_NDIV_SET 0x000003ff +#define A2W_PLLC_CTRL (A2W_BASE + 0x120) +#define A2W_PLLC_CTRL_PRSTN_SET 0x00020000 +#define A2W_PLLC_CTRL_PWRDN_SET 0x00010000 +#define A2W_PLLC_CTRL_NDIV_SET 0x000003ff +#define A2W_PLLD_CTRL (A2W_BASE + 0x140) +#define A2W_PLLD_CTRL_NDIV_SET 0x000003ff +#define A2W_PLLH_CTRL (A2W_BASE + 0x160) +#define A2W_PLLH_CTRL_NDIV_SET 0x000000ff +#define A2W_PLLB_CTRL (A2W_BASE + 0x1e0) +#define A2W_PLLB_CTRL_NDIV_SET 0x000003ff + +#define A2W_PLLA_DSI0 (A2W_BASE + 0x300) +#define A2W_PLLA_DSI0_CHENB_LSB 8 +#define A2W_PLLA_DSI0_DIV_SET 0x000000ff +#define A2W_PLLC_CORE2 (A2W_BASE + 0x320) +#define A2W_PLLC_CORE2_CHENB_LSB 8 +#define A2W_PLLC_CORE2_DIV_SET 0x000000ff +#define A2W_PLLD_DSI0 (A2W_BASE + 0x340) +#define A2W_PLLD_DSI0_CHENB_LSB 8 +#define A2W_PLLD_DSI0_DIV_SET 0x000000ff +#define A2W_PLLH_AUX (A2W_BASE + 0x360) +#define A2W_PLLH_AUX_CHENB_LSB 8 +#define A2W_PLLH_AUX_DIV_SET 0x000000ff +#define A2W_PLLB_ARM (A2W_BASE + 0x3e0) +#define A2W_PLLB_ARM_CHENB_LSB 8 +#define A2W_PLLB_ARM_DIV_SET 0x000000ff +#define A2W_PLLA_CORE (A2W_BASE + 0x400) +#define A2W_PLLA_CORE_CHENB_LSB 8 +#define A2W_PLLA_CORE_DIV_SET 0x000000ff +#define A2W_PLLD_CORE (A2W_BASE + 0x440) +#define A2W_PLLD_CORE_CHENB_LSB 8 +#define A2W_PLLD_CORE_DIV_SET 0x000000ff +#define A2W_PLLH_RCAL (A2W_BASE + 0x460) +#define A2W_PLLH_RCAL_CHENB_LSB 8 +#define A2W_PLLH_RCAL_DIV_SET 0x000000ff +#define A2W_PLLB_SP0 (A2W_BASE + 0x4e0) +#define A2W_PLLB_SP0_CHENB_LSB 8 +#define A2W_PLLB_SP0_DIV_SET 0x000000ff +#define A2W_PLLA_PER (A2W_BASE + 0x500) +#define A2W_PLLA_PER_CHENB_LSB 8 +#define A2W_PLLA_PER_DIV_SET 0x000000ff +#define A2W_PLLC_PER (A2W_BASE + 0x520) +#define A2W_PLLC_PER_CHENB_LSB 8 +#define A2W_PLLC_PER_DIV_SET 0x000000ff +#define A2W_PLLD_PER (A2W_BASE + 0x540) +#define A2W_PLLD_PER_CHENB_LSB 8 +#define A2W_PLLD_PER_DIV_SET 0x000000ff +#define A2W_PLLH_PIX (A2W_BASE + 0x560) +#define A2W_PLLH_PIX_CHENB_LSB 8 +#define A2W_PLLH_PIX_DIV_SET 0x000000ff +#define A2W_PLLC_CORE1 (A2W_BASE + 0x420) +#define A2W_PLLC_CORE1_CHENB_LSB 8 +#define A2W_PLLC_CORE1_DIV_SET 0x000000ff +#define A2W_PLLB_SP1 (A2W_BASE + 0x5e0) +#define A2W_PLLB_SP1_CHENB_LSB 8 +#define A2W_PLLB_SP1_DIV_SET 0x000000ff +#define A2W_PLLA_CCP2 (A2W_BASE + 0x600) +#define A2W_PLLA_CCP2_CHENB_LSB 8 +#define A2W_PLLA_CCP2_DIV_SET 0x000000ff +#define A2W_PLLC_CORE0 (A2W_BASE + 0x620) +#define A2W_PLLC_CORE0_CHENB_LSB 8 +#define A2W_PLLC_CORE0_DIV_SET 0x000000ff +#define A2W_PLLD_DSI1 (A2W_BASE + 0x640) +#define A2W_PLLD_DSI1_CHENB_LSB 8 +#define A2W_PLLD_DSI1_DIV_SET 0x000000ff +#define A2W_PLLB_SP2 (A2W_BASE + 0x6e0) +#define A2W_PLLB_SP2_CHENB_LSB 8 +#define A2W_PLLB_SP2_DIV_SET 0x000000ff + +// Common A2W_PLL_ANA_KAIP bits +#define A2W_PLL_ANA_KAIP_KA_LSB 8 +#define A2W_PLL_ANA_KAIP_KI_LSB 4 +#define A2W_PLL_ANA_KAIP_KP_LSB 0 + +#define A2W_PLLA_ANA_KAIP (A2W_BASE + 0x310) +#define A2W_PLLC_ANA_KAIP (A2W_BASE + 0x330) +#define A2W_PLLD_ANA_KAIP (A2W_BASE + 0x350) +#define A2W_PLLH_ANA_KAIP (A2W_BASE + 0x370) +#define A2W_PLLB_ANA_KAIP (A2W_BASE + 0x3f0) + +#define A2W_PLLA_ANA_VCO (A2W_BASE + 0x610) +#define A2W_PLLC_ANA_VCO (A2W_BASE + 0x630) +#define A2W_PLLD_ANA_VCO (A2W_BASE + 0x650) +#define A2W_PLLH_ANA_VCO (A2W_BASE + 0x670) +#define A2W_PLLB_ANA_VCO (A2W_BASE + 0x6f0) diff --git a/platform/bcm28xx/include/platform/bcm28xx/pll_read.h b/platform/bcm28xx/include/platform/bcm28xx/pll_read.h new file mode 100644 index 0000000000..3efb6311f9 --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/pll_read.h @@ -0,0 +1,19 @@ +#pragma once + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif +uint32_t clk_get_input_freq(uint32_t ctlreg); +uint32_t clk_get_freq(uint32_t divreg, uint32_t ctlreg); +uint32_t get_vpu_per_freq(void); +uint32_t get_uart_base_freq(void); +uint32_t get_pll_freq(enum pll pll); +uint32_t get_pll_chan_freq(enum pll_chan chan); +int measure_clock(int mux); +int cmd_measure_clocks(int argc, const cmd_args *argv); +#ifdef __cplusplus +} +#endif diff --git a/platform/bcm28xx/include/platform/bcm28xx/sdhost.h b/platform/bcm28xx/include/platform/bcm28xx/sdhost.h new file mode 100644 index 0000000000..c98314b0ff --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/sdhost.h @@ -0,0 +1,33 @@ +#pragma once + +#include + +#define SH_BASE (BCM_PERIPH_BASE_PHYS + 0x202000) + +#define SH_CMD (SH_BASE + 0x00) +#define SH_CMD_NEW_FLAG_SET 0x8000 +#define SH_CMD_FAIL_FLAG_SET 0x4000 +#define SH_CMD_BUSY_CMD_SET 0x0800 +#define SH_CMD_NO_RESPONSE_SET 0x0400 +#define SH_CMD_LONG_RESPONSE_SET 0x0200 +#define SH_CMD_READ_CMD_SET 0x0040 +#define SH_CMD_COMMAND_SET 0x003f +#define SH_ARG (SH_BASE + 0x04) +#define SH_TOUT (SH_BASE + 0x08) +#define SH_CDIV (SH_BASE + 0x0c) +#define SH_RSP0 (SH_BASE + 0x10) +#define SH_RSP1 (SH_BASE + 0x14) +#define SH_RSP2 (SH_BASE + 0x18) +#define SH_RSP3 (SH_BASE + 0x1c) +#define SH_HSTS (SH_BASE + 0x20) +#define SH_HSTS_DATA_FLAG_SET 0x01 +#define SH_VDD (SH_BASE + 0x30) +#define SH_VDD_POWER_ON_SET 0x01 +#define SH_EDM (SH_BASE + 0x34) +#define SH_HCFG (SH_BASE + 0x38) +#define SH_HCFG_SLOW_CARD_SET 0x8 +#define SH_HCFG_WIDE_EXT_BUS_SET 0x4 +#define SH_HCFG_WIDE_INT_BUS_SET 0x2 +#define SH_HBCT (SH_BASE + 0x3c) +#define SH_DATA (SH_BASE + 0x40) +#define SH_HBLC (SH_BASE + 0x50) diff --git a/platform/bcm28xx/include/platform/bcm28xx/sdhost_impl.h b/platform/bcm28xx/include/platform/bcm28xx/sdhost_impl.h new file mode 100644 index 0000000000..64b5b13b9d --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/sdhost_impl.h @@ -0,0 +1,13 @@ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +bdev_t *rpi_sdhost_init(void); + +#ifdef __cplusplus +} +#endif diff --git a/platform/bcm28xx/include/platform/bcm28xx/sdram.h b/platform/bcm28xx/include/platform/bcm28xx/sdram.h new file mode 100644 index 0000000000..eb5d29ce4e --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/sdram.h @@ -0,0 +1,13 @@ +#pragma once + +void sdram_init(void); + +enum RamSize { + kRamSize1GB = 0, + kRamSize512MB = 1, + kRamSize256MB = 2, + kRamSize128MB = 3, + kRamSize2GB = 4, + kRamSize4GB = 5, + kRamSizeUnknown +}; diff --git a/platform/bcm28xx/include/platform/bcm28xx/udelay.h b/platform/bcm28xx/include/platform/bcm28xx/udelay.h new file mode 100644 index 0000000000..b7120e8b3d --- /dev/null +++ b/platform/bcm28xx/include/platform/bcm28xx/udelay.h @@ -0,0 +1,11 @@ +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif +void udelay(uint32_t usec); +#ifdef __cplusplus +} +#endif diff --git a/platform/bcm28xx/intc.c b/platform/bcm28xx/intc.c index cf85322a45..464fc3096c 100644 --- a/platform/bcm28xx/intc.c +++ b/platform/bcm28xx/intc.c @@ -14,15 +14,14 @@ #include #include #include - -#if defined (BCM2836) -#include -typedef struct arm_iframe arm_platform_iframe_t; -#elif defined (BCM2837) -#include -typedef struct arm64_iframe_long arm_platform_iframe_t; -#else -#error Unknown BCM28XX Variant +#include + +#if ARCH_ARM + #include + typedef struct arm_iframe arm_platform_iframe_t; +#elif ARCH_ARM64 + #include + typedef struct arm64_iframe_long arm_platform_iframe_t; #endif @@ -166,6 +165,7 @@ enum handler_return platform_irq(arm_platform_iframe_t *frame) { THREAD_STATS_INC(interrupts); // see what kind of irq it is +#if BCM2835 != 1 uint32_t pend = *REG32(INTC_LOCAL_IRQ_PEND0 + cpu * 4); pend &= ~(1 << (INTERRUPT_ARM_LOCAL_GPU_FAST % 32)); // mask out gpu interrupts @@ -176,6 +176,9 @@ enum handler_return platform_irq(arm_platform_iframe_t *frame) { vector = ARM_IRQ_LOCAL_BASE + ctz(pend); goto decoded; } +#else + uint32_t pend; +#endif // XXX disable for now, since all of the interesting irqs are mirrored into the other banks #if 0 diff --git a/platform/bcm28xx/mailbox.c b/platform/bcm28xx/mailbox.c index cc84be22ab..b671132637 100644 --- a/platform/bcm28xx/mailbox.c +++ b/platform/bcm28xx/mailbox.c @@ -120,6 +120,12 @@ void dispflush(void) { } +#ifndef WITH_KERNEL_VM +inline void *paddr_to_kvaddr(paddr_t x) { + return x; +} +#endif + /* LK display (lib/gfx.h) calls this function */ status_t display_get_framebuffer(struct display_framebuffer *fb) { // VideoCore returns 32-bit bus address, which needs to be converted to kernel virtual diff --git a/platform/bcm28xx/otp/otp.c b/platform/bcm28xx/otp/otp.c new file mode 100644 index 0000000000..9171989ec4 --- /dev/null +++ b/platform/bcm28xx/otp/otp.c @@ -0,0 +1,318 @@ +#include +#include +#include +#include +#include +#include +#include +#include + +#define OTP_MAX_CMD_WAIT 1000 +#define OTP_MAX_PROG_WAIT 32000 +#define OTP_MAX_WRITE_RETRIES 16 + +enum otp_command { + OTP_CMD_READ = 0, +#ifndef RPI4 + OTP_CMD_PROG_ENABLE = 0x1, + OTP_CMD_PROG_DISABLE = 0x2, +#else + OTP_CMD_PROG_ENABLE = 0x2, + OTP_CMD_PROG_DISABLE = 0x3, +#endif + OTP_CMD_PROGRAM_WORD = 0xa, +}; + +/* OTP_CTRL_LO Bits */ +#define OTP_CMD_START 1 +#ifndef RPI4 +# define OTP_STAT_PROG_OK 4 +# define OTP_STAT_PROG_ENABLE 0x1000 +#else +# define OTP_STAT_PROG_ENABLE 4 +#endif + +/* OTP Status Bits */ +#ifdef RPI4 +# define OTP_STAT_CMD_DONE 2 +#else +# define OTP_STAT_CMD_DONE 1 +#endif + +#define OTP_PROG_EN_SEQ { 0xf, 0x4, 0x8, 0xd }; + +static int cmd_otp_pretty(int argc, const cmd_args *argv); +static int cmd_otp_full(int argc, const cmd_args *argv); +static int cmd_otp_write(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("otp_pretty_print", "pretty-print all known otp values", &cmd_otp_pretty) +STATIC_COMMAND("otp_dump_all","dump all OTP values", &cmd_otp_full) +STATIC_COMMAND("otp_write","write new OTP value", &cmd_otp_write) +STATIC_COMMAND_END(otp); + +static inline void otp_delay(void) { + udelay(1); +} + +static void otp_open(void) { + // TODO: Is this really needed? The code seems to work + // without this block, at least on BCM2711 B0 silicon. + *REG32(OTP_CONFIG) = 3; + otp_delay(); + + *REG32(OTP_CTRL_HI) = 0; + *REG32(OTP_CTRL_LO) = 0; + *REG32(OTP_ADDR) = 0; + *REG32(OTP_DATA) = 0; + *REG32(OTP_CONFIG) = 2; +} + +static void otp_close(void) { + *REG32(OTP_CTRL_HI) = 0; + *REG32(OTP_CTRL_LO) = 0; + *REG32(OTP_CONFIG) = 0; +} + +static int otp_wait_status(uint32_t mask, int retry) { + int i = retry; + do { + otp_delay(); + if (*REG32(OTP_STATUS) & mask) + return 0; + } while (--i); + return -1; +} + +static int otp_set_command(uint32_t ctrlhi, uint32_t cmd) { + *REG32(OTP_CTRL_HI) = ctrlhi; + *REG32(OTP_CTRL_LO) = cmd << 1; + if (otp_wait_status(OTP_STAT_CMD_DONE, OTP_MAX_CMD_WAIT)) + return -1; + *REG32(OTP_CTRL_LO) = (cmd << 1) | OTP_CMD_START; + return otp_wait_status(OTP_STAT_CMD_DONE, OTP_MAX_CMD_WAIT); +} + +static uint32_t otp_read_open(uint8_t addr) { + *REG32(OTP_ADDR) = addr; + return (uint32_t) otp_set_command(0, OTP_CMD_READ) ?: *REG32(OTP_DATA); +} + +uint32_t otp_read(uint8_t addr) { + uint32_t val; + otp_open(); + val = otp_read_open(addr); + otp_close(); + return val; +} + +static int otp_enable_program(void) +{ + static const uint32_t seq[] = OTP_PROG_EN_SEQ; + unsigned i; + + for (i = 0; i < countof(seq); ++i) { +#ifndef RPI4 + *REG32(OTP_BITSEL) = seq[i]; +#else + *REG32(OTP_DATA) = seq[i]; +#endif + if (otp_set_command(0, OTP_CMD_PROG_ENABLE)) + return -1; + } + return otp_wait_status(OTP_STAT_PROG_ENABLE, OTP_MAX_PROG_WAIT); +} + +static int otp_disable_program(void) +{ + return otp_set_command(0, OTP_CMD_PROG_DISABLE); +} + +#ifndef RPI4 + +static int otp_program_bit(uint8_t addr, uint8_t bit) +{ + uint32_t cmd; + int err; + int i; + + *REG32(OTP_ADDR) = addr; + *REG32(OTP_BITSEL) = bit; + + if (addr < 8) + cmd = 0x38000a; + else if (addr < 77) + cmd = 0x58000a; + else + cmd = 0x78000a; + err = -1; + for (i = 0; i < OTP_MAX_WRITE_RETRIES; ++i) { + otp_set_command(0x1420000, cmd); + if (!otp_set_command(0x1484, 0x88003) && + (*REG32(OTP_STATUS) & OTP_STAT_PROG_OK)) { + err = 0; + break; + } + } + for (i = 0; i < OTP_MAX_WRITE_RETRIES; ++i) { + otp_set_command(0x9420000, cmd); + if (!otp_set_command(0x8001484, 0x88003) && + (*REG32(OTP_STATUS) & OTP_STAT_PROG_OK)) { + err = 0; + break; + } + } + return err; +} + +static int otp_write_enabled(uint8_t addr, uint32_t newval) +{ + int bitnum, err; + uint32_t oldval = otp_read_open(addr); + if (oldval == 0xffffffffL) // This check guards against read failures + return 0; + + err = 0; + for (bitnum = 0; bitnum < 32; ++bitnum) { + uint32_t bitmask = (uint32_t)1 << bitnum; + if ((oldval & bitmask) != 0 || (newval & bitmask) == 0) + continue; + if (otp_program_bit(addr, bitnum) < 0) + ++err; + } + return err; +} + +#else /* RPI4 */ + +static int otp_write_enabled(uint8_t addr, uint32_t newval) +{ + uint32_t oldval = otp_read_open(addr); + if (oldval == 0xffffffffL) // This check guards against read failures + return 0; + *REG32(OTP_DATA) = newval | oldval; + otp_delay(); + *REG32(OTP_ADDR) = addr; + otp_delay(); + return otp_set_command(0, OTP_CMD_PROGRAM_WORD); +} + +#endif /* RPI4 */ + +static int otp_write_open(uint8_t addr, uint32_t val) +{ + int err; + if (otp_enable_program()) + return OTP_ERR_ENABLE; + err = otp_write_enabled(addr, val); + if (err) + err = OTP_ERR_PROGRAM; + if (otp_disable_program()) + err = err ?: OTP_ERR_DISABLE; + return err; +} + +int otp_write(uint8_t addr, uint32_t val) +{ + int err; + otp_open(); + err = otp_write_open(addr, val); + otp_close(); + return err; +} + +void dump_all_otp(void) { + printf("full otp dump\n"); + for (uint8_t addr=0; addr < 67; addr++) { + uint32_t value = otp_read(addr); + printf("%02d:%08x\n", addr, value); + } +} + +static int cmd_otp_full(int argc, const cmd_args *argv) { + dump_all_otp(); + return 0; +} + +void otp_pretty_print(void) { + // https://github.com/raspberrypi/firmware/issues/974 + // addr 32 contains warrenty flag + uint32_t bootmode = otp_read(17); + printf("OTP17: 0x%08x\n", bootmode); + if (bootmode & (1<< 1)) printf(" 19.2mhz crystal present\n"); + if (bootmode & (1<< 3)) printf(" SDIO pullups should be on?\n"); + if (bootmode & (1<<19)) printf(" GPIO boot mode\n"); + if (bootmode & (1<<20)) printf(" GPIO boot mode bank bit is set\n"); + if (bootmode & (1<<21)) printf(" SD card boot enabled\n"); + if (bootmode & (1<<22)) printf(" bank to boot from set\n"); + if (bootmode & (1<<28)) printf(" USB device boot enabled\n"); + if (bootmode & (1<<29)) printf(" USB host boot enabled (ethernet/mass-storage)\n"); + if (bootmode != otp_read(18)) printf("WARNING: boot mode duplicate doesnt match\n"); + uint32_t serial = otp_read(28); + printf("\nSoC serial# 0x%08x\n", serial); + if (~serial != otp_read(29)) printf("WARNING: serial# duplicate doesnt match\n"); + uint32_t revision = otp_read(30); + // https://www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/README.md + printf("\nHW revision: 0x%08x\n", revision); + if (revision & (1 <<23)) { // new style revision + printf(" Type: %d\n", (revision >> 4) & 0xff); + printf(" Rev: %d\n", revision & 0xf); + printf(" Proc: %d\n", (revision >> 12) & 0xf); + printf(" Manufacturer: %d\n", (revision >> 16) & 0xf); + printf(" Ram: %d\n", (revision >> 20) & 0x7); + } + uint32_t maclow = otp_read(64); + uint32_t machi = otp_read(65); + printf("\nOptional Mac Override: %08x%x\n", maclow, machi); + + uint32_t advanced_boot = otp_read(66); + printf("\nOTP66: 0x%08x\n", advanced_boot); + if (advanced_boot & (1<<7)) { + printf(" ETH_CLK on GPIO%d\n", advanced_boot & 0x7f); + if (advanced_boot & (1<<25)) printf(" ETH_CLK 24mhz\n"); + else printf(" ETH_CLK 25mhz\n"); + } + if (advanced_boot & (1<<15)) { + printf(" LAN_RUN on GPIO%d\n", (advanced_boot >> 8) & 0x7f); + } + if (advanced_boot & (1<<24)) printf(" extended USB timeout\n"); +} + +int cmd_otp_pretty(int argc, const cmd_args *argv) { + otp_pretty_print(); + return 0; +} + +static int cmd_otp_write(int argc, const cmd_args *argv) { + uint32_t addr, val; + int err; + if (argc != 3) { + printf("usage: otp_write 36 0x20\n"); + return -1; + } + addr = argv[1].u; + val = argv[2].u; + otp_open(); + printf("old value: 0x%08"PRIx32"\n", otp_read_open(addr)); + err = otp_write_open(addr, val); + switch (err) { + case OTP_ERR_ENABLE: + printf("cannot %s OTP programming\n", "enable"); + break; + case OTP_ERR_PROGRAM: + printf("programming command failed\n"); + break; + case OTP_ERR_DISABLE: + printf("cannot %s OTP programming\n", "disable"); + break; +#ifndef RPI4 + case 0: + break; + default: + printf("%d bits failed\n", err); +#endif + } + printf("new value: 0x%08"PRIx32"\n", otp_read_open(addr)); + otp_close(); + return 0; +} diff --git a/platform/bcm28xx/otp/rules.mk b/platform/bcm28xx/otp/rules.mk new file mode 100644 index 0000000000..ba263f4e1b --- /dev/null +++ b/platform/bcm28xx/otp/rules.mk @@ -0,0 +1,9 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/otp.c \ + + +include make/module.mk diff --git a/platform/bcm28xx/pixelvalve/include/platform/bcm28xx/pv.h b/platform/bcm28xx/pixelvalve/include/platform/bcm28xx/pv.h new file mode 100644 index 0000000000..372961ef0d --- /dev/null +++ b/platform/bcm28xx/pixelvalve/include/platform/bcm28xx/pv.h @@ -0,0 +1,44 @@ +#pragma once + +#include + +struct pv_timings { + uint16_t vfp, vsync, vbp, vactive; + uint16_t hfp, hsync, hbp, hactive; + uint16_t vfp_even, vsync_even, vbp_even, vactive_even; + bool interlaced; + int clock_mux; +}; + +struct pixel_valve { + volatile uint32_t c; + volatile uint32_t vc; + volatile uint32_t vsyncd_even; + volatile uint32_t horza; + volatile uint32_t horzb; + volatile uint32_t verta; + volatile uint32_t vertb; + volatile uint32_t verta_even; + volatile uint32_t vertb_even; + volatile uint32_t int_enable; + volatile uint32_t int_status; + volatile uint32_t h_active; +}; + +void setup_pixelvalve(struct pv_timings *timings, int pvnr); +void setup_pv_interrupt(int pvnr, int_handler handler, void *arg); +struct pixel_valve *getPvAddr(int pvnr); + +#define PV_CONTROL_FIFO_CLR (1<<1) +#define PV_CONTROL_EN (1<<0) + +#define PV_INTEN_HSYNC_START (1<<0) +#define PV_INTEN_HBP_START (1<<1) +#define PV_INTEN_HACT_START (1<<2) +#define PV_INTEN_HFP_START (1<<3) +#define PV_INTEN_VSYNC_START (1<<4) +#define PV_INTEN_VBP_START (1<<5) +#define PV_INTEN_VACT_START (1<<6) +#define PV_INTEN_VFP_START (1<<7) +#define PV_INTEN_VFP_END (1<<8) +#define PV_INTEN_IDLE (1<<9) diff --git a/platform/bcm28xx/pixelvalve/pv.c b/platform/bcm28xx/pixelvalve/pv.c new file mode 100644 index 0000000000..ffb5186cdb --- /dev/null +++ b/platform/bcm28xx/pixelvalve/pv.c @@ -0,0 +1,93 @@ +#include +#include +#include +#include +#include + +struct pixel_valve *getPvAddr(int pvnr) { + uint32_t addr; + assert(pvnr <= 2); + switch (pvnr) { + case 0: + addr = BCM_PERIPH_BASE_VIRT + 0x206000; + break; + case 1: + addr = BCM_PERIPH_BASE_VIRT + 0x207000; + break; + case 2: + addr = BCM_PERIPH_BASE_VIRT + 0x807000; + break; + default: + return NULL; + } + struct pixel_valve *rawpv = (struct pixel_valve*) addr; + return rawpv; +} + +unsigned int getPvIrq(int pvnr) { + assert(pvnr <= 2); + switch (pvnr) { + case 0: + return 45; + case 1: + return 46; + case 2: + return 42; + default: + return -1; + } +} + +void setup_pixelvalve(struct pv_timings *t, int pvnr) { + struct pixel_valve *rawpv = getPvAddr(pvnr); + + // reset the PV fifo + rawpv->c = 0; + rawpv->c = PV_CONTROL_FIFO_CLR | PV_CONTROL_EN; + rawpv->c = 0; + + rawpv->horza = (t->hbp << 16) | t->hsync; + rawpv->horzb = (t->hfp << 16) | t->hactive; + + rawpv->verta = (t->vbp << 16) | t->vsync; + rawpv->vertb = (t->vfp << 16) | t->vactive; + + if (t->interlaced) { + rawpv->verta_even = (t->vbp_even << 16) | t->vsync_even; + rawpv->vertb_even = (t->vfp << 16) | t->vactive_even; + } + +#define CLK_SELECT(n) ((n & 3) << 2) +# define PV_CONTROL_CLK_SELECT_DSI 0 +# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 +# define PV_CONTROL_CLK_SELECT_VEC 2 +#define PIXEL_REP(n) (((n) & 0x3) << 4) +#define FIFO_LEVEL(n) ((n & 0x3f) << 15) + + rawpv->vc = BV(0) | // video enable + BV(1)| // continous + (t->interlaced ? BV(4) : 0); + + rawpv->h_active = t->hactive; + + uint32_t fifo_len_bytes = 64; + fifo_len_bytes = fifo_len_bytes - 3 * 6; + + rawpv->c = PV_CONTROL_EN | + PV_CONTROL_FIFO_CLR | + //CLK_SELECT(PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI) | // set to DPI clock + CLK_SELECT(PV_CONTROL_CLK_SELECT_VEC) | // vec + PIXEL_REP(1 - 1) | + BV(12) | // wait for h-start + BV(13) | // trigger underflow + BV(14) | // clear at start + FIFO_LEVEL(fifo_len_bytes); +} + +void setup_pv_interrupt(int pvnr, int_handler handler, void *arg) { + //struct pixel_valve *rawpv = getPvAddr(pvnr); + unsigned int irq = getPvIrq(pvnr); + + register_int_handler(irq, handler, arg); + unmask_interrupt(irq); +} diff --git a/platform/bcm28xx/pixelvalve/rules.mk b/platform/bcm28xx/pixelvalve/rules.mk new file mode 100644 index 0000000000..176a226187 --- /dev/null +++ b/platform/bcm28xx/pixelvalve/rules.mk @@ -0,0 +1,10 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/pv.c \ + +GLOBAL_INCLUDES += $(LOCAL_DIR)/include + +include make/module.mk diff --git a/platform/bcm28xx/platform.c b/platform/bcm28xx/platform.c index e2c62efb57..262c8ac498 100644 --- a/platform/bcm28xx/platform.c +++ b/platform/bcm28xx/platform.c @@ -15,12 +15,20 @@ #include #include #include +#include + +#ifdef HAVE_ARM_TIMER #include +#endif + #include -#include #include +#include +#include +#include +#include -#if BCM2836 +#if BCM2836 || BCM2835 #include #include @@ -89,30 +97,78 @@ struct mmu_initial_mapping mmu_initial_mappings[] = { #define DEBUG_UART 1 +#elif ARCH_VPU + #define DEBUG_UART 0 #else -#error Unknown BCM28XX Variant + #error Unknown BCM28XX Variant #endif extern void intc_init(void); extern void arm_reset(void); +static void switch_vpu_to_pllc(void); +// 19.2mhz for most models +// 54mhz for rpi4 +uint32_t xtal_freq = CRYSTAL; +#ifdef WITH_KERNEL_VM static pmm_arena_t arena = { .name = "sdram", .base = SDRAM_BASE, .size = MEMSIZE, .flags = PMM_ARENA_FLAG_KMAP, }; +#endif + +__WEAK uint32_t get_uart_base_freq() { + return 48 * 1000 * 1000; +} void platform_init_mmu_mappings(void) { } +static void switch_vpu_to_pllc() { + switch_vpu_to_src(CM_SRC_OSC); + *REG32(CM_VPUDIV) = CM_PASSWORD | (1 << 12); + + int core0_div = 4; + int per_div = 4; + + const uint64_t pllc_mhz = 108 * per_div * 4; + + setup_pllc( pllc_mhz * 1000 * 1000, core0_div, per_div); + + int vpu_divisor = 1; + + *REG32(CM_VPUCTL) = CM_PASSWORD | CM_VPUCTL_FRAC_SET | CM_SRC_OSC | CM_VPUCTL_GATE_SET; + *REG32(CM_VPUDIV) = CM_PASSWORD | (vpu_divisor << 12); + *REG32(CM_VPUCTL) = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET; + *REG32(CM_VPUCTL) = CM_PASSWORD | CM_SRC_PLLC_CORE0 | CM_VPUCTL_GATE_SET | 0x10; /* ENAB */ + + //*REG32(CM_TIMERDIV) = CM_PASSWORD | (19 << 12) | 819; // TODO, look into this timer + //*REG32(CM_TIMERCTL) = CM_PASSWORD | CM_SRC_OSC | 0x10; + + int vpu = measure_clock(5); + int pllc_core0 = vpu*vpu_divisor; + uint32_t pllc = pllc_core0 * core0_div; + dprintf(INFO, "VPU now at %dmhz, ", vpu/1000/1000); + dprintf(INFO, "PLLC_CORE0 at %dmhz, ", pllc_core0/1000/1000); + dprintf(INFO, "PLLC at %dmhz\n", pllc / 1000 / 1000); +} + void platform_early_init(void) { uart_init_early(); intc_init(); -#if BCM2837 +#ifdef ARCH_VPU + //if (xtal_freq == 19200000) { + switch_vpu_to_pllc(); + //} +#endif + +#if BCM2835 +#elif BCM2837 arm_generic_timer_init(INTERRUPT_ARM_LOCAL_CNTPNSIRQ, 0); /* look for a flattened device tree just before the kernel */ @@ -159,12 +215,15 @@ void platform_early_init(void) { #elif BCM2836 arm_generic_timer_init(INTERRUPT_ARM_LOCAL_CNTPNSIRQ, 1000000); +#elif ARCH_VPU #else #error Unknown BCM28XX Variant #endif +#ifdef WITH_KERNEL_VM /* add the main memory arena */ pmm_add_arena(&arena); +#endif #if BCM2837 /* reserve the first 64k of ram, which should be holding the fdt */ @@ -192,13 +251,22 @@ void platform_early_init(void) { } #endif #endif + puts("done platform early init"); } void platform_init(void) { +#if BCM2835 == 1 + gpio_config(0, kBCM2708PinmuxOut); +#endif + +#ifdef RPI4 + gpio_config(42, kBCM2708PinmuxOut); +#endif uart_init(); #if BCM2837 init_framebuffer(); #endif + printf("crystal is %lf MHz\n", (double)xtal_freq/1000/1000); } void platform_dputc(char c) { @@ -215,3 +283,34 @@ int platform_dgetc(char *c, bool wait) { return 0; } +void platform_halt(platform_halt_action suggested_action, + platform_halt_reason reason) { + if (suggested_action == HALT_ACTION_REBOOT) { + dprintf(ALWAYS, "waiting for watchdog\n"); + uart_flush_tx(0); + arch_disable_ints(); + *REG32(PM_WDOG) = PM_PASSWORD | (1 & PM_WDOG_MASK); + uint32_t t = *REG32(PM_RSTC); + t &= PM_RSTC_WRCFG_CLR; + t |= 0x20; + *REG32(PM_RSTC) = PM_PASSWORD | t; + for (;;); + } + dprintf(ALWAYS, "HALT: spinning forever... (reason = %d)\n", reason); + arch_disable_ints(); + for (;;); +} + +void target_set_debug_led(unsigned int led, bool on) { + switch (led) { + case 0: +#ifdef RPI4 + gpio_set(42, on); +#elif BCM2835==1 + gpio_set(0, on); +#endif + break; + default: + break; + } +} diff --git a/platform/bcm28xx/pll/pll_control.c b/platform/bcm28xx/pll/pll_control.c new file mode 100644 index 0000000000..ef6e913d25 --- /dev/null +++ b/platform/bcm28xx/pll/pll_control.c @@ -0,0 +1,557 @@ +#include +#include +#include +#include +#include +#include +#include + +#define PLL_MAX_LOCKWAIT 1000 + +static int cmd_set_pll_freq(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("set_pll_freq", "set pll frequency", &cmd_set_pll_freq) +STATIC_COMMAND_END(pll_control); + +const struct pll_def pll_def[] = { +#if 0 + [PLL_A] = { + .name = "PLLA", + .ana = REG32(A2W_PLLA_ANA0), + .dig = REG32(A2W_PLLA_DIG0), + .enable_bit = A2W_XOSC_CTRL_PLLAEN_SET, + .frac = REG32(A2W_PLLA_FRAC), + .ctrl = REG32(A2W_PLLA_CTRL), + .ndiv_mask = A2W_PLLA_CTRL_NDIV_SET, + .ana1_prescale_bit = 14, + .cm_flock_bit = CM_LOCK_FLOCKA_BIT, + .cm_pll = REG32(CM_PLLA), + .ana_kaip = REG32(A2W_PLLA_ANA_KAIP), + .ana_vco = REG32(A2W_PLLA_ANA_VCO), + }, +#endif + [PLL_B] = { + .name = "PLLB", + .ana = REG32(A2W_PLLB_ANA0), + .dig = REG32(A2W_PLLB_DIG0), + .enable_bit = A2W_XOSC_CTRL_PLLBEN_SET, + .frac = REG32(A2W_PLLB_FRAC), + .ctrl = REG32(A2W_PLLB_CTRL), + .ndiv_mask = A2W_PLLB_CTRL_NDIV_SET, + .ana1_prescale_bit = 14, + .cm_flock_bit = CM_LOCK_FLOCKB_BIT, + .cm_pll = REG32(CM_PLLB), + .ana_kaip = REG32(A2W_PLLB_ANA_KAIP), + .ana_vco = REG32(A2W_PLLB_ANA_VCO), + }, +#if 0 + [PLL_C] = { + .name = "PLLC", + .ana = REG32(A2W_PLLC_ANA0), + .dig = REG32(A2W_PLLC_DIG0), + .enable_bit = A2W_XOSC_CTRL_PLLCEN_SET, + .frac = REG32(A2W_PLLC_FRAC), + .ctrl = REG32(A2W_PLLC_CTRL), + .ndiv_mask = A2W_PLLC_CTRL_NDIV_SET, + .ana1_prescale_bit = 14, + .cm_flock_bit = CM_LOCK_FLOCKC_BIT, + .cm_pll = REG32(CM_PLLC), + .ana_kaip = REG32(A2W_PLLC_ANA_KAIP), + .ana_vco = REG32(A2W_PLLC_ANA_VCO), + }, + [PLL_D] = { + .name = "PLLD", + .ana = REG32(A2W_PLLD_ANA0), + .dig = REG32(A2W_PLLD_DIG0), + .enable_bit = A2W_XOSC_CTRL_PLLDEN_SET, + .frac = REG32(A2W_PLLD_FRAC), + .ctrl = REG32(A2W_PLLD_CTRL), + .ndiv_mask = A2W_PLLD_CTRL_NDIV_SET, + .ana1_prescale_bit = 14, + .cm_flock_bit = CM_LOCK_FLOCKD_BIT, + .cm_pll = REG32(CM_PLLD), + .ana_kaip = REG32(A2W_PLLD_ANA_KAIP), + .ana_vco = REG32(A2W_PLLD_ANA_VCO), + }, + [PLL_H] = { + .name = "PLLH", + .ana = REG32(A2W_PLLH_ANA0), + .dig = REG32(A2W_PLLH_DIG0), + .enable_bit = A2W_XOSC_CTRL_PLLCEN_SET, // official firmware does this (?) + .frac = REG32(A2W_PLLH_FRAC), + .ctrl = REG32(A2W_PLLH_CTRL), + .ndiv_mask = A2W_PLLH_CTRL_NDIV_SET, + .ana1_prescale_bit = 11, + .cm_flock_bit = CM_LOCK_FLOCKH_BIT, + .cm_pll = REG32(CM_PLLH), + .ana_kaip = REG32(A2W_PLLH_ANA_KAIP), + .ana_vco = REG32(A2W_PLLH_ANA_VCO), + }, +#endif +}; + +const struct pll_chan_def pll_chan_def[] = { +#if 0 + [PLL_CHAN_ACORE] = { + .name = "PLLA_CORE", + .ctrl = REG32(A2W_PLLA_CORE), + .chenb_bit = A2W_PLLA_CORE_CHENB_LSB, + .div_mask = A2W_PLLA_CORE_DIV_SET, + .pll = PLL_A, + }, + [PLL_CHAN_APER] = { + .name = "PLLA_PER", + .ctrl = REG32(A2W_PLLA_PER), + .chenb_bit = A2W_PLLA_PER_CHENB_LSB, + .div_mask = A2W_PLLA_PER_DIV_SET, + .pll = PLL_A, + }, + [PLL_CHAN_ADSI0] = { + .name = "PLLA_DSI0", + .ctrl = REG32(A2W_PLLA_DSI0), + .chenb_bit = A2W_PLLA_DSI0_CHENB_LSB, + .div_mask = A2W_PLLA_DSI0_DIV_SET, + .pll = PLL_A, + }, + [PLL_CHAN_ACCP2] = { + .name = "PLLA_CCP2", + .ctrl = REG32(A2W_PLLA_CCP2), + .chenb_bit = A2W_PLLA_CCP2_CHENB_LSB, + .div_mask = A2W_PLLA_CCP2_DIV_SET, + .pll = PLL_A, + }, + [PLL_CHAN_BARM] = { + .name = "PLLB_ARM", + .ctrl = REG32(A2W_PLLB_ARM), + .chenb_bit = A2W_PLLB_ARM_CHENB_LSB, + .div_mask = A2W_PLLB_ARM_DIV_SET, + .pll = PLL_B, + }, + [PLL_CHAN_BSP0] = { + .name = "PLLB_SP0", + .ctrl = REG32(A2W_PLLB_SP0), + .chenb_bit = A2W_PLLB_SP0_CHENB_LSB, + .div_mask = A2W_PLLB_SP0_DIV_SET, + .pll = PLL_B, + }, + [PLL_CHAN_BSP1] = { + .name = "PLLB_SP1", + .ctrl = REG32(A2W_PLLB_SP1), + .chenb_bit = A2W_PLLB_SP1_CHENB_LSB, + .div_mask = A2W_PLLB_SP1_DIV_SET, + .pll = PLL_B, + }, + [PLL_CHAN_BSP2] = { + .name = "PLLB_SP2", + .ctrl = REG32(A2W_PLLB_SP2), + .chenb_bit = A2W_PLLB_SP2_CHENB_LSB, + .div_mask = A2W_PLLB_SP2_DIV_SET, + .pll = PLL_B, + }, + [PLL_CHAN_CCORE0] = { + .name = "PLLC_CORE0", + .ctrl = REG32(A2W_PLLC_CORE0), + .chenb_bit = A2W_PLLC_CORE0_CHENB_LSB, + .div_mask = A2W_PLLC_CORE0_DIV_SET, + .pll = PLL_C, + }, + [PLL_CHAN_CCORE1] = { + .name = "PLLC_CORE1", + .ctrl = REG32(A2W_PLLC_CORE1), + .chenb_bit = A2W_PLLC_CORE1_CHENB_LSB, + .div_mask = A2W_PLLC_CORE1_DIV_SET, + .pll = PLL_C, + }, + [PLL_CHAN_CCORE2] = { + .name = "PLLC_CORE2", + .ctrl = REG32(A2W_PLLC_CORE2), + .chenb_bit = A2W_PLLC_CORE2_CHENB_LSB, + .div_mask = A2W_PLLC_CORE2_DIV_SET, + .pll = PLL_C, + }, + [PLL_CHAN_CPER] = { + .name = "PLLC_PER", + .ctrl = REG32(A2W_PLLC_PER), + .chenb_bit = A2W_PLLC_PER_CHENB_LSB, + .div_mask = A2W_PLLC_PER_DIV_SET, + .pll = PLL_C, + }, + [PLL_CHAN_DCORE] = { + .name = "PLLD_CORE", + .ctrl = REG32(A2W_PLLD_CORE), + .chenb_bit = A2W_PLLD_CORE_CHENB_LSB, + .div_mask = A2W_PLLD_CORE_DIV_SET, + .pll = PLL_D, + }, + [PLL_CHAN_DPER] = { + .name = "PLLD_PER", + .ctrl = REG32(A2W_PLLD_PER), + .chenb_bit = A2W_PLLD_PER_CHENB_LSB, + .div_mask = A2W_PLLD_PER_DIV_SET, + .pll = PLL_D, + }, + [PLL_CHAN_DDSI0] = { + .name = "PLLD_DSI0", + .ctrl = REG32(A2W_PLLD_DSI0), + .chenb_bit = A2W_PLLD_DSI0_CHENB_LSB, + .div_mask = A2W_PLLD_DSI0_DIV_SET, + .pll = PLL_D, + }, + [PLL_CHAN_DDSI1] = { + .name = "PLLD_DSI1", + .ctrl = REG32(A2W_PLLD_DSI1), + .chenb_bit = A2W_PLLD_DSI1_CHENB_LSB, + .div_mask = A2W_PLLD_DSI1_DIV_SET, + .pll = PLL_D, + }, + [PLL_CHAN_HPIX] = { + .name = "PLLH_PIX", + .ctrl = REG32(A2W_PLLH_PIX), + .chenb_bit = A2W_PLLH_PIX_CHENB_LSB, + .div_mask = A2W_PLLH_PIX_DIV_SET, + .pll = PLL_H, + }, + [PLL_CHAN_HRCAL] = { + .name = "PLLH_RCAL", + .ctrl = REG32(A2W_PLLH_RCAL), + .chenb_bit = A2W_PLLH_RCAL_CHENB_LSB, + .div_mask = A2W_PLLH_RCAL_DIV_SET, + .pll = PLL_H, + }, + [PLL_CHAN_HAUX] = { + .name = "PLLH_AUX", + .ctrl = REG32(A2W_PLLH_AUX), + .chenb_bit = A2W_PLLH_AUX_CHENB_LSB, + .div_mask = A2W_PLLH_AUX_DIV_SET, + .pll = PLL_H, + }, +#endif +}; + +static void pll_start(enum pll pll) +{ + const struct pll_def *def = &pll_def[pll]; + uint32_t dig[4]; + + dig[3] = def->dig[3]; + dig[2] = def->dig[2]; + dig[1] = def->dig[1]; + dig[0] = def->dig[0]; + + if (pll == PLL_H) { + // CM_PLLH does not contain any HOLD bits + def->dig[3] = A2W_PASSWORD | dig[3]; + def->dig[2] = A2W_PASSWORD | (dig[2] & ~0xa8UL); + def->dig[1] = A2W_PASSWORD | dig[1]; + } else { + // set all HOLD bits + *def->cm_pll = CM_PASSWORD | (*def->cm_pll | 0xaa); + def->dig[3] = A2W_PASSWORD | dig[3]; + def->dig[2] = A2W_PASSWORD | (dig[2] & ~0x100401UL); + def->dig[1] = A2W_PASSWORD | (dig[1] & ~0x4000UL); + } + def->dig[0] = A2W_PASSWORD | dig[0]; + + *def->ctrl = A2W_PASSWORD | (*def->ctrl | A2W_PLL_CTRL_PRSTN); + + def->dig[3] = A2W_PASSWORD | (dig[3] | 0x42); + def->dig[2] = A2W_PASSWORD | dig[2]; + def->dig[1] = A2W_PASSWORD | dig[1]; + def->dig[0] = A2W_PASSWORD | dig[0]; +} + +#ifdef RPI4 +static uint32_t saved_ana_vco[PLL_NUM] = { + [PLL_A] = 2, + [PLL_B] = 2, + [PLL_C] = 2, + [PLL_D] = 2, +}; +#endif + +int set_pll_freq(enum pll pll, uint32_t freq) { + const struct pll_def *def = &pll_def[pll]; + bool was_prescaled; + bool is_prescaled; + bool was_off; + + if (!freq) { + *def->cm_pll = CM_PASSWORD | CM_PLL_ANARST; + *def->ctrl = A2W_PASSWORD | A2W_PLL_CTRL_PWRDN; + return 0; + } + + was_off = !(*def->ctrl & A2W_PLL_CTRL_PRSTN); + +#if RPI4 + uint32_t ana_vco = saved_ana_vco[pll]; + was_prescaled = BIT_SET(ana_vco, 4); +#else + uint32_t ana3 = def->ana[3]; + uint32_t ana2 = def->ana[2]; + uint32_t ana1 = def->ana[1]; + uint32_t ana0 = def->ana[0]; + was_prescaled = BIT_SET(ana1, def->ana1_prescale_bit); +#endif + + // Divider is a fixed-point number with a 20-bit fractional part. + uint32_t div = (((uint64_t)freq << 20) + xtal_freq / 2) / xtal_freq; + +#if RPI4 + is_prescaled = freq > MHZ_TO_HZ(1600); +#else + is_prescaled = freq > MHZ_TO_HZ(1750); + if (is_prescaled) { + div = (div + 1) >> 1; + ana1 |= 1UL << def->ana1_prescale_bit; + } else { + ana1 &= ~(1UL << def->ana1_prescale_bit); + } +#endif + + // Unmask the reference clock from the crystal oscillator. + *REG32(A2W_XOSC_CTRL) |= A2W_PASSWORD | def->enable_bit; + +#ifdef RPI4 + if (!was_off) { + ana_vco |= 0x10000UL; + *def->ana_vco = A2W_PASSWORD | ana_vco; + } +#endif + +#ifndef RPI4 + // PLLs with a prescaler will set all ANA registers, because there + // is no other way to manipulate the prescaler enable bit. Since + // these registers also contain KA, KI and KP, their new values + // must be set here, not through a write to A2W_PLLx_ANA_KAIP. + if (pll == PLL_H) { + ana0 = (ana0 & ~A2W_PLLH_ANA0_KA_MASK & ~A2W_PLLH_ANA0_KI_LO_MASK) + | (2UL << A2W_PLLH_ANA0_KA_LSB) + | (2UL << A2W_PLLH_ANA0_KI_LO_LSB); + ana1 = (ana1 & ~A2W_PLLH_ANA1_KI_HI_MASK & ~A2W_PLLH_ANA1_KP_MASK) + | (0UL << A2W_PLLH_ANA1_KI_HI_MASK) + | (6UL << A2W_PLLH_ANA1_KP_LSB); + } else { + ana3 = (ana3 & ~A2W_PLL_ANA3_KA_MASK) + | (2UL << A2W_PLL_ANA3_KA_LSB); + ana1 = (ana1 & A2W_PLL_ANA1_KI_MASK & ~A2W_PLL_ANA1_KP_MASK) + | (2UL << A2W_PLL_ANA1_KI_LSB) + | (8UL << A2W_PLL_ANA1_KP_LSB); + } +#endif + + // The Linux driver manipulates the prescaler bit before setting + // a new NDIV if the prescaler is being turned _OFF_. + // I believe it is a bug. + // The programmable divider in a BCM283x apparently cannot cope + // with frequencies above 1750 MHz. This is the reason for adding + // an optional prescaler in the feedback path, so the maximum PLL + // frequency can go up to 3.5 GHz, albeit at the cost of precision. + // If the prescaler is turned off, the divider counter will be + // exposed to the full VCO frequency (i.e. above 1750 MHz). + // On BCM2711, bit 4 of ANA_VCO is manipulated after setting the + // new divider if and only if the rate is going from a frequency + // above 1.6 GHz to a frequency less than or equal 1.6 GHz. + if (!was_prescaled || is_prescaled) { +#ifdef RPI4 + if (is_prescaled) { + *def->ana_kaip = A2W_PASSWORD + | (0 << A2W_PLL_ANA_KAIP_KA_LSB) + | (2 << A2W_PLL_ANA_KAIP_KI_LSB) + | (3 << A2W_PLL_ANA_KAIP_KP_LSB); + ana_vco |= 0x10UL; + *def->ana_vco = A2W_PASSWORD | ana_vco; + } else { + *def->ana_kaip = A2W_PASSWORD + | (0 << A2W_PLL_ANA_KAIP_KA_LSB) + | (2 << A2W_PLL_ANA_KAIP_KI_LSB) + | (5 << A2W_PLL_ANA_KAIP_KP_LSB); + ana_vco &= ~0x10UL; + *def->ana_vco = A2W_PASSWORD | ana_vco; + } +#else + def->ana[3] = A2W_PASSWORD | ana3; + def->ana[2] = A2W_PASSWORD | ana2; + def->ana[1] = A2W_PASSWORD | ana1; + def->ana[0] = A2W_PASSWORD | ana0; +#endif + } + + // Set the PLL multiplier from the oscillator. + *def->frac = A2W_PASSWORD | (div & A2W_PLL_FRAC_MASK); + *def->ctrl = A2W_PASSWORD + | (*def->ctrl + & ~A2W_PLL_CTRL_PWRDN + & ~A2W_PLL_CTRL_PDIV_MASK + & ~def->ndiv_mask) + | (div >> 20) + | (1 << A2W_PLL_CTRL_PDIV_LSB); + + if (was_prescaled && !is_prescaled) { +#ifdef RPI4 + *def->ana_kaip = A2W_PASSWORD + | (0 << A2W_PLL_ANA_KAIP_KA_LSB) + | (2 << A2W_PLL_ANA_KAIP_KI_LSB) + | (5 << A2W_PLL_ANA_KAIP_KP_LSB); + ana_vco &= ~0x10UL; + *def->ana_vco = A2W_PASSWORD | ana_vco; +#else + def->ana[3] = A2W_PASSWORD | ana3; + def->ana[2] = A2W_PASSWORD | ana2; + def->ana[1] = A2W_PASSWORD | ana1; + def->ana[0] = A2W_PASSWORD | ana0; +#endif + } + + // Take the PLL out of reset. + *def->cm_pll = CM_PASSWORD | (*def->cm_pll & ~CM_PLL_ANARST); + + // Wait for the PLL to lock. + unsigned lockwait = PLL_MAX_LOCKWAIT; + while (!BIT_SET(*REG32(CM_LOCK), def->cm_flock_bit)) + if (--lockwait == 0) + break; + +#ifdef RPI4 + if (!was_off) { + ana_vco &= ~0x10000UL; + *def->ana_vco = A2W_PASSWORD | ana_vco; + } + saved_ana_vco[pll] = ana_vco; +#endif + + if (!lockwait) { + dprintf(INFO, "%s won't lock\n", def->name); + return -1; + } + + if (was_off) + pll_start(pll); + + dprintf(SPEW, "%s frequency locked after %u iterations\n", + def->name, PLL_MAX_LOCKWAIT - lockwait); + return 0; +} + +void configure_pll_b(uint32_t freq) { + const struct pll_def *def = &pll_def[PLL_B]; + uint32_t orig_ctrl = *def->ctrl; + *REG32(A2W_XOSC_CTRL) |= A2W_PASSWORD | def->enable_bit; + *def->frac = A2W_PASSWORD | 0xeaaa8; // out of 0x100000 + *def->ctrl = A2W_PASSWORD | 48 | 0x1000; + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLL_DIGRST | CM_PLL_ANARST; + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLL_DIGRST | CM_PLL_ANARST | CM_PLLB_HOLDARM_SET; + + def->ana[3] = A2W_PASSWORD | 0x100; + def->ana[2] = A2W_PASSWORD | 0x0; + def->ana[1] = A2W_PASSWORD | 0x140000; + def->ana[0] = A2W_PASSWORD | 0x0; + + // set dig values + if ((orig_ctrl & A2W_PLL_CTRL_PRSTN) == 0) + pll_start(PLL_B); + + *REG32(A2W_PLLB_ARM) = A2W_PASSWORD | 2; + + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLL_DIGRST | CM_PLL_ANARST | CM_PLLB_HOLDARM_SET | CM_PLLB_LOADARM_SET; + *REG32(CM_PLLB) = CM_PASSWORD | CM_PLL_DIGRST | CM_PLL_ANARST | CM_PLLB_HOLDARM_SET; + *REG32(CM_PLLB) = CM_PASSWORD; + + *REG32(CM_ARMCTL) = CM_PASSWORD | 4 | CM_ARMCTL_ENAB_SET; +} + +static int cmd_set_pll_freq(int argc, const cmd_args *argv) { + if (argc != 3) { + printf("usage: set_pll_freq \n"); + return -1; + } + enum pll pll = argv[1].u; + uint32_t freq = argv[2].u; + return set_pll_freq(pll, freq); +} + +// in A2W_PLLC_CTRL +#define PDIV(n) ((n & 7) << 12) +// in A2W_PLLC_ANA1 +#define KP(n) ((n & 0xf) << 15) +#define KI(n) ((n & 0x7) << 19) +// in A2W_PLLC_ANA3 +#define KA(n) ((n & 7) << 7) +// for all but PLLH +#define ANA1_DOUBLE (1<<14) +// for PLLH +#define PLLH_ANA1_DOUBLE (1<<11) + +void switch_vpu_to_src(int src) { + *REG32(CM_VPUCTL) = CM_PASSWORD | (*REG32(CM_VPUCTL) & ~0xf) | (src & 0xf); + while (*REG32(CM_VPUCTL) & CM_VPUCTL_BUSY_SET) {}; +} + +void setup_pllc(uint64_t target_freq, int core0_div, int per_div) { + int pdiv = 1; + uint64_t xtal_in = xtal_freq; + printf("xtal_in = %llu\n", xtal_in); + uint64_t goal_freq = target_freq / 2; + printf("goal_freq = %llu\n", goal_freq); + uint64_t divisor = (goal_freq<<20) / xtal_in; + int div = divisor >> 20; + int frac = divisor & 0xfffff; + printf("divisor 0x%llx -> %d+(%d/2^20)\n", divisor, div, frac); + printf("ctrl: 0x%x\nfrac: 0x%x\n", *REG32(A2W_PLLC_CTRL), *REG32(A2W_PLLC_FRAC)); + + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_ANARST_SET; + + *REG32(A2W_XOSC_CTRL) |= A2W_PASSWORD | A2W_XOSC_CTRL_PLLCEN_SET; + + *REG32(A2W_PLLC_FRAC) = A2W_PASSWORD | frac; + *REG32(A2W_PLLC_CTRL) = A2W_PASSWORD | div | PDIV(pdiv); + printf("frac set to 0x%x, wanted 0x%x\n", *REG32(A2W_PLLC_FRAC), frac); + + *REG32(A2W_PLLC_ANA3) = A2W_PASSWORD | KA(2); + *REG32(A2W_PLLC_ANA2) = A2W_PASSWORD | 0x0; + *REG32(A2W_PLLC_ANA1) = A2W_PASSWORD | ANA1_DOUBLE | KI(2) | KP(8); + *REG32(A2W_PLLC_ANA0) = A2W_PASSWORD | 0x0; + + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_DIGRST_SET; + + /* hold all */ + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET; + + *REG32(A2W_PLLC_DIG3) = A2W_PASSWORD | 0x0; + *REG32(A2W_PLLC_DIG2) = A2W_PASSWORD | 0x400000; + *REG32(A2W_PLLC_DIG1) = A2W_PASSWORD | 0x5; + *REG32(A2W_PLLC_DIG0) = A2W_PASSWORD | div | 0x555000; + + *REG32(A2W_PLLC_CTRL) = A2W_PASSWORD | div | PDIV(pdiv) | A2W_PLLC_CTRL_PRSTN_SET; + *REG32(A2W_PLLC_FRAC) = A2W_PASSWORD | frac; + + *REG32(A2W_PLLC_DIG3) = A2W_PASSWORD | 0x42; + *REG32(A2W_PLLC_DIG2) = A2W_PASSWORD | 0x500401; + *REG32(A2W_PLLC_DIG1) = A2W_PASSWORD | 0x4005; + *REG32(A2W_PLLC_DIG0) = A2W_PASSWORD | div | 0x555000; + + *REG32(A2W_PLLC_CORE0) = A2W_PASSWORD | core0_div; + + *REG32(A2W_PLLC_PER) = A2W_PASSWORD | per_div; + + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET | CM_PLLC_LOADCORE0_SET; + + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDPER_SET | CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET | CM_PLLC_HOLDCORE0_SET; + + *REG32(CM_PLLC) = CM_PASSWORD | CM_PLLC_DIGRST_SET | + CM_PLLC_HOLDCORE2_SET | + CM_PLLC_HOLDCORE1_SET; + + puts("waiting for lock"); + while (!BIT_SET(*REG32(CM_LOCK), CM_LOCK_FLOCKC_BIT)) {} + printf("ctrl: 0x%x\nfrac: 0x%x\n", *REG32(A2W_PLLC_CTRL), *REG32(A2W_PLLC_FRAC)); + *REG32(A2W_PLLC_FRAC) = A2W_PASSWORD | frac; + printf("ctrl: 0x%x\nfrac: 0x%x\n", *REG32(A2W_PLLC_CTRL), *REG32(A2W_PLLC_FRAC)); +} diff --git a/platform/bcm28xx/pll/pll_read.c b/platform/bcm28xx/pll/pll_read.c new file mode 100644 index 0000000000..1205b4ab77 --- /dev/null +++ b/platform/bcm28xx/pll/pll_read.c @@ -0,0 +1,237 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int cmd_pll_dump(int argc, const cmd_args *argv); +static int cmd_measure_clock(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("dump_pll_state", "print all pll state", &cmd_pll_dump) +STATIC_COMMAND("measure_clock", "measure an internal clock rate", &cmd_measure_clock) +STATIC_COMMAND("measure_clocks", "measure all internal clocks", &cmd_measure_clocks) +STATIC_COMMAND_END(pll); + +uint32_t get_vpu_per_freq(void) { + return clk_get_freq(CM_VPUDIV, CM_VPUCTL); +} + +uint32_t get_uart_base_freq() { + return measure_clock(28); + //return clk_get_freq(CM_UARTDIV, CM_UARTCTL); +} + +uint32_t get_pll_freq(enum pll pll) { + const struct pll_def *def = &pll_def[pll]; + uint32_t ctrl = *def->ctrl; + uint32_t ndiv = ctrl & def->ndiv_mask; + uint32_t pdiv = (ctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_LSB; + if (pdiv == 0) + return 0; + uint32_t frac = *def->frac & A2W_PLL_FRAC_MASK; + uint32_t div = (ndiv << 20) | frac; +#ifndef RPI4 + if (BIT_SET(def->ana[1], def->ana1_prescale_bit)) + div <<= 1; +#endif + uint64_t mult1 = (uint64_t)div * xtal_freq / pdiv; + return mult1 >> 20; +} + +uint32_t get_pll_chan_freq(enum pll_chan chan) { + const struct pll_chan_def *def = &pll_chan_def[chan]; + printf("def is 0x%x\n", def); + uint32_t ctrl_val = *def->ctrl; + uint32_t div = ctrl_val & def->div_mask; + if (BIT_SET(ctrl_val, def->chenb_bit) || div == 0) + return 0; + return get_pll_freq(def->pll) / div; +} + +uint32_t clk_get_freq(uint32_t divreg, uint32_t ctlreg) { + uint32_t div = *REG32(divreg); + if (div == 0) return 0; + uint64_t input_freq = clk_get_input_freq(ctlreg); + return ((input_freq << 12) / div); +} + +uint32_t clk_get_input_freq(uint32_t ctlreg) { + uint32_t ctl = *REG32(ctlreg); + switch (ctl & 0xf) { + case 0: // GND clock source + return 0; + case 1: // crystal oscilator + return xtal_freq; + case 2: // test debug 0 + case 3: // test debug 1 + return 0; + case 4: // plla_core + return get_pll_chan_freq(PLL_CHAN_ACORE); + case 5: // pllc_core0 + return get_pll_chan_freq(PLL_CHAN_CCORE0); + case 6: // plld_per + return get_pll_chan_freq(PLL_CHAN_DPER); + case 7: // pllh_aux + return get_pll_chan_freq(PLL_CHAN_HAUX); + case 8: // pllc_core1 + return get_pll_chan_freq(PLL_CHAN_CCORE1); + case 9: // pllc_core2 + return get_pll_chan_freq(PLL_CHAN_CCORE2); + default: + return 0; + } +} + +static uint32_t dump_pll_state(enum pll pll) { + const struct pll_def *def = &pll_def[pll]; + uint32_t ctrl_val = *def->ctrl; + uint32_t frac_value = *def->frac; + dprintf(INFO, "A2W_%s_CTRL: 0x%x\n", def->name, ctrl_val); + dprintf(INFO, "A2W_%s_FRAC: 0x%x\n", def->name, frac_value); + dprintf(INFO, "CM_%s: 0x%x\n", def->name, *(def->cm_pll)); + uint32_t freq = get_pll_freq(pll); + dprintf(INFO, "%s freq: %u\n", def->name, freq); + return freq; +} + +static void dump_pll_chan_state(enum pll_chan pll_chan) { + const struct pll_chan_def *def = &pll_chan_def[pll_chan]; + uint32_t ctrl_val = *def->ctrl; + dprintf(INFO, "\tA2W_%s: 0x%x\n", def->name, ctrl_val); + uint32_t freq = get_pll_chan_freq(pll_chan); + dprintf(INFO, "\t%s freq: %u\n", def->name, freq); +} + +static void dump_plldiv2_state(const char *prefix, uint32_t ctrl, uint32_t div) { + uint32_t ctrl_val = *REG32(ctrl); + uint32_t div_val = *REG32(div); + dprintf(INFO, "CM_%sCTL: 0x%x\n", prefix, ctrl_val); + dprintf(INFO, "CM_%sDIV: 0x%x\n", prefix, div_val); +} + +static int cmd_pll_dump(int argc, const cmd_args *argv) { + enum pll pll; + for (pll = 0; pll < PLL_NUM; ++pll) { + uint32_t freq = dump_pll_state(pll); + if (freq > 0) { + enum pll_chan pll_chan; + for (pll_chan = 0; pll_chan < PLL_CHAN_NUM; ++pll_chan) + if (pll_chan_def[pll_chan].pll == pll) + dump_pll_chan_state(pll_chan); + } + } + + dump_plldiv2_state("VPU", CM_VPUCTL, CM_VPUDIV); + printf("CM_LOCK: 0x%x\n", *REG32(CM_LOCK)); + return 0; +} + +// based on https://github.com/raspberrypi/linux/blob/rpi-4.19.y/drivers/clk/bcm/clk-bcm2835.c#L356 +#define CM_KILL 0x40 +#define CM_BUSY 0x80 +#define CM_SRC_MASK 0xf +#define CM_SRC_BITS 4 +#define CM_TCNT_SRC1_SHIFT 12 + +int measure_clock(int mux) { + int divisor = 1000; + *REG32(CM_TCNTCTL) = CM_PASSWORD | CM_KILL; + *REG32(CM_TCNTCTL) = CM_PASSWORD | (mux & CM_SRC_MASK) | (mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT; + *REG32(CM_OSCCOUNT) = CM_PASSWORD | (xtal_freq / divisor); + udelay(1); + while (*REG32(CM_OSCCOUNT)) { + } + + while (*REG32(CM_TCNTCTL) & CM_BUSY) { + } + + int count = *REG32(CM_TCNTCNT); + *REG32(CM_TCNTCNT) = CM_PASSWORD | 0; + return count * divisor; +} + +static const char *clock_names[] = { + [1] = "H264", + [2] = "ISP", + [3] = "SDRAM", + [4] = "V3D", // guess, from start.elf + [5] = "VPU", + [6] = "OTP", + [7] = "ARM", // guess, from start.elf + [9] = "TIMER", // guess, from start.elf + [0xa] = "PVTMON", // VC6 only, from a start.elf + [0xc] = "dsi0p", + "dsi1p", + "cam0", + "cam1", + [0x11] = "dpi", + "dsi0e", + "dsi1e", + "gp0", + "gp1", + "hsm", + "pcm", + "pwm", + "slim", + [0x1b] = "smi", + "uart", + "vec", + [0x26] = "aveo", + [0x26] = "emmc", + [0x2a] = "emmc2" +}; + +static int cmd_measure_clock(int argc, const cmd_args *argv) { + if (argc != 2) { + puts("error, missing argument"); + // A = default-freq when netbooting a custom bootcode.bin + // B = default when netbooting kernel.img under closed fw on a pi2 + // reg offset A B + puts("1 - H264"); // CM_H264 0x28 + puts("2 - ISP"); // CM_ISP 0x30 + puts("3 - sdram"); // CM_SDC 0xa8 + puts("4 - V3D"); // 250mhz + puts("5 - VPU"); // CM_VPU 0x08 100,000khz 250mhz + puts("6 - OTP"); // CM_OTP 0x90 4,800khz 4.8mhz + puts("9 - ???"); // 500khz 500khz + puts("10 - ???"); // 1.92mhz + puts("12 - dsi0p"); // CM_DSI0P 0x60 + puts("13 - dsi1p"); // CM_DSI1P 0x160 + puts("14 - cam0"); // CM_CAM0 0x40 + puts("15 - cam1"); // CM_CAM1 0x48 + puts("17 - dpi"); // CM_DPI 0x68 + puts("18 - dsi0e"); // CM_DSI0E 0x58 + puts("19 - dsi1e"); // CM_DSI1E 0x158 + puts("20 - gp0"); // CM_GP0 0x70 + puts("21 - gp1"); // CM_GP1 0x78 25mhz 25mhz + puts("22 - hsm"); // CM_HSM 0x88 + puts("23 - pcm"); // CM_PCM 0x98 + puts("24 - pwm"); // CM_PWM 0xa0 + puts("25 - slim"); // CM_SLIM 0xa8 + puts("27 - smi"); // CM_SMI 0xb0 + puts("28 - uart"); // CM_UART 0xf0 1,916khz 48mhz + puts("29 - vec"); // CM_VEC 0xf8 108mhz + puts("30 - ???"); // 44khz 44khz + puts("38 - aveo"); // CM_AVEO 0x1b8 + puts("39 - emmc"); // CM_EMMC 0x1c0 200mhz + puts("42 - emmc2"); // CM_EMMC2 0x1d0 + return 0; + } + int mux = argv[1].u; + int count = measure_clock(mux); + printf("count is %d\n", count); + return 0; +} + +int cmd_measure_clocks(int argc, const cmd_args *argv) { + for (int i=0; i<43; i++) { + int count = measure_clock(i); + printf("clock #%d(%s) is %d\n", i, clock_names[i], count); + } + return 0; +} diff --git a/platform/bcm28xx/pll/rules.mk b/platform/bcm28xx/pll/rules.mk new file mode 100644 index 0000000000..7018cb8bc1 --- /dev/null +++ b/platform/bcm28xx/pll/rules.mk @@ -0,0 +1,9 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/pll_read.c \ + $(LOCAL_DIR)/pll_control.c \ + +include make/module.mk diff --git a/platform/bcm28xx/power/include/platform/bcm28xx/power.h b/platform/bcm28xx/power/include/platform/bcm28xx/power.h new file mode 100644 index 0000000000..85b3c2b0ed --- /dev/null +++ b/platform/bcm28xx/power/include/platform/bcm28xx/power.h @@ -0,0 +1,49 @@ +#pragma once + +#include +#include + +#define PM_BASE (BCM_PERIPH_BASE_VIRT + 0x100000) +#define PM_PASSWORD 0x5a000000 + +#define PM_AUDIO (PM_BASE + 0x004) + +#define PM_RSTC (PM_BASE + 0x1c) +#define PM_RSTC_WRCFG_CLR 0xffffffcf // mask to keep everything but the watchdog config +// https://github.com/raspberrypi/linux/issues/932 +// docs for RSTS +// definitions from broadcom/bcm2708_chip/cpr_powman.h +// comments from github issue +#define PM_RSTS (PM_BASE + 0x20) +#define PM_RSTS_HADPOR_SET 0x00001000 // bit 12 had power-on reset +#define PM_RSTS_HADSRH_SET 0x00000400 // bit 10 had software hard reset +#define PM_RSTS_HADSRF_SET 0x00000200 // bit 9 had software full reset +#define PM_RSTS_HADSRQ_SET 0x00000100 // bit 8 had software quick reset +#define PM_RSTS_HADWRH_SET 0x00000040 // bit 6 had watchdog hard reset +#define PM_RSTS_HADWRF_SET 0x00000020 // bit 5 had watchdog full reset +#define PM_RSTS_HADWRQ_SET 0x00000010 // bit 4 had watchdog quick reset +#define PM_RSTS_HADDRH_SET 0x00000004 // bit 2 had debugger hard reset +#define PM_RSTS_HADDRF_SET 0x00000002 // bit 1 had debugger full reset +#define PM_RSTS_HADDRQ_SET 0x00000001 // bit 0 had debugger quick reset +#define PM_WDOG (PM_BASE + 0x24) +#define PM_WDOG_MASK 0x00000fff +#define PM_USB (PM_BASE + 0x5c) +#define PM_SMPS (PM_BASE + 0x6c) +#define PM_SPAREW (PM_BASE + 0x74) +#define PM_IMAGE (PM_BASE + 0x108) +#define PM_GRAFX (PM_BASE + 0x10c) +#define PM_PROC (PM_BASE + 0x110) + +#define PM_ENABLE BV(12) +#define PM_V3DRSTN BV(6) +#define PM_ISFUNC BV(5) +#define PM_MRDONE BV(4) +#define PM_MEMREP BV(3) +#define PM_ISPOW BV(2) +#define PM_POWOK BV(1) +#define PM_POWUP BV(0) + +void power_up_image(void); +void power_up_usb(void); +void power_domain_on(volatile uint32_t *reg, uint32_t rstn); +void power_arm_start(void); diff --git a/platform/bcm28xx/power/power.c b/platform/bcm28xx/power/power.c new file mode 100644 index 0000000000..6665540f00 --- /dev/null +++ b/platform/bcm28xx/power/power.c @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include +#include + +#define PM_PROC_ARMRSTN_CLR 0xffffffbf +#define PM_IMAGE_PERIRSTN_SET 0x00000040 +#define PM_IMAGE_H264RSTN_SET 0x00000080 +#define PM_IMAGE_ISPRSTN_SET 0x00000100 + +static int cmd_pm_dump(int argc, const cmd_args *argv); +static int cmd_pm_usb_on(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("pm_dump_all", "dump power domain states", &cmd_pm_dump) +STATIC_COMMAND("pm_usb_on", "enable usb power domain", &cmd_pm_usb_on) +STATIC_COMMAND_END(pm); + +void power_up_image(void) { + puts("image domain on..."); + //dumpreg(PM_IMAGE); + *REG32(PM_IMAGE) |= PM_PASSWORD | 0x10000 | BV(6); // CFG = 1 +#if 0 + printf("PM_IMAGE: 0x%x\n", *REG32(PM_IMAGE)); + *REG32(PM_IMAGE) |= PM_PASSWORD | 1; // POWUP = 1 + for (int i=0; i<10; i++) { + if (*REG32(PM_IMAGE) & 2) { // if power ok + break; + } + udelay(1); + if (i == 9) puts("PM_IMAGE timeout"); + } + printf("PM_IMAGE: 0x%x\n", *REG32(PM_IMAGE)); + *REG32(PM_IMAGE) = PM_PASSWORD | (*REG32(PM_IMAGE) & ~1); // POWUP = 0 + + *REG32(PM_IMAGE) |= PM_PASSWORD | 0x30000; // CFG = 3 + *REG32(PM_IMAGE) |= PM_PASSWORD | 1; // POWUP = 1 + for (int i=0; i<10; i++) { + if (*REG32(PM_IMAGE) & 2) { // if power ok + break; + } + udelay(1); + if (i == 9) puts("PM_IMAGE timeout"); + } + printf("PM_IMAGE: 0x%x\n", *REG32(PM_IMAGE)); + *REG32(PM_IMAGE) |= PM_PASSWORD | 0x40; +#endif + //dumpreg(PM_IMAGE); + power_domain_on(REG32(PM_IMAGE), ~(PM_IMAGE_ISPRSTN_SET | PM_IMAGE_H264RSTN_SET | PM_IMAGE_PERIRSTN_SET)); + //dumpreg(PM_IMAGE); +} + +void power_up_usb(void) { + // TODO, move power domain code into its own driver + power_up_image(); + + puts("usb power on..."); + *REG32(PM_USB) = PM_PASSWORD | 1; + udelay(600); + + //dumpreg(CM_PERIICTL); + *REG32(CM_PERIIDIV) = CM_PASSWORD | 0x1000; + *REG32(CM_PERIICTL) |= CM_PASSWORD | 0x40; + //dumpreg(CM_PERIICTL); + *REG32(CM_PERIICTL) = (*REG32(CM_PERIICTL) & 0xffffffbf) | CM_PASSWORD; + //dumpreg(CM_PERIICTL); + //dumpreg(CM_PERIIDIV); + + *REG32(PM_IMAGE) |= PM_PASSWORD | PM_V3DRSTN; + *REG32(CM_PERIICTL) |= CM_PASSWORD | 0x40; +} + +void power_domain_on(volatile uint32_t *reg, uint32_t rstn) { + puts("bringing domain up"); + /* If it was already powered on by the fw, leave it that way. */ + if (*REG32(reg) & PM_POWUP) { + puts("already on"); + return; + } + /* Enable power */ + *REG32(reg) |= PM_PASSWORD | PM_POWUP; + + puts("waiting"); + while (!(*REG32(reg) & PM_POWOK)) { + udelay(1); // TODO, add timeout + } + + /* Disable electrical isolation */ + *REG32(reg) |= PM_PASSWORD | PM_ISPOW; + + puts("mem rep"); + /* Repair memory */ + *REG32(reg) |= PM_PASSWORD | PM_MEMREP; + while (!(*REG32(reg) & PM_MRDONE)) { + udelay(1); // TODO, add timeout + } + /* Disable functional isolation */ + *REG32(reg) |= PM_PASSWORD | PM_ISFUNC; +} + +void power_arm_start(void) { + power_domain_on(REG32(PM_PROC), PM_PROC_ARMRSTN_CLR); +} + +static void dump_power_domain(const char *name, uint32_t pmreg) { + volatile uint32_t *reg = REG32(pmreg); + uint32_t v = *reg; + printf("%8s: 0x%x == 0x%08x ", name, pmreg, v); + printf("%2s %2s %2s", v & PM_POWUP ? "UP":"", v & PM_POWOK ? "OK":"", v & PM_ENABLE ? "EN":""); + if ((pmreg == PM_IMAGE) && (v & BV(7))) printf(" H264RSTN"); + puts(""); +} + +static int cmd_pm_dump(int argc, const cmd_args *argv) { + dump_power_domain("PM_USB", PM_USB); + dump_power_domain("PM_SMPS", PM_SMPS); + dump_power_domain("PM_IMAGE", PM_IMAGE); + dump_power_domain("PM_GRAFX", PM_GRAFX); + dump_power_domain("PM_PROC", PM_PROC); + return 0; +} +static int cmd_pm_usb_on(int argc, const cmd_args *argv) { + power_up_usb(); + return 0; +} diff --git a/platform/bcm28xx/power/rules.mk b/platform/bcm28xx/power/rules.mk new file mode 100644 index 0000000000..5f817e8e27 --- /dev/null +++ b/platform/bcm28xx/power/rules.mk @@ -0,0 +1,8 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/power.c \ + +include make/module.mk diff --git a/platform/bcm28xx/print_timestamp.c b/platform/bcm28xx/print_timestamp.c new file mode 100644 index 0000000000..53a22e47ad --- /dev/null +++ b/platform/bcm28xx/print_timestamp.c @@ -0,0 +1,9 @@ +#include +#include +#include + +void print_timestamp() { + uint32_t clock_lo = *REG32(ST_CLO); + + printf("%3d.%06d ", clock_lo / 1000000, clock_lo % 1000000); +} diff --git a/platform/bcm28xx/rpi-ddr2/LICENSE b/platform/bcm28xx/rpi-ddr2/LICENSE new file mode 100644 index 0000000000..8f854e4e14 --- /dev/null +++ b/platform/bcm28xx/rpi-ddr2/LICENSE @@ -0,0 +1,241 @@ +Code copyrighted to Broadom Corporation is released under BSD 3-Clause License +============================================================================== + +Copyright (c) 2009-2014, Broadcom Corporation All rights reserved. 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autoram_dram_init(uint level) { + sdram_init(); + uint32_t start = UNCACHED_RAM | (1 * MB); + uint32_t length = 10 * MB; + novm_add_arena("dram", start, length); +} +LK_INIT_HOOK(autoram, &autoram_dram_init, LK_INIT_LEVEL_PLATFORM_EARLY + 1); diff --git a/platform/bcm28xx/rpi-ddr2/autoram/rules.mk b/platform/bcm28xx/rpi-ddr2/autoram/rules.mk new file mode 100644 index 0000000000..9bf99ac42a --- /dev/null +++ b/platform/bcm28xx/rpi-ddr2/autoram/rules.mk @@ -0,0 +1,11 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_DEPS += platform/bcm28xx/rpi-ddr2 + +MODULE_SRCS += $(LOCAL_DIR)/autoram.c + +GLOBAL_DEFINES += NOVM_MAX_ARENAS=2 NOVM_DEFAULT_ARENA=0 + +include make/module.mk diff --git a/platform/bcm28xx/rpi-ddr2/ddr2.h b/platform/bcm28xx/rpi-ddr2/ddr2.h new file mode 100644 index 0000000000..0fef492612 --- /dev/null +++ b/platform/bcm28xx/rpi-ddr2/ddr2.h @@ -0,0 +1,113 @@ +#pragma once + +// heavily copied from bcm2708_chip/sdc_ctrl.h +// from the rpi-open-firmware repo +// (from the v3d source release??) +// TODO, replace this with the official headers + +#define SD_CS_SDUP_SET 0x00008000 +#define SD_CS_DEL_KEEP_SET 0x00040000 +#define SD_MR_RDATA_SET 0x00ff0000 +#define SD_MR_RDATA_LSB 16 +#define SD_MR_RW_SET 0x10000000 +#define SD_MR_HI_Z_SET 0x20000000 +#define SD_MR_TIMEOUT_SET 0x40000000 +#define SD_MR_DONE_SET 0x80000000 + +#define CM_SDCCTL 0x7e1011a8 +#define CM_SDCCTL_SRC_CLR 0xfffffff0 +#define CM_SDCCTL_ENAB_SET 0x00000010 +#define CM_SDCCTL_BUSY_SET 0x00000080 +#define CM_SDCCTL_CTRL_CLR 0xffff0fff +#define CM_SDCCTL_CTRL_LSB 12 +#define CM_SDCCTL_ACCPT_SET 0x00010000 +#define CM_SDCCTL_UPDATE_SET 0x00020000 +#define CM_SDCCTL_UPDATE_CLR 0xfffdffff +#define CM_SDCDIV 0x7e1011ac +#define CM_SDCDIV_DIV_LSB 12 +#define CM_SDCCTL_CTRL_SET 0x0000f000 + +#define SD_CS 0x7ee00000 +#define SD_CS_RESTRT_SET 0x00000001 +#define SD_CS_EN_SET 0x00000002 +#define SD_CS_DPD_SET 0x00000004 +#define SD_CS_STBY_SET 0x00000008 +#define SD_CS_STATEN_SET 0x00000040 +#define SD_CS_STOP_SET 0x00000080 +#define SD_CS_ASHDN_T_LSB 19 +#define SD_SA 0x7ee00004 +#define SD_SA_POWSAVE_SET 0x00000001 +#define SD_SA_CLKSTOP_SET 0x00000080 +#define SD_SA_PGEHLDE_SET 0x00000100 +#define SD_SA_RFSH_T_LSB 16 +#define SD_SB 0x7ee00008 +#define SD_SB_COLBITS_LSB 0 +#define SD_SB_ROWBITS_LSB 2 +#define SD_SB_BANKLOW_LSB 5 +#define SD_SB_EIGHTBANK_SET 0x00000010 +#define SD_SB_REORDER_SET 0x00000080 +#define SD_SC 0x7ee0000c +#define SD_SC_WL_LSB 0 +#define SD_SC_T_WTR_LSB 4 +#define SD_SC_T_WR_LSB 8 +#define SD_SC_T_RRD_LSB 20 +#define SD_SC_T_RFC_LSB 24 +#define SD_PT2 0x7ee00010 +#define SD_PT2_T_INIT5_LSB 0 +#define SD_PT1 0x7ee00014 +#define SD_PT1_T_INIT1_LSB 0 +#define SD_PT1_T_INIT3_LSB 8 +#define SD_PHYC 0x7ee00060 +#define SD_PHYC_PHYRST_SET 0x00000001 +#define SD_MRT 0x7ee00064 +#define SD_MRT_T_MRW_LSB 0 +#define SD_MR 0x7ee00090 +#define SD_SD 0x7ee00094 +#define SD_SD_T_RCD_LSB 0 +#define SD_SD_T_RPpb_LSB 4 +#define SD_SD_T_RAS_LSB 8 +#define SD_SD_T_XP_LSB 16 +#define SD_SD_T_RC_LSB 20 +#define SD_SD_T_RPab_LSB 28 +#define SD_SE 0x7ee00098 +#define SD_SE_T_XSR_LSB 0 +#define SD_SE_T_RTP_LSB 8 +#define SD_SE_T_FAW_LSB 12 +#define SD_SE_RL_LSB 20 +#define SD_SE_RL_EN_LSB 28 + +#define APHY_CSR_GLBL_ADDR_DLL_RESET 0x7ee06004 +#define APHY_CSR_GLBL_ADR_DLL_LOCK_STAT 0x7ee06020 +#define APHY_CSR_DDR_PLL_GLOBAL_RESET 0x7ee06024 +#define APHY_CSR_DDR_PLL_POST_DIV_RESET 0x7ee06028 +#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0 0x7ee0602c +#define APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1 0x7ee06030 +#define APHY_CSR_DDR_PLL_MDIV_VALUE 0x7ee06034 +#define APHY_CSR_DDR_PLL_LOCK_STATUS 0x7ee06048 +#define APHY_CSR_DDR_PLL_PWRDWN 0x7ee06058 +#define APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL 0x7ee06068 +#define APHY_CSR_ADDR_PVT_COMP_CTRL 0x7ee06070 +#define APHY_CSR_ADDR_PVT_COMP_STATUS 0x7ee06078 +#define APHY_CSR_PHY_BIST_CNTRL_SPR 0x7ee06080 + +#define DPHY_CSR_GLBL_DQ_DLL_RESET 0x7ee07004 +#define DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT 0x7ee07018 +#define DPHY_CSR_BOOT_READ_DQS_GATE_CTRL 0x7ee07040 +#define DPHY_CSR_DQ_PHY_MISC_CTRL 0x7ee07048 +#define DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL 0x7ee0704c +#define DPHY_CSR_DQ_PAD_MISC_CTRL 0x7ee07050 +#define DPHY_CSR_DQ_PVT_COMP_CTRL 0x7ee07054 +#define DPHY_CSR_DQ_PVT_COMP_STATUS 0x7ee0705c + +#define A2W_PASSWORD 0x5a000000 + +#define A2W_XOSC_CTRLR HW_REGISTER_RW( 0x7e102990 ) +#define A2W_SMPS_LDO0 0x7e1020d0 +#define A2W_SMPS_LDO1 0x7e1020d4 + +// copied from rpi-open-firmware +#define LPDDR2_MR_DEVICE_FEATURE_2 2 +#define LPDDR2_MR_IO_CONFIG 3 +#define LPDDR2_MR_MANUFACTURER_ID 5 +#define LPDDR2_MR_METRICS 8 +#define LPDDR2_MR_CALIBRATION 10 diff --git a/platform/bcm28xx/rpi-ddr2/rules.mk b/platform/bcm28xx/rpi-ddr2/rules.mk new file mode 100644 index 0000000000..b7e707cf31 --- /dev/null +++ b/platform/bcm28xx/rpi-ddr2/rules.mk @@ -0,0 +1,7 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += $(LOCAL_DIR)/sdram.c + +include make/module.mk diff --git a/platform/bcm28xx/rpi-ddr2/sdram.c b/platform/bcm28xx/rpi-ddr2/sdram.c new file mode 100644 index 0000000000..4b994b8be7 --- /dev/null +++ b/platform/bcm28xx/rpi-ddr2/sdram.c @@ -0,0 +1,597 @@ +/*============================================================================= +Copyright (C) 2016-2017 Authors of rpi-open-firmware +Copyright (C) 2016 Julian Brown +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +VideoCoreIV SDRAM initialization code. + +=============================================================================*/ + +#include "ddr2.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ALWAYS_INLINE __attribute__((always_inline)) inline + +const char* size_to_string[] = { + "1GB", + "512MB", + "256MB", + "128MB", + "2GB", + "4GB", + "UNKNOWN" +}; + +enum RamSize g_RAMSize = kRamSizeUnknown; + +/* + Registers + ========= + + SC: AC Timing (Page 202) + SB: ??? + SD: AC Timing (Page 202) + SE: AC Timing (Page 202) + + PT1: + Minimum Idle time after first CKE assertion + Minimum CKE low time after completion of power ramp + PT2: + DAI Duration + */ + +#define MR_REQUEST_SUCCESS(x) ((SD_MR_TIMEOUT_SET & x) != SD_MR_TIMEOUT_SET) +#define MR_GET_RDATA(x) ((x & SD_MR_RDATA_SET) >> SD_MR_RDATA_LSB) + +#define SIP_DEBUG(x) x +#define SCLKU_DEBUG(x) //SIP_DEBUG(x) + +#define BIST_pvt 0x20 +#define BIST_reset 0x10 + +#define PVT_calibrate_request 0x1 + +#define logf(fmt, ...) print_timestamp(); printf("[SDRAM:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__); + +static const char* lpddr2_manufacturer_name(uint32_t mr) { + switch (mr) { + case 1: + return "Samsung"; + case 2: + return "Qimonda"; + case 3: + return "Elpida"; + case 4: + return "Etron"; + case 5: + return "Nanya"; + case 6: + return "Hynix"; + default: + return "Unknown"; + } +} + +#define MR8_DENSITY_SHIFT 0x2 +#define MR8_DENSITY_MASK (0xF << 0x2) + +static enum RamSize lpddr2_size(uint32_t mr) { + switch (mr) { + case 0x58: + return kRamSize1GB; + case 0x18: + return kRamSize512MB; + case 0x14: + return kRamSize256MB; + case 0x10: + return kRamSize128MB; + default: + return kRamSizeUnknown; + } +} + +/***************************************************************************** + * Guts + *****************************************************************************/ + +ALWAYS_INLINE inline void clkman_update_begin(void) { + *REG32(CM_SDCCTL) |= CM_PASSWORD | CM_SDCCTL_UPDATE_SET; + SCLKU_DEBUG(logf("waiting for ACCPT (%X) ...\n", *REG32(CM_SDCCTL))); + for (;;) if (*REG32(CM_SDCCTL) & CM_SDCCTL_ACCPT_SET) break; + SCLKU_DEBUG(logf("ACCPT received! (%X)\n", *REG32(CM_SDCCTL))); +} + +ALWAYS_INLINE inline void clkman_update_end(void) { + *REG32(CM_SDCCTL) = CM_PASSWORD | (*REG32(CM_SDCCTL) & CM_SDCCTL_UPDATE_CLR); + SCLKU_DEBUG(logf("waiting for ACCPT clear (%X) ...\n", *REG32(CM_SDCCTL))); + for (;;) if ((*REG32(CM_SDCCTL) & CM_SDCCTL_ACCPT_SET) == 0) break; + SCLKU_DEBUG(logf("ACCPT cleared! (%X)\n", *REG32(CM_SDCCTL))); +} + +ALWAYS_INLINE void reset_phy_dll(void) { + SIP_DEBUG(logf("resetting aphy and dphy dlls ...\n")); + + /* politely tell sdc that we'll be messing with address lines */ + *REG32(APHY_CSR_PHY_BIST_CNTRL_SPR) = 0x30; + + *REG32(DPHY_CSR_GLBL_DQ_DLL_RESET) = 0x1; + *REG32(APHY_CSR_GLBL_ADDR_DLL_RESET) = 0x1; + + /* stall ... */ + *REG32(SD_CS); + *REG32(SD_CS); + *REG32(SD_CS); + *REG32(SD_CS); + + *REG32(DPHY_CSR_GLBL_DQ_DLL_RESET) = 0x0; + *REG32(APHY_CSR_GLBL_ADDR_DLL_RESET) = 0x0; + + SIP_DEBUG(logf("waiting for dphy master dll to lock ...\n")); + for (;;) if ((*REG32(DPHY_CSR_GLBL_MSTR_DLL_LOCK_STAT) & 0xFFFF) == 0xFFFF) break; + SIP_DEBUG(logf("dphy master dll locked!\n")); +} + +typedef struct { + uint32_t max_freq; + uint32_t RL; + uint32_t tRPab; + uint32_t tRPpb; + uint32_t tRCD; + uint32_t tWR; + uint32_t tRASmin; + uint32_t tRRD; + uint32_t tWTR; + uint32_t tXSR; + uint32_t tXP; + uint32_t tRFCab; + uint32_t tRTP; + uint32_t tCKE; + uint32_t tCKESR; + uint32_t tDQSCKMAXx2; + uint32_t tRASmax; + uint32_t tFAW; + uint32_t tRC; + uint32_t tREFI; + + uint32_t tINIT1; + uint32_t tINIT3; + uint32_t tINIT5; + + uint32_t rowbits; + uint32_t colbits; + uint32_t banklow; +} lpddr2_timings_t; + +// 7.8 / (1.0 / 400) + +lpddr2_timings_t g_InitSdramParameters = { + /* SA (us) */ + .tREFI = 3113, //Refresh rate: 3113 * (1.0 / 400) = 7.78us + /* SC (ns) */ + .tRFCab = 50, + .tRRD = 2, + .tWR = 7, + .tWTR = 4, + /* SD (ns) */ + .tRPab = 7, + .tRC = 24, + .tXP = 1, + .tRASmin = 15, + .tRPpb = 6, + .tRCD = 6, + /* SE (ns) */ + .tFAW = 18, + .tRTP = 1, + .tXSR = 54, + /* PT */ + .tINIT1 = 40, // Minimum CKE low time after completion of power ramp: 40 * (1.0 / 0.4) = 100ns + .tINIT3 = 79800, // Minimum Idle time after first CKE assertion: 79800 * (1.0 / 400) = 199.5us ~ 200us + .tINIT5 = 3990, //Max DAI: 3990* (1.0 / 400) = 9.9us ~ 10us + /* SB */ + .rowbits = 2, + .colbits = 1, + .banklow = 2 +}; + +static void reset_with_timing(lpddr2_timings_t* T) { + uint32_t ctrl = 0x4; + + *REG32(SD_CS) = (*REG32(SD_CS) & ~(SD_CS_DEL_KEEP_SET|SD_CS_DPD_SET|SD_CS_RESTRT_SET)) | SD_CS_STBY_SET; + + /* wait for SDRAM controller to go down */ + SIP_DEBUG(logf("waiting for SDRAM controller to go down (%X) ...\n", *REG32(SD_CS))); + for (;;) if ((*REG32(SD_CS) & SD_CS_SDUP_SET) == 0) break; + SIP_DEBUG(logf("SDRAM controller down!\n")); + + /* disable SDRAM clock */ + clkman_update_begin(); + *REG32(CM_SDCCTL) = (*REG32(CM_SDCCTL) & ~(CM_SDCCTL_ENAB_SET|CM_SDCCTL_CTRL_SET)) | CM_PASSWORD; + clkman_update_end(); + + SIP_DEBUG(logf("SDRAM clock disabled!\n")); + + /* + * Migrate over to master PLL. + */ + + *REG32(APHY_CSR_DDR_PLL_PWRDWN) = 0; + *REG32(APHY_CSR_DDR_PLL_GLOBAL_RESET) = 0; + *REG32(APHY_CSR_DDR_PLL_POST_DIV_RESET) = 0; + + /* 400MHz */ + *REG32(APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL0) = (1 << 16) | 0x53; + *REG32(APHY_CSR_DDR_PLL_VCO_FREQ_CNTRL1) = 0; + *REG32(APHY_CSR_DDR_PLL_MDIV_VALUE) = 0; + + *REG32(APHY_CSR_DDR_PLL_GLOBAL_RESET) = 1; + + SIP_DEBUG(logf("waiting for master ddr pll to lock ...\n")); + for (;;) if (*REG32(APHY_CSR_DDR_PLL_LOCK_STATUS) & (1 << 16)) break; + SIP_DEBUG(logf("master ddr pll locked!\n")); + + *REG32(APHY_CSR_DDR_PLL_POST_DIV_RESET) = 1; + + clkman_update_begin(); + *REG32(CM_SDCCTL) = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (*REG32(CM_SDCCTL) & CM_SDCCTL_CTRL_CLR); + clkman_update_end(); + + *REG32(SD_SA) = + (T->tREFI << SD_SA_RFSH_T_LSB) + | SD_SA_PGEHLDE_SET + | SD_SA_CLKSTOP_SET + | SD_SA_POWSAVE_SET + | 0x3214; + + *REG32(SD_SB) = + SD_SB_REORDER_SET + | (T->banklow << SD_SB_BANKLOW_LSB) + | SD_SB_EIGHTBANK_SET + | (T->rowbits << SD_SB_ROWBITS_LSB) + | (T->colbits << SD_SB_COLBITS_LSB); + + logf("SDRAM Addressing Mode: Bank=%d Row=%d Col=%d SB=0x%X\n", T->banklow, T->rowbits, T->colbits, *REG32(SD_SB)); + + *REG32(SD_SC) = + (T->tRFCab << SD_SC_T_RFC_LSB) + | (T->tRRD << SD_SC_T_RRD_LSB) + | (T->tWR << SD_SC_T_WR_LSB) + | (T->tWTR << SD_SC_T_WTR_LSB) + | (3 << SD_SC_WL_LSB); + + *REG32(SD_SD) = + (T->tRPab << SD_SD_T_RPab_LSB) + | (T->tRC << SD_SD_T_RC_LSB) + | (T->tXP << SD_SD_T_XP_LSB) + | (T->tRASmin << SD_SD_T_RAS_LSB) + | (T->tRPpb << SD_SD_T_RPpb_LSB) + | (T->tRCD << SD_SD_T_RCD_LSB); + + *REG32(SD_SE) = + (1 << SD_SE_RL_EN_LSB) + | (4 << SD_SE_RL_LSB) + | (T->tFAW << SD_SE_T_FAW_LSB) + | (T->tRTP << SD_SE_T_RTP_LSB) + | (T->tXSR << SD_SE_T_XSR_LSB); + + *REG32(SD_PT1) = + (T->tINIT3 << SD_PT1_T_INIT3_LSB) + | (T->tINIT1 << SD_PT1_T_INIT1_LSB); + + *REG32(SD_PT2) = + T->tINIT5 << SD_PT2_T_INIT5_LSB; + + *REG32(SD_MRT) = + 0x3 << SD_MRT_T_MRW_LSB; + + reset_phy_dll(); + + /* wait for address line pll to come back */ + SIP_DEBUG(logf("waiting for address dll to lock ...\n")); + for (;;) if (*REG32(APHY_CSR_GLBL_ADR_DLL_LOCK_STAT) == 3) break; + SIP_DEBUG(logf("address dll locked!\n")); + + /* tell sdc we're done messing with address lines */ + *REG32(APHY_CSR_PHY_BIST_CNTRL_SPR) = 0x0; + + /* woo, turn on sdram! */ + *REG32(SD_CS) = + (((4 << SD_CS_ASHDN_T_LSB) + | SD_CS_STATEN_SET + | SD_CS_EN_SET) + & ~(SD_CS_STOP_SET|SD_CS_STBY_SET)) | SD_CS_RESTRT_SET; +} + +static unsigned int read_mr(unsigned int addr) { + while ((*REG32(SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + *REG32(SD_MR) = addr & 0xFF; + unsigned int mrr; + while (((mrr = *REG32(SD_MR)) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + return mrr; +} + +static unsigned int write_mr(unsigned int addr, unsigned int data, bool wait) { + while ((*REG32(SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + + *REG32(SD_MR) = (addr & 0xFF) | ((data & 0xFF) << 8) | SD_MR_RW_SET; + + if (wait) { + unsigned int mrr; + while (((mrr = *REG32(SD_MR)) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + + if (mrr & SD_MR_TIMEOUT_SET) + panic("MR write timed out (addr=%d data=0x%X)", addr, data); + + return mrr; + } else { + return 0; + } +} + +static void reset_phy(void) { + logf("%s: resetting SDRAM PHY ...\n", __FUNCTION__); + + /* reset PHYC */ + *REG32(SD_PHYC) = SD_PHYC_PHYRST_SET; + udelay(64); + *REG32(SD_PHYC) = 0; + + logf("%s: resetting DPHY CTRL ...\n", __FUNCTION__); + + *REG32(DPHY_CSR_DQ_PHY_MISC_CTRL) = 0x7; + *REG32(DPHY_CSR_DQ_PAD_MISC_CTRL) = 0x0; + *REG32(DPHY_CSR_BOOT_READ_DQS_GATE_CTRL) = 0x11; + + reset_phy_dll(); + + *REG32(APHY_CSR_PHY_BIST_CNTRL_SPR) = 0x0; +} + +static void switch_to_cprman_clock(unsigned int source, unsigned int div) { + *REG32(CM_SDCDIV) = CM_PASSWORD | (div << CM_SDCDIV_DIV_LSB); + *REG32(CM_SDCCTL) = CM_PASSWORD | (*REG32(CM_SDCCTL) & CM_SDCCTL_SRC_CLR) | source; + *REG32(CM_SDCCTL) |= CM_PASSWORD | CM_SDCCTL_ENAB_SET; + + logf("switching sdram to cprman clock (src=%d, div=%d), waiting for busy (0x%X) ...\n", source, div, *REG32(CM_SDCCTL)); + + for (;;) if (*REG32(CM_SDCCTL) & CM_SDCCTL_BUSY_SET) break; + + logf("busy set, switch complete!\n"); +} + +static void init_clkman(void) { + uint32_t ctrl = 0; + + clkman_update_begin(); + *REG32(CM_SDCCTL) = CM_PASSWORD | (ctrl << CM_SDCCTL_CTRL_LSB) | (*REG32(CM_SDCCTL) & CM_SDCCTL_CTRL_CLR); + clkman_update_end(); +} + +#define CALL_INIT_CLKMAN init_clkman(); + + +/***************************************************************************** + * Calibration + *****************************************************************************/ + +static void calibrate_pvt_early(void) { + /* some hw revisions require different slews */ + uint32_t cpuid; + __asm__ ("version %0" : "=r"(cpuid)); + // tests for a cpuid ending in 0x___14_ + bool st = ((cpuid >> 4) & 0xFFF) == 0x14; + uint32_t dq_slew = (st ? 2 : 3); + logf("cpuid 0x%x and dq_slew %d\n", cpuid, dq_slew); + + /* i don't get it, the spec says do not use this register */ + write_mr(0xFF, 0, true); + /* RL = 6 / WL = 3 */ + write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, true); + + *REG32(APHY_CSR_ADDR_PAD_DRV_SLEW_CTRL) = 0x333; + *REG32(DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL) = (dq_slew << 8) | (dq_slew << 4) | 3; + + logf("DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL = 0x%X\n", *REG32(DPHY_CSR_DQ_PAD_DRV_SLEW_CTRL)); + + /* tell sdc we want to calibrate */ + *REG32(APHY_CSR_PHY_BIST_CNTRL_SPR) = BIST_pvt; + + /* pvt compensation */ + *REG32(APHY_CSR_ADDR_PVT_COMP_CTRL) = PVT_calibrate_request; + logf("waiting for address PVT calibration ...\n"); + for (;;) if (*REG32(APHY_CSR_ADDR_PVT_COMP_STATUS) & 2) break; + + *REG32(DPHY_CSR_DQ_PVT_COMP_CTRL) = PVT_calibrate_request; + logf("waiting for data PVT calibration ...\n"); + for (;;) if (*REG32(DPHY_CSR_DQ_PVT_COMP_STATUS) & 2) break; + + /* tell sdc we're done calibrating */ + *REG32(APHY_CSR_PHY_BIST_CNTRL_SPR) = 0x0; + + /* send calibration command */ + uint32_t old_mrt = *REG32(SD_MRT); + *REG32(SD_MRT) = 20; + logf("waiting for SDRAM calibration command ...\n"); + *REG32(SD_MR) = LPDDR2_MR_CALIBRATION | (0xFF << 8) | SD_MR_RW_SET | SD_MR_HI_Z_SET; + while ((*REG32(SD_MR) & SD_MR_DONE_SET) != SD_MR_DONE_SET) {} + *REG32(SD_MRT) = old_mrt; + + write_mr(LPDDR2_MR_IO_CONFIG, st ? 3 : 2, false); +} + + +/***************************************************************************** + * Late init + *****************************************************************************/ + +static void init_late(void) { +} + +/***************************************************************************** + * Self-test + *****************************************************************************/ + +#define RT_BASE 0xC0000000 + +#define RT_PAT0 0xAAAAAAAA +#define RT_PAT1 0xFF00AA00 +#define RT_PAT2 0x99999999 + +#define RT_ASSERT(i_, expected) \ + if (ram[(i_)] != expected) { \ + logf("ERROR: At 0x%p, was expecting 0x%X from read, got 0x%X instead!\n", \ + &ram[(i_)], \ + expected, \ + ram[(i_)]); \ + panic("SDRAM self test failed!"); \ + } + +// tests a 16kb chunk of ram, starting at addr +static void selftest_at(uint32_t addr) { + logf("Testing region at 0x%X ...\n", addr); + + // do all acceess via the uncached alias, otherwise it would be an L2 cache hit + volatile uint32_t* ram = (volatile uint32_t*)(addr | RT_BASE); + + for (int i = 0; i < 0x1000; i += 4) { + ram[i] = RT_PAT0; + ram[i + 1] = RT_PAT1; + ram[i + 2] = RT_PAT2; + ram[i + 3] = RT_PAT0; + } + + for (int i = 0; i < 0x1000; i += 4) { + RT_ASSERT(i, RT_PAT0); + RT_ASSERT(i + 1, RT_PAT1); + RT_ASSERT(i + 2, RT_PAT2); + RT_ASSERT(i + 3, RT_PAT0); + } +} + +static void selftest(void) { + logf("Starting self test ...\n"); + + switch (g_RAMSize) { + case kRamSize1GB: + selftest_at(0x3FF00000); // 1023mb + selftest_at(0x2FF00000); // 767mb + case kRamSize512MB: + selftest_at(0x1FF00000); // 511mb + case kRamSize256MB: + selftest_at(0xFF00000); // 255mb + default: + selftest_at(0x0); + } + + logf("Self test successful!\n"); +} + +#undef RT_ASSERT + +void sdram_init() { + uint32_t vendor_id, bc; + + logf("(0) SD_CS = 0x%X\n", *REG32(SD_CS)); + + *REG32(PM_SMPS) = PM_PASSWORD | 0x1; + *REG32(A2W_SMPS_LDO1) = A2W_PASSWORD | 0x40000; + *REG32(A2W_SMPS_LDO0) = A2W_PASSWORD | 0x0; + + *REG32(A2W_XOSC_CTRL) |= A2W_PASSWORD | A2W_XOSC_CTRL_DDREN_SET; + + /* + * STEP 1: + * configure the low-frequency PLL and enable SDC and perform + * the calibration sequence. + */ + + switch_to_cprman_clock(CM_SRC_OSC, 1); + + CALL_INIT_CLKMAN; + + reset_phy(); + + /* magic values */ + *REG32(SD_SA) = 0x006E3395; + *REG32(SD_SB) = 0x0F9; + *REG32(SD_SC) = 0x6000431; + *REG32(SD_SD) = 0x10000011; + *REG32(SD_SE) = 0x10106000; + *REG32(SD_PT1) = 0x0AF002; + *REG32(SD_PT2) = 0x8C; + *REG32(SD_MRT) = 0x3; + *REG32(SD_CS) = 0x200042; + + /* wait for SDRAM controller */ + logf("waiting for SDUP (%X) ...\n", *REG32(SD_CS)); + for (;;) if (*REG32(SD_CS) & SD_CS_SDUP_SET) break; + logf("SDRAM controller has arrived! (%X)\n", *REG32(SD_CS)); + + /* RL = 6 / WL = 3 */ + write_mr(LPDDR2_MR_DEVICE_FEATURE_2, 4, false); + calibrate_pvt_early(); + + /* identify installed memory */ + vendor_id = read_mr(LPDDR2_MR_MANUFACTURER_ID); + if (!MR_REQUEST_SUCCESS(vendor_id)) { + panic("vendor id memory register read timed out"); + } + vendor_id = MR_GET_RDATA(vendor_id); + + bc = read_mr(LPDDR2_MR_METRICS); + if (!MR_REQUEST_SUCCESS(bc)) { + panic("basic configuration memory register read timed out"); + } + bc = MR_GET_RDATA(bc); + + g_RAMSize = lpddr2_size(bc); + + logf("SDRAM Type: %s %s LPDDR2 (BC=0x%X)\n", + lpddr2_manufacturer_name(vendor_id), + size_to_string[g_RAMSize], + bc); + + if (g_RAMSize == kRamSizeUnknown) + panic("unknown ram size (MR8 response was 0x%X)", bc); + + /* + * STEP 2: + * after calibration, enable high-freq SDRAM PLL. because we're + * running from cache, we can freely mess with SDRAM clock without + * any issues, removing the need to copy the SDRAM late init stuff + * to bootrom ram. if later code that's running from SDRAM wants to + * mess with SDRAM clock it would need to do that. + */ + + if (g_RAMSize == kRamSize1GB) { + g_InitSdramParameters.colbits = 3; + g_InitSdramParameters.rowbits = 3; + g_InitSdramParameters.banklow = 3; + } else if (g_RAMSize == kRamSize512MB) { + g_InitSdramParameters.colbits = 2; + } + + reset_with_timing(&g_InitSdramParameters); + init_late(); + selftest(); +} diff --git a/platform/bcm28xx/rules.mk b/platform/bcm28xx/rules.mk index 8f29103603..3beb13ba0d 100644 --- a/platform/bcm28xx/rules.mk +++ b/platform/bcm28xx/rules.mk @@ -3,69 +3,103 @@ LOCAL_DIR := $(GET_LOCAL_DIR) MODULE := $(LOCAL_DIR) WITH_SMP := 1 +#SMP_MAX_CPUS ?= 1 #LK_HEAP_IMPLEMENTATION ?= dlmalloc - -MODULE_DEPS := \ - dev/timer/arm_generic \ - lib/cbuf +MODULE_DEPS += platform/bcm28xx/power + +ifeq ($(ARCH),vpu) + MODULE_DEPS += platform/bcm28xx/pll + ifeq ($(BOOTCODE),1) + MEMBASE := 0x80000000 # in the 8 alias + MEMSIZE := 0x20000 # 128kb + LINKER_SCRIPT += $(LOCAL_DIR)/bootcode.ld + else + MEMBASE := 0xc0000000 + MEMSIZE ?= 0x01400000 # 20MB + LINKER_SCRIPT += $(LOCAL_DIR)/start.ld + endif + GLOBAL_DEFINES += SMP_MAX_CPUS=1 +else # it must be arm32 or arm64 + ifeq ($(HAVE_ARM_TIMER),1) + MODULE_DEPS += dev/timer/arm_generic + GLOBAL_DEFINES += HAVE_ARM_TIMER=1 + else + MODULE_DEPS += dev/timer/vc4 + GLOBAL_DEFINES += VC4_TIMER_CHANNEL=1 + endif + MEMBASE := 0x00000000 + MODULE_SRCS += \ + $(LOCAL_DIR)/mailbox.c \ + $(LOCAL_DIR)/intc.c \ + + LINKER_SCRIPT += $(BUILDDIR)/system-onesegment.ld + GLOBAL_DEFINES += \ + ARM_ARCH_WAIT_FOR_SECONDARIES=1 +endif -#lib/bio \ - lib/cbuf \ - lib/minip \ +# lib/minip \ dev/interrupt/arm_gic \ dev/timer/arm_cortex_a9 MODULE_SRCS += \ $(LOCAL_DIR)/gpio.c \ - $(LOCAL_DIR)/intc.c \ $(LOCAL_DIR)/platform.c \ - $(LOCAL_DIR)/mailbox.c \ + $(LOCAL_DIR)/udelay.c \ + $(LOCAL_DIR)/print_timestamp.c \ + #$(LOCAL_DIR)/i2c.c \ + + +ifeq ($(TARGET),rpi1) + KERNEL_BASE = 0x00000000 + MMIO_BASE_VIRT = 0x20000000U + KERNEL_LOAD_OFFSET := 0x00000000 + MEMSIZE ?= 0x10000000 # 256MB + WITH_SMP = 0 + GLOBAL_DEFINES += MMIO_BASE_VIRT=$(MMIO_BASE_VIRT) TARGET_HAS_DEBUG_LED=1 + MODULE_SRCS += $(LOCAL_DIR)/uart.c +else ifeq ($(TARGET),rpi2) + # put our kernel at 0x80000000 + KERNEL_BASE = 0x80000000 + MMIO_BASE_VIRT = 0xe0000000U + KERNEL_LOAD_OFFSET := 0x00008000 + MEMSIZE ?= 0x10000000 # 256MB + SMP_CPU_ID_BITS := 8 + GLOBAL_DEFINES += MMIO_BASE_VIRT=$(MMIO_BASE_VIRT) + + MODULE_SRCS += $(LOCAL_DIR)/uart.c +else ifeq ($(TARGET),rpi3) + KERNEL_LOAD_OFFSET := 0x00080000 + MEMSIZE ?= 0x40000000 # 1GB + GLOBAL_DEFINES += \ + MMU_WITH_TRAMPOLINE=1 -MEMBASE := 0x00000000 + MODULE_SRCS += $(LOCAL_DIR)/miniuart.c -GLOBAL_DEFINES += \ - ARM_ARCH_WAIT_FOR_SECONDARIES=1 - -LINKER_SCRIPT += \ - $(BUILDDIR)/system-onesegment.ld - -ifeq ($(TARGET),rpi2) -ARCH := arm -ARM_CPU := cortex-a7 -# put our kernel at 0x80000000 -KERNEL_BASE = 0x80000000 -KERNEL_LOAD_OFFSET := 0x00008000 -MEMSIZE ?= 0x10000000 # 256MB -SMP_CPU_ID_BITS := 8 -GLOBAL_DEFINES += \ - BCM2836=1 + MODULE_DEPS += \ + app/shell \ + app/tests \ + lib/fdt +else ifeq ($(TARGET),rpi3-vpu) + GLOBAL_DEFINES += \ -MODULE_SRCS += \ - $(LOCAL_DIR)/uart.c + MODULE_SRCS += \ + $(LOCAL_DIR)/uart.c \ -else ifeq ($(TARGET),rpi3) -ARCH := arm64 -ARM_CPU := cortex-a53 + MODULES += platform/bcm28xx/sdhost + +else ifeq ($(TARGET),rpi4-vpu) + GLOBAL_DEFINES += RPI4=1 -KERNEL_LOAD_OFFSET := 0x00080000 -MEMSIZE ?= 0x40000000 # 1GB + MODULE_SRCS += \ + $(LOCAL_DIR)/uart.c \ + $(LOCAL_DIR)/genet.c \ + +endif GLOBAL_DEFINES += \ MEMBASE=$(MEMBASE) \ MEMSIZE=$(MEMSIZE) \ - MMU_WITH_TRAMPOLINE=1 \ - BCM2837=1 - -MODULE_SRCS += \ - $(LOCAL_DIR)/miniuart.c - -MODULE_DEPS += \ - app/shell \ - app/tests \ - lib/fdt - -endif include make/module.mk diff --git a/platform/bcm28xx/sdhost/block_device.hpp b/platform/bcm28xx/sdhost/block_device.hpp new file mode 100644 index 0000000000..abfd7ee396 --- /dev/null +++ b/platform/bcm28xx/sdhost/block_device.hpp @@ -0,0 +1,38 @@ +/*============================================================================= +Copyright (C) 2016-2017 Authors of rpi-open-firmware +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +Block device. + +=============================================================================*/ + +#include + +struct BlockDevice : bdev_t { + unsigned int block_size; + + template + inline bool real_read_block(bnum_t sector, T* dest_buffer) { + return real_read_block(sector, reinterpret_cast(dest_buffer)); + } + + inline unsigned int get_block_size() { + return block_size; + } + + bool real_read_block(bnum_t sector, uint32_t* buf); + + /* called to stop the block device */ + void stop() {} +}; diff --git a/platform/bcm28xx/sdhost/rules.mk b/platform/bcm28xx/sdhost/rules.mk new file mode 100644 index 0000000000..2e796422d5 --- /dev/null +++ b/platform/bcm28xx/sdhost/rules.mk @@ -0,0 +1,9 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += $(LOCAL_DIR)/sdhost_impl.cpp + +MODULES += lib/bio + +include make/module.mk diff --git a/platform/bcm28xx/sdhost/sd_proto.hpp b/platform/bcm28xx/sdhost/sd_proto.hpp new file mode 100644 index 0000000000..ac43cef5c8 --- /dev/null +++ b/platform/bcm28xx/sdhost/sd_proto.hpp @@ -0,0 +1,370 @@ +/* $NetBSD: sdmmcreg.h,v 1.21 2015/10/29 22:37:15 jmcneill Exp $ */ +/* $OpenBSD: sdmmcreg.h,v 1.4 2009/01/09 10:55:22 jsg Exp $ */ + +/* + * Copyright (c) 2006 Uwe Stuehler + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include + +#pragma once + +#include + +/* MMC commands */ /* response type */ +#define MMC_GO_IDLE_STATE 0 /* R0 */ +#define MMC_SEND_OP_COND 1 /* R3 */ +#define MMC_ALL_SEND_CID 2 /* R2 */ +#define MMC_SET_RELATIVE_ADDR 3 /* R1 */ +#define MMC_SWITCH 6 /* R1b */ +#define MMC_SELECT_CARD 7 /* R1 */ +#define MMC_SEND_EXT_CSD 8 /* R1 */ +#define MMC_SEND_CSD 9 /* R2 */ +#define MMC_SEND_CID 10 /* R2 */ +#define MMC_STOP_TRANSMISSION 12 /* R1b */ +#define MMC_SEND_STATUS 13 /* R1 */ +#define MMC_INACTIVE_STATE 15 /* R0 */ +#define MMC_SET_BLOCKLEN 16 /* R1 */ +#define MMC_READ_BLOCK_SINGLE 17 /* R1 */ +#define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */ +#define MMC_SEND_TUNING_BLOCK 19 /* R1 */ +#define MMC_SEND_TUNING_BLOCK_HS200 21 /* R1 */ +#define MMC_SET_BLOCK_COUNT 23 /* R1 */ +#define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */ +#define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */ +#define MMC_PROGRAM_CSD 27 /* R1 */ +#define MMC_SET_WRITE_PROT 28 /* R1b */ +#define MMC_SET_CLR_WRITE_PROT 29 /* R1b */ +#define MMC_SET_SEND_WRITE_PROT 30 /* R1 */ +#define MMC_TAG_SECTOR_START 32 /* R1 */ +#define MMC_TAG_SECTOR_END 33 /* R1 */ +#define MMC_UNTAG_SECTOR 34 /* R1 */ +#define MMC_TAG_ERASE_GROUP_START 35 /* R1 */ +#define MMC_TAG_ERASE_GROUP_END 36 /* R1 */ +#define MMC_UNTAG_ERASE_GROUP 37 /* R1 */ +#define MMC_ERASE 38 /* R1b */ +#define MMC_LOCK_UNLOCK 42 /* R1b */ +#define MMC_APP_CMD 55 /* R1 */ +#define MMC_READ_OCR 58 /* R3 */ + +/* SD commands */ /* response type */ +#define SD_SEND_RELATIVE_ADDR 3 /* R6 */ +#define SD_SEND_SWITCH_FUNC 6 /* R1 */ +#define SD_SEND_IF_COND 8 /* R7 */ +#define SD_VOLTAGE_SWITCH 11 /* R1 */ + +/* SD application commands */ /* response type */ +#define SD_APP_SET_BUS_WIDTH 6 /* R1 */ +#define SD_APP_SD_STATUS 13 /* R1 */ +#define SD_APP_OP_COND 41 /* R3 */ +#define SD_APP_SEND_SCR 51 /* R1 */ + +/* OCR bits */ +#define MMC_OCR_MEM_READY (1U<<31)/* memory power-up status bit */ +#define MMC_OCR_HCS (1<<30) /* SD only */ +#define MMC_OCR_ACCESS_MODE_MASK (3<<29) /* MMC only */ +#define MMC_OCR_ACCESS_MODE_BYTE (0<<29) /* MMC only */ +#define MMC_OCR_ACCESS_MODE_SECTOR (2<<29) /* MMC only */ +#define MMC_OCR_S18A (1<<24) +#define MMC_OCR_3_5V_3_6V (1<<23) +#define MMC_OCR_3_4V_3_5V (1<<22) +#define MMC_OCR_3_3V_3_4V (1<<21) +#define MMC_OCR_3_2V_3_3V (1<<20) +#define MMC_OCR_3_1V_3_2V (1<<19) +#define MMC_OCR_3_0V_3_1V (1<<18) +#define MMC_OCR_2_9V_3_0V (1<<17) +#define MMC_OCR_2_8V_2_9V (1<<16) +#define MMC_OCR_2_7V_2_8V (1<<15) +#define MMC_OCR_2_6V_2_7V (1<<14) +#define MMC_OCR_2_5V_2_6V (1<<13) +#define MMC_OCR_2_4V_2_5V (1<<12) +#define MMC_OCR_2_3V_2_4V (1<<11) +#define MMC_OCR_2_2V_2_3V (1<<10) +#define MMC_OCR_2_1V_2_2V (1<<9) +#define MMC_OCR_2_0V_2_1V (1<<8) +#define MMC_OCR_1_9V_2_0V (1<<7) +#define MMC_OCR_1_8V_1_9V (1<<6) +#define MMC_OCR_1_7V_1_8V (1<<5) +#define MMC_OCR_1_6V_1_7V (1<<4) + +/* R1 response type bits */ +#define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */ +#define MMC_R1_SWITCH_ERROR (1<<7) /* switch command failed */ +#define MMC_R1_APP_CMD (1<<5) /* app. commands supported */ + +/* 48-bit response decoding (32 bits w/o CRC) */ +#define MMC_R1(resp) ((resp)[0]) +#define MMC_R3(resp) ((resp)[0]) +#define SD_R6(resp) ((resp)[0]) +#define MMC_R7(resp) ((resp)[0]) +#define MMC_SPI_R1(resp) ((resp)[0]) +#define MMC_SPI_R7(resp) ((resp)[1]) + +/* RCA argument and response */ +#define MMC_ARG_RCA(rca) ((rca) << 16) +#define SD_R6_RCA(resp) (SD_R6((resp)) >> 16) + +/* bus width argument */ +#define SD_ARG_BUS_WIDTH_1 0 +#define SD_ARG_BUS_WIDTH_4 2 + +/* EXT_CSD fields */ +#define EXT_CSD_BUS_WIDTH 183 /* WO */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_STRUCTURE 194 /* RO */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_SEC_COUNT 212 /* RO */ + +/* EXT_CSD field definitions */ +#define EXT_CSD_CMD_SET_NORMAL (1U << 0) +#define EXT_CSD_CMD_SET_SECURE (1U << 1) +#define EXT_CSD_CMD_SET_CPSECURE (1U << 2) + +/* EXT_CSD_BUS_WIDTH */ +#define EXT_CSD_BUS_WIDTH_1 0 /* 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* 8 bit mode */ + +/* EXT_CSD_STRUCTURE */ +#define EXT_CSD_STRUCTURE_VER_1_0 0 /* CSD Version No.1.0 */ +#define EXT_CSD_STRUCTURE_VER_1_1 1 /* CSD Version No.1.1 */ +#define EXT_CSD_STRUCTURE_VER_1_2 2 /* Version 4.1-4.2-4.3 */ + +/* EXT_CSD_CARD_TYPE */ +#define EXT_CSD_CARD_TYPE_F_26M (1 << 0) +#define EXT_CSD_CARD_TYPE_F_52M (1 << 1) +#define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) +#define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) +#define EXT_CSD_CARD_TYPE_F_HS200_1_8V (1 << 4) +#define EXT_CSD_CARD_TYPE_F_HS200_1_2V (1 << 5) +#define EXT_CSD_CARD_TYPE_F_HS400_1_8V (1 << 6) +#define EXT_CSD_CARD_TYPE_F_HS400_1_2V (1 << 7) +#define EXT_CSD_CARD_TYPE_26M 0x01 +#define EXT_CSD_CARD_TYPE_52M 0x03 +#define EXT_CSD_CARD_TYPE_52M_V18 0x07 +#define EXT_CSD_CARD_TYPE_52M_V12 0x0b +#define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f + +/* MMC_SWITCH access mode */ +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ + +/* SPI mode reports R1/R2(SEND_STATUS) status. */ +#define R1_SPI_IDLE (1 << 0) +#define R1_SPI_ERASE_RESET (1 << 1) +#define R1_SPI_ILLEGAL_COMMAND (1 << 2) +#define R1_SPI_COM_CRC (1 << 3) +#define R1_SPI_ERASE_SEQ (1 << 4) +#define R1_SPI_ADDRESS (1 << 5) +#define R1_SPI_PARAMETER (1 << 6) +/* R1 bit 7 is always zero */ +#define R2_SPI_CARD_LOCKED (1 << 8) +#define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1 << 10) +#define R2_SPI_CC_ERROR (1 << 11) +#define R2_SPI_CARD_ECC_ERROR (1 << 12) +#define R2_SPI_WP_VIOLATION (1 << 13) +#define R2_SPI_ERASE_PARAM (1 << 14) +#define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE + +/* MMC R2 response (CSD) */ +#define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) +#define MMC_CSD_CSDVER_1_0 0 +#define MMC_CSD_CSDVER_1_1 1 +#define MMC_CSD_CSDVER_1_2 2 /* MMC 4.1 - 4.2 - 4.3 */ +#define MMC_CSD_CSDVER_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ +#define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) +#define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */ +#define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */ +#define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */ +#define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */ +#define MMC_CSD_MMCVER_4_0 4 /* MMC 4.1 - 4.2 - 4.3 */ +#define MMC_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) +#define MMC_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 115, 4) +#define MMC_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 112, 3) +#define MMC_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) +#define MMC_CSD_TRAN_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) +#define MMC_CSD_TRAN_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) +#define MMC_CSD_TRAN_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) +#define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) +#define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) +#define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \ + (MMC_CSD_C_SIZE_MULT((resp))+2)) +#define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) +#define MMC_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) +#define MMC_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) + +/* MMC v1 R2 response (CID) */ +#define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24) +#define MMC_CID_PNM_V1_CPY(resp, pnm) \ + do { \ + (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ + (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ + (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ + (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ + (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ + (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ + (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \ + (pnm)[7] = '\0'; \ + } while (/*CONSTCOND*/0) +#define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8) +#define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24) +#define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8) + +/* MMC v2 R2 response (CID) */ +#define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8) +#define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16) +#define MMC_CID_PNM_V2_CPY(resp, pnm) \ + do { \ + (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ + (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ + (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ + (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ + (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ + (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \ + (pnm)[6] = '\0'; \ + } while (/*CONSTCOND*/0) +#define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32) + +/* SD R2 response (CSD) */ +#define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2) +#define SD_CSD_CSDVER_1_0 0 +#define SD_CSD_CSDVER_2_0 1 +#define SD_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4) +#define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8) +#define SD_CSD_TAAC_EXP(resp) MMC_RSP_BITS((resp), 115, 4) +#define SD_CSD_TAAC_MANT(resp) MMC_RSP_BITS((resp), 112, 3) +#define SD_CSD_TAAC_1_5_MSEC 0x26 +#define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8) +#define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8) +#define SD_CSD_SPEED_MANT(resp) MMC_RSP_BITS((resp), 99, 4) +#define SD_CSD_SPEED_EXP(resp) MMC_RSP_BITS((resp), 96, 3) +#define SD_CSD_SPEED_25_MHZ 0x32 +#define SD_CSD_SPEED_50_MHZ 0x5a +#define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12) +#define SD_CSD_CCC_BASIC (1 << 0) /* basic */ +#define SD_CSD_CCC_BR (1 << 2) /* block read */ +#define SD_CSD_CCC_BW (1 << 4) /* block write */ +#define SD_CSD_CCC_ERACE (1 << 5) /* erase */ +#define SD_CSD_CCC_WP (1 << 6) /* write protection */ +#define SD_CSD_CCC_LC (1 << 7) /* lock card */ +#define SD_CSD_CCC_AS (1 << 8) /*application specific*/ +#define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */ +#define SD_CSD_CCC_SWITCH (1 << 10) /* switch */ +#define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4) +#define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1) +#define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1) +#define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1) +#define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1) +#define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12) +#define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \ + (SD_CSD_C_SIZE_MULT((resp))+2)) +#define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3) +#define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3) +#define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3) +#define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3) +#define SD_CSD_VDD_RW_CURR_100mA 0x7 +#define SD_CSD_VDD_RW_CURR_80mA 0x6 +#define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22) +#define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10) +#define SD_CSD_V2_BL_LEN 0x9 /* 512 */ +#define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3) +#define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1) +#define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */ +#define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */ +#define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1) +#define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3) +#define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4) +#define SD_CSD_RW_BL_LEN_2G 0xa +#define SD_CSD_RW_BL_LEN_1G 0x9 +#define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1) +#define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1) +#define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1) +#define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1) +#define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1) +#define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2) + +/* SD R2 response (CID) */ +#define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8) +#define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16) +#define SD_CID_PNM_CPY(resp, pnm) \ + do { \ + (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \ + (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \ + (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \ + (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \ + (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \ + (pnm)[5] = '\0'; \ + } while (/*CONSTCOND*/0) +#define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8) +#define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32) +#define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12) + +/* SCR (SD Configuration Register) */ +#define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4) +#define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */ +#define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4) +#define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */ +#define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */ +#define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */ +#define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1) +#define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3) +#define SCR_SD_SECURITY_NONE 0 /* no security */ +#define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */ +#define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */ +#define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4) +#define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */ +#define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */ +#define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1) +#define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4) +#define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 9) +#define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1) +#define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1) +#define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32) + +#define MMC_RSP_BITS(resp, start, len) __bitfield((resp), (start), (len)) +static inline int +__bitfield(uint32_t *src, int start, int len) { + uint8_t *sp; + uint32_t dst, mask; + int shift, bs, bc; + + if (start < 0 || len < 0 || len > 32) + return 0; + + dst = 0; + mask = len % 32 ? UINT_MAX >> (32 - (len % 32)) : UINT_MAX; + shift = 0; + + while (len > 0) { + sp = (uint8_t *)src + start / 8; + bs = start % 8; + bc = 8 - bs; + if (bc > len) + bc = len; + dst |= (*sp >> bs) << shift; + shift += bc; + start += bc; + len -= bc; + } + + dst &= mask; + return (int)dst; +} diff --git a/platform/bcm28xx/sdhost/sdhost_impl.cpp b/platform/bcm28xx/sdhost/sdhost_impl.cpp new file mode 100644 index 0000000000..fba34de14f --- /dev/null +++ b/platform/bcm28xx/sdhost/sdhost_impl.cpp @@ -0,0 +1,626 @@ +/*============================================================================= +Copyright (C) 2016-2017 Authors of rpi-open-firmware +All rights reserved. + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +FILE DESCRIPTION +SDHOST driver. This used to be known as ALTMMC. + +=============================================================================*/ + +#include "sd_proto.hpp" +#include "block_device.hpp" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern "C" { + #include +} + +#define SDEDM_WRITE_THRESHOLD_SHIFT 9 +#define SDEDM_READ_THRESHOLD_SHIFT 14 +#define SDEDM_THRESHOLD_MASK 0x1f + +#define SAFE_READ_THRESHOLD 4 +#define SAFE_WRITE_THRESHOLD 4 + +#define VOLTAGE_SUPPLY_RANGE 0x100 +#define CHECK_PATTERN 0x55 + +#define SDHSTS_BUSY_IRPT 0x400 +#define SDHSTS_BLOCK_IRPT 0x200 +#define SDHSTS_SDIO_IRPT 0x100 +#define SDHSTS_REW_TIME_OUT 0x80 +#define SDHSTS_CMD_TIME_OUT 0x40 +#define SDHSTS_CRC16_ERROR 0x20 +#define SDHSTS_CRC7_ERROR 0x10 +#define SDHSTS_FIFO_ERROR 0x08 + +#define SDEDM_FSM_MASK 0xf +#define SDEDM_FSM_IDENTMODE 0x0 +#define SDEDM_FSM_DATAMODE 0x1 +#define SDEDM_FSM_READDATA 0x2 +#define SDEDM_FSM_WRITEDATA 0x3 +#define SDEDM_FSM_READWAIT 0x4 +#define SDEDM_FSM_READCRC 0x5 +#define SDEDM_FSM_WRITECRC 0x6 +#define SDEDM_FSM_WRITEWAIT1 0x7 +#define SDEDM_FSM_POWERDOWN 0x8 +#define SDEDM_FSM_POWERUP 0x9 +#define SDEDM_FSM_WRITESTART1 0xa +#define SDEDM_FSM_WRITESTART2 0xb +#define SDEDM_FSM_GENPULSES 0xc +#define SDEDM_FSM_WRITEWAIT2 0xd +#define SDEDM_FSM_STARTPOWDOWN 0xf + +#define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR|SDHSTS_CRC16_ERROR|SDHSTS_REW_TIME_OUT|SDHSTS_FIFO_ERROR) +#define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT|SDHSTS_TRANSFER_ERROR_MASK) + +#define logf(fmt, ...) { print_timestamp(); printf("[EMMC:%s]: " fmt, __FUNCTION__, ##__VA_ARGS__); } +#define mfence() __sync_synchronize() + +#define kIdentSafeClockRate 0x148 + +static int cmd_sdhost_init(int argc, const cmd_args *argv); + +STATIC_COMMAND_START +STATIC_COMMAND("sdhost_init", "initialize the sdhost driver", &cmd_sdhost_init) +STATIC_COMMAND_END(sdhost); + +struct BCM2708SDHost : BlockDevice { + bool is_sdhc; + bool is_high_capacity; + bool card_ready; + + uint32_t ocr; + uint32_t rca; + + uint32_t cid[4]; + uint32_t csd[4]; + + uint64_t capacity_bytes; + + uint32_t r[4]; + + uint32_t current_cmd; + + void set_power(bool on) { + *REG32(SH_VDD) = on ? SH_VDD_POWER_ON_SET : 0x0; + } + + bool wait(uint32_t timeout = 100000) { + uint32_t t = timeout; + + while(*REG32(SH_CMD) & SH_CMD_NEW_FLAG_SET) { + if (t == 0) { + logf("timed out after %dus!\n", timeout) + return false; + } + t--; + udelay(10); + } + + return true; + } + + bool send_raw(uint32_t command, uint32_t arg = 0) { + uint32_t sts; + + wait(); + + sts = *REG32(SH_HSTS); + if (sts & SDHSTS_ERROR_MASK) + *REG32(SH_HSTS) = sts; + + current_cmd = command & SH_CMD_COMMAND_SET; + + *REG32(SH_ARG) = arg; + *REG32(SH_CMD) = command | SH_CMD_NEW_FLAG_SET; + + mfence(); + + return true; + } + + bool send(uint32_t command, uint32_t arg = 0) { + return send_raw(command & SH_CMD_COMMAND_SET, arg); + } + + bool send_136_resp(uint32_t command, uint32_t arg = 0) { + return send_raw((command & SH_CMD_COMMAND_SET) | SH_CMD_LONG_RESPONSE_SET, arg); + } + + bool send_no_resp(uint32_t command, uint32_t arg = 0) { + return send_raw((command & SH_CMD_COMMAND_SET) | SH_CMD_NO_RESPONSE_SET, arg); + } + + void configure_pinmux() { + gpio_config(48, kBCM2708Pinmux_ALT0); + gpio_config(49, kBCM2708Pinmux_ALT0); + gpio_config(50, kBCM2708Pinmux_ALT0); + gpio_config(51, kBCM2708Pinmux_ALT0); + gpio_config(52, kBCM2708Pinmux_ALT0); + gpio_config(53, kBCM2708Pinmux_ALT0); + + struct gpio_pull_batch pullBatch; + GPIO_PULL_CLEAR(pullBatch); + GPIO_PULL_SET(pullBatch, 48, kPullUp); + GPIO_PULL_SET(pullBatch, 49, kPullUp); + GPIO_PULL_SET(pullBatch, 50, kPullUp); + GPIO_PULL_SET(pullBatch, 51, kPullUp); + GPIO_PULL_SET(pullBatch, 52, kPullUp); + GPIO_PULL_SET(pullBatch, 53, kPullUp); + gpio_apply_batch(&pullBatch); + + //logf("pinmux configured for aux0\n"); + } + + void reset() { + logf("resetting controller ...\n"); + set_power(false); + + *REG32(SH_CMD) = 0; + *REG32(SH_ARG) = 0; + *REG32(SH_TOUT) = 0xF00000; + *REG32(SH_CDIV) = 0; + *REG32(SH_HSTS) = 0x7f8; + *REG32(SH_HCFG) = 0; + *REG32(SH_HBCT) = 0; + *REG32(SH_HBLC) = 0; + + uint32_t temp = *REG32(SH_EDM); + + temp &= ~((SDEDM_THRESHOLD_MASK< /dev/null ...\n", block_size, sector); + } +#endif + + /* drain junk from FIFO */ + drain_fifo(); + + /* enter READ mode */ + send_raw(MMC_READ_BLOCK_MULTIPLE | SH_CMD_READ_CMD_SET, sector); + + int i; + uint32_t hsts_err = 0; + + +#ifdef DUMP_READ + if (buf) + printf("----------------------------------------------------\n"); +#endif + + /* drain useful data from FIFO */ + for (i = 0; i < 128; i++) { + /* wait for FIFO */ + if (!wait_for_fifo_data()) { + break; + } + + uint32_t hsts_err = *REG32(SH_HSTS) & SDHSTS_ERROR_MASK; + if (hsts_err) { + logf("ERROR: transfer error on FIFO word %d: 0x%x\n", i, *REG32(SH_HSTS)); + break; + } + + + volatile uint32_t data = *REG32(SH_DATA); + +#ifdef DUMP_READ + printf("%08x ", data); +#endif + if (buf) + *(buf++) = data; + } + + send_raw(MMC_STOP_TRANSMISSION | SH_CMD_BUSY_CMD_SET); + +#ifdef DUMP_READ + printf("\n"); + if (buf) + printf("----------------------------------------------------\n"); +#endif + + if (hsts_err) { + logf("ERROR: Transfer error, status: 0x%x\n", *REG32(SH_HSTS)); + return false; + } + +#ifdef DUMP_READ + if (buf) + logf("Completed read for %d\n", sector); +#endif + return true; + } + + + + bool select_card() { + send(MMC_SELECT_CARD, MMC_ARG_RCA(rca)); + + if (!wait()) + return false; + + return true; + } + + bool init_card() { + char pnm[8]; + uint64_t block_length; + uint32_t clock_div = 0; + + send_no_resp(MMC_GO_IDLE_STATE); + + if (!query_voltage_and_type()) { + //logf("ERROR: Failed to query card voltage!\n"); + return false; + } + + if (!identify_card()) { + //logf("ERROR: Failed to identify card!\n"); + return false; + } + + SD_CID_PNM_CPY(cid, pnm); + + //logf("Detected SD card:\n"); + printf(" Product : %s\n", pnm); + + if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_2_0) { + printf(" CSD : Ver 2.0\n"); + printf(" Capacity: %d\n", SD_CSD_V2_CAPACITY(csd)); + printf(" Size : %d\n", SD_CSD_V2_C_SIZE(csd)); + + block_length = 1 << SD_CSD_V2_BL_LEN; + + /* work out the capacity of the card in bytes */ + capacity_bytes = (SD_CSD_V2_CAPACITY(csd) * block_length); + + clock_div = 5; + } else if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) { + printf(" CSD : Ver 1.0\n"); + printf(" Capacity: %d\n", SD_CSD_CAPACITY(csd)); + printf(" Size : %d\n", SD_CSD_C_SIZE(csd)); + + block_length = 1 << SD_CSD_READ_BL_LEN(csd); + + /* work out the capacity of the card in bytes */ + capacity_bytes = (SD_CSD_CAPACITY(csd) * block_length); + + clock_div = 10; + } else { + printf("ERROR: Unknown CSD version 0x%x!\n", SD_CSD_CSDVER(csd)); + return false; + } + + printf(" BlockLen: 0x%x\n", block_length); + + if (!select_card()) { + //logf("ERROR: Failed to select card!\n"); + return false; + } + + if (SD_CSD_CSDVER(csd) == SD_CSD_CSDVER_1_0) { + /* + * only needed for 1.0 ones, the 2.0 ones have this + * fixed at 512. + */ + //logf("Setting block length to 512 ...\n"); + send(MMC_SET_BLOCKLEN, 512); + if (!wait()) { + logf("ERROR: Failed to set block length!\n"); + return false; + } + } + + block_size = 512; + + logf("Card initialization complete: %s %dMB SD%s Card\n", pnm, (uint32_t)(capacity_bytes >> 20), is_high_capacity ? "HC" : ""); + + /* + * this makes some dangerous assumptions that the all csd2 cards are sdio cards + * and all csd1 cards are sd cards and that mmc cards won't be used. this also assumes + * PLLC.CORE0 is at 250MHz which is probably a safe assumption since we set it. + */ + if (clock_div) { + logf("Identification complete, changing clock to %dMHz for data mode ...\n", 250 / clock_div); + *REG32(SH_CDIV) = clock_div - 2; + } + + return true; + } + + void restart_controller() { + is_sdhc = false; + + logf("hcfg 0x%X, cdiv 0x%X, edm 0x%X, hsts 0x%X\n", + *REG32(SH_HCFG), + *REG32(SH_CDIV), + *REG32(SH_EDM), + *REG32(SH_HSTS)); + + logf("Restarting the eMMC controller ...\n"); + + configure_pinmux(); + reset(); + + *REG32(SH_HCFG) &= ~SH_HCFG_WIDE_EXT_BUS_SET; + *REG32(SH_HCFG) = SH_HCFG_SLOW_CARD_SET | SH_HCFG_WIDE_INT_BUS_SET; + *REG32(SH_CDIV) = kIdentSafeClockRate; + + udelay(300); + mfence(); + + if (init_card()) { + card_ready = true; + + /* + * looks like a silicon bug to me or a quirk of csd2, who knows + */ + for (int i = 0; i < 3; i++) { + if (!real_read_block(0, nullptr)) { + panic("fifo flush cycle %d failed", i); + } + } + } else { + panic("failed to reinitialize the eMMC controller"); + } + } + + void stop() { + if (card_ready) { + logf("flushing fifo ...\n"); + drain_fifo_nowait(); + + logf("asking card to enter idle state ...\n"); + *REG32(SH_CDIV) = kIdentSafeClockRate; + udelay(150); + + send_no_resp(MMC_GO_IDLE_STATE); + udelay(500); + } + + logf("stopping sdhost controller driver ...\n"); + + *REG32(SH_CMD) = 0; + *REG32(SH_ARG) = 0; + *REG32(SH_TOUT) = 0xA00000; + *REG32(SH_CDIV) = 0x1FB; + + logf("powering down controller ...\n"); + *REG32(SH_VDD) = 0; + *REG32(SH_HCFG) = 0; + *REG32(SH_HBCT) = 0x400; + *REG32(SH_HBLC) = 0; + *REG32(SH_HSTS) = 0x7F8; + + logf("resetting state machine ...\n"); + + *REG32(SH_CMD) = 0; + *REG32(SH_ARG) = 0; + } + + BCM2708SDHost() { + restart_controller(); + logf("eMMC driver sucessfully started!\n"); + } +}; + +struct BCM2708SDHost *sdhost = 0; + +static ssize_t sdhost_read_block_wrap(struct bdev *bdev, void *buf, bnum_t block, uint count) { + BCM2708SDHost *dev = reinterpret_cast(bdev); + //printf("sdhost_read_block_wrap(..., 0x%x, %d, %d)\n", buf, block, count); + for (int i=0; i(buf + (sdhost->get_block_size() * i)); + bool ret = dev->real_read_block(block + i, dest); + if (!ret) return -1; + } + return sdhost->get_block_size() * count; +} + +bdev_t *rpi_sdhost_init() { + if (!sdhost) { + sdhost = new BCM2708SDHost; + auto blocksize = sdhost->get_block_size(); + auto blocks = sdhost->capacity_bytes / blocksize; + bio_initialize_bdev(sdhost, "sdhost", blocksize, blocks, 0, NULL, BIO_FLAGS_NONE); + //sdhost->read = sdhost_read_wrap; + sdhost->read_block = sdhost_read_block_wrap; + bio_register_device(sdhost); + } + return sdhost; +} + +static int cmd_sdhost_init(int argc, const cmd_args *argv) { + rpi_sdhost_init(); + return 0; +} diff --git a/platform/bcm28xx/start.ld b/platform/bcm28xx/start.ld new file mode 100644 index 0000000000..a6ba619403 --- /dev/null +++ b/platform/bcm28xx/start.ld @@ -0,0 +1,79 @@ +/* + * based heavily on https://github.com/ptesarik/vc4boot + */ + +OUTPUT_FORMAT("elf32-vc4", "elf32-vc4", "elf32-vc4") +OUTPUT_ARCH(vc4) +ENTRY(_start) +GROUP(-lgcc) + +MEMORY { + /* in the C alias, direct uncached + */ + ram (rwx) : ORIGIN = 0xc0000000 + 20M, LENGTH = 20M +} +SECTIONS { + .text : { + PROVIDE(_start = .); + . = ALIGN(4); + *(.text .stub .text.* .gnu.linkonce.t.*) + *(.gnu.warning) + KEEP (*(.init)) + KEEP (*(.fini)) + KEEP (*(.jcr)) + _etext = .; + } >ram =0 + + .rodata : { + . = ALIGN(4); + _frodata = .; + *(.rodata .rodata.* .gnu.linkonce.r.*) + *(.rodata1) + _erodata = .; + } >ram + + .init_array : { + PROVIDE (__init_array_start = .); + __ctor_list = .; + *(.init_array) + *(.init_array.*) + *(.ctors) + *(.ctors.*) + __init_array_end = .; + __ctor_end = .; + } >ram + + .vectorTable : ALIGN(512) { + *(.data.vectorTable) + } >ram + + .rel : { *(.*.rel*) } + + .data : { + . = ALIGN(4); + _fdata = .; + *(.data .data.* .gnu.linkonce.d.*) + *(.data1) + SORT(CONSTRUCTORS) + *(.sdata .sdata.* .gnu.linkonce.s.*) + _edata = .; + } >ram + + .bss : { + . = ALIGN(4); + _fbss = .; + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + _end = .; + PROVIDE (end = .); + } >ram + + /* First location in stack is highest address in RAM */ + PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4); +} diff --git a/platform/bcm28xx/start4/rules.mk b/platform/bcm28xx/start4/rules.mk new file mode 100644 index 0000000000..4cf0cce181 --- /dev/null +++ b/platform/bcm28xx/start4/rules.mk @@ -0,0 +1,10 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +MODULE := $(LOCAL_DIR) + +MODULE_SRCS += \ + $(LOCAL_DIR)/start4.c + +EXTRA_LINKER_SCRIPTS += $(LOCAL_DIR)/start4.ld + +include make/module.mk diff --git a/platform/bcm28xx/start4/start4.c b/platform/bcm28xx/start4/start4.c new file mode 100644 index 0000000000..e8ce2f18e1 --- /dev/null +++ b/platform/bcm28xx/start4/start4.c @@ -0,0 +1,146 @@ +#include +#include +#include +#include +#include + +uint32_t bootloader_state[4] __attribute__ ((section(".text.bootloader_state"))) = { 0x41545342, 0, 0, 0 }; +// bit 0 declares support for a certain cpuid on the VPU +// bit 1 is pi400 flag? +// pi400 booting over usb-dev requires both bit0 and bit1 +uint32_t firmware_rev[4] __attribute__ ((section(".text.firmware_rev"))) = { 0x3, 0, 0, 0 }; + +typedef struct { + char revision[41]; + char type[8]; + char date[16]; + char time[12]; + uint32_t padding; + uint32_t something; + uint32_t serial; + uint32_t something2; +} bver_state; +// the new tryboot flag may appear in BVER + +typedef struct { + uint32_t macend; // 0 + uint32_t macstart; // 4 + uint8_t mac[6]; // 10 + uint8_t pad[2]; // 12 + uint32_t thing1; // 14 + uint16_t thing2; // 18 + uint8_t pad2[2]; // 20 + char serial_str[12];// 22 + uint8_t myip[4]; // 34 + uint32_t pad3[2]; // 38 + uint8_t tftp_ip[4]; // 40 + char prefix[128]; // 44 +} bstn_state; + +typedef struct { + void *vl805hub_addr; + uint32_t vl805hub_size; + void *vl805mcu_addr; + uint32_t vl805mcu_size; + uint32_t bitfield; // bit1 means vl805 eeprom is present + void *buffer; + uint32_t usb_handle; +} busb_state; + +typedef struct { + uint32_t a; + uint32_t b; + uint32_t c; +} bstm_state; + +static void print_bver(bver_state *bver) { + printf("\trevision: %s, type: %s, %s %s, 0x%x, serial: 0x%x something 0x%x\n", bver->revision, bver->type, bver->date, bver->time, bver->something, bver->serial, bver->something2); +} + +static void print_bstn(bstn_state *bstn) { + printf("\tmac1: %08x%08x\n", bstn->macstart, bstn->macend); + printf("\tmac2: %02x:%02x:%02x:%02x:%02x:%02x\n", bstn->mac[0], bstn->mac[1], bstn->mac[2], bstn->mac[3], bstn->mac[4], bstn->mac[5]); + printf("\tserial1: %s\n", bstn->serial_str); + printf("\tmyip: %d.%d.%d.%d\n", bstn->myip[3], bstn->myip[2], bstn->myip[1], bstn->myip[0]); + printf("\ttftp_server: %d.%d.%d.%d\n", bstn->tftp_ip[3], bstn->tftp_ip[2], bstn->tftp_ip[1], bstn->tftp_ip[0]); + printf("\ttftp_prefix: %s\n", bstn->prefix); +} + +static void print_busb(busb_state *busb) { + printf("\tvl805hub: 0x%x + %d\n", busb->vl805hub_addr, busb->vl805hub_size); + printf("\tvl805mcu: 0x%x + %d\n", busb->vl805mcu_addr, busb->vl805mcu_size); + printf("\tbitfield: 0x%x\n", busb->bitfield); + printf("\tbuffer: 0x%x, handle: 0x%x\n", busb->buffer, busb->usb_handle); +} + +static void print_bstm(bstm_state *bstm) { + printf("\tA: 0x%x, B: 0x%x, C: 0x%x\n", bstm->a, bstm->b, bstm->c); + if (bstm->b == 0) puts("\tSD"); + if (bstm->b == 1) puts("\tNET"); + if (bstm->b == 2) puts("\tUSB-MSD"); + if (bstm->b == 3) puts("\tUSB-DEV"); + if (bstm->b == 4) puts("\tUSB-BCM-MSD"); +} + +static char guard(char c) { + if ((c >= ' ') && (c <= '~')) { + return c; + } else { + return '.'; + } +} + +static void print_word(int i, uint32_t w) { + char a,b,c,d; + a = w & 0xff; + b = (w >> 8) & 0xff; + c = (w >> 16) & 0xff; + d = (w >> 24) & 0xff; + a = guard(a); + b = guard(b); + c = guard(c); + d = guard(d); + printf("%d: 0x%x (%c%c%c%c)\n", i, w, a,b,c,d); +} + +static void start4_print_state(uint level) { + printf("ST_CLO: %d\n", *REG32(ST_CLO)); + printf("bootloader state 0x%x 0x%x 0x%x 0x%x\n", bootloader_state[0], bootloader_state[1], bootloader_state[2], bootloader_state[3]); + uint32_t *state = bootloader_state[1]; + if (state) { + puts("some state exists"); + while (true) { + char a,b,c,d; + a = state[0] & 0xff; + b = (state[0] >> 8) & 0xff; + c = (state[0] >> 16) & 0xff; + d = (state[0] >> 24) & 0xff; + printf("TAG 0x%x(%c%c%c%c), 0x%x 0x%x\n", state[0], a,b,c,d, state[1], state[2]); + switch (state[0]) { + case 0x52455642: // BVER + print_bver(&state[3]); + break; + case 0x4e545342: // BSTN + print_bstn(&state[3]); + break; + case 0x42535542: // BUSB + print_busb(&state[3]); + break; + case 0x4d545342: // BSTM + print_bstm(&state[3]); + break; + default: { + uint32_t size = state[2]; + if (size == 0) size = state[1]; + for (int i=3; i < (size/4); i++) { + print_word(i, state[i]); + } + } + } + if (state[2] == 0) break; + state += (state[2]/4); + } + } +} + +LK_INIT_HOOK(start4, &start4_print_state, LK_INIT_LEVEL_APPS); diff --git a/platform/bcm28xx/start4/start4.ld b/platform/bcm28xx/start4/start4.ld new file mode 100644 index 0000000000..c174f1ee8a --- /dev/null +++ b/platform/bcm28xx/start4/start4.ld @@ -0,0 +1,9 @@ +SECTIONS { + .text.bootloader_state : { + *(.text.bootloader_state) + } + .text.firmware_rev : { + *(.text.firmware_rev) + } +} +INSERT AFTER .text; diff --git a/platform/bcm28xx/uart.c b/platform/bcm28xx/uart.c index 914a529775..5e3202d0e0 100644 --- a/platform/bcm28xx/uart.c +++ b/platform/bcm28xx/uart.c @@ -8,11 +8,15 @@ #include #include #include +#include #include #include #include #include #include +#include +#include +#include /* TODO: extract this into a generic PL011 driver */ @@ -39,6 +43,14 @@ static cbuf_t uart_rx_buf[NUM_UART]; +static int cmd_uart_dump(int argc, const cmd_args *argv); +int uart_putc(int port, char c); +void udelay(uint32_t t); + +STATIC_COMMAND_START +STATIC_COMMAND("dump_uart_state", "print uart state relating to baud", &cmd_uart_dump) +STATIC_COMMAND_END(uart); + static inline uintptr_t uart_to_ptr(unsigned int n) { switch (n) { default: @@ -47,6 +59,13 @@ static inline uintptr_t uart_to_ptr(unsigned int n) { } } +static uint32_t calculate_baud_divisor(uint32_t baud) { + uint32_t uart_freq = get_uart_base_freq(); + if (uart_freq == 0) return 0; + uint32_t divisor = (uart_freq << 6) / baud / 16; + return divisor; +} + static enum handler_return uart_irq(void *arg) { bool resched = false; uint port = (uint)arg; @@ -61,27 +80,60 @@ static enum handler_return uart_irq(void *arg) { /* while fifo is not empty, read chars out of it */ while ((UARTREG(base, UART_TFR) & (1<<4)) == 0) { - char c = UARTREG(base, UART_DR); - cbuf_write_char(rxbuf, c, false); - - resched = true; + uint32_t data = UARTREG(base, UART_DR); + char c = data & 0xff; + if (data & 0x400) { + dprintf(INFO, "UART break detected\n"); + } else if (data & 0x100) { + dprintf(INFO, "UART framing error\n"); + } else { + if (data & 0x800) { + dprintf(INFO, "UART input overflow\n"); + } + cbuf_write_char(rxbuf, c, false); + + resched = true; + } } } return resched ? INT_RESCHEDULE : INT_NO_RESCHEDULE; } +static void uart_flush(int port) { + // waits until tx FIFO has room, but is not flushed fully + uintptr_t base = uart_to_ptr(port); + while (UARTREG(base, UART_TFR) & 0x20); +} + void uart_init(void) { + gpio_config(14, 4); + gpio_config(15, 4); for (size_t i = 0; i < NUM_UART; i++) { + uintptr_t base = uart_to_ptr(i); + // create circular buffer to hold received data cbuf_initialize(&uart_rx_buf[i], RXBUF_SIZE); + DEBUG_ASSERT(uart_rx_buf[i].event.magic == EVENT_MAGIC); // assumes interrupts are contiguous register_int_handler(INTERRUPT_VC_UART + i, &uart_irq, (void *)i); + uint32_t divisor = calculate_baud_divisor(115200); + + uart_flush(i); + + UARTREG(base, UART_CR) = 0; // shutdown the entire uart // clear all irqs UARTREG(uart_to_ptr(i), UART_ICR) = 0x3ff; + UARTREG(base, UART_LCRH) = 0x70; // fifo enable, 8bit mode + + if (divisor > 0) { + UARTREG(base, UART_IBRD) = (divisor >> 6) & 0xffff; + UARTREG(base, UART_FBRD) = divisor & 0x3f; + } + // set fifo trigger level UARTREG(uart_to_ptr(i), UART_IFLS) = 0; // 1/8 rxfifo, 1/8 txfifo @@ -89,7 +141,7 @@ void uart_init(void) { UARTREG(uart_to_ptr(i), UART_IMSC) = (1<<6)|(1<<4); // rtim, rxim // enable receive - UARTREG(uart_to_ptr(i), UART_CR) |= (1<<9); // rxen + UARTREG(uart_to_ptr(i), UART_CR) |= (1<<9) | (1<<8) | (1<<0); // rxen, tx_enable, uarten // enable interrupt unmask_interrupt(INTERRUPT_VC_UART + i); @@ -97,9 +149,30 @@ void uart_init(void) { } void uart_init_early(void) { + if (*REG32(CM_UARTDIV) == 0) { + //puts("fixing divisor"); + //return; + // CM_UARTDIV can range from 0 to 1023 with a fractional resolution of 1/4096th + // on the rpi1-3, this sets the freq to 19.2 / (0x3900 / 0x1000) == ~5.3mhz + // TODO, have a better default for other models? + *REG32(CM_UARTDIV) = CM_PASSWORD | 0x3900; + *REG32(CM_UARTCTL) = CM_PASSWORD | CM_SRC_OSC | CM_UARTCTL_FRAC_SET | CM_UARTCTL_ENAB_SET; + } + udelay(100); + for (size_t i = 0; i < NUM_UART; i++) { - UARTREG(uart_to_ptr(i), UART_CR) = (1<<8)|(1<<0); // tx_enable, uarten + uintptr_t base = uart_to_ptr(i); + uint32_t divisor = calculate_baud_divisor(115200); + UARTREG(base, UART_CR) = 0; // shutdown the entire uart + UARTREG(base, UART_LCRH) = 0x70; // fifo enable, 8bit mode + if (divisor > 0) { + UARTREG(base, UART_IBRD) = (divisor >> 6) & 0xffff; + UARTREG(base, UART_FBRD) = divisor & 0x3f; + } + UARTREG(base, UART_CR) = (1<<8)|(1<<0); // tx_enable, uarten } + gpio_config(14, 4); + printf("uart early init done\n"); } int uart_putc(int port, char c) { @@ -117,6 +190,7 @@ int uart_getc(int port, bool wait) { cbuf_t *rxbuf = &uart_rx_buf[port]; char c; + assert(port < NUM_UART); if (cbuf_read_char(rxbuf, &c, wait) == 1) return c; @@ -124,6 +198,11 @@ int uart_getc(int port, bool wait) { } void uart_flush_tx(int port) { + // waits until FIFO is empty and the final stop bit has been sent + uintptr_t base = uart_to_ptr(port); + while (!(UARTREG(base, UART_TFR) & 0x80)); + while (UARTREG(base, UART_TFR) & 0x8); + //udelay(250); // ugly hack } void uart_flush_rx(int port) { @@ -132,4 +211,20 @@ void uart_flush_rx(int port) { void uart_init_port(int port, uint baud) { } +static int cmd_uart_dump(int argc, const cmd_args *argv) { + uintptr_t base = uart_to_ptr(0); + uint32_t baud = 115200; + + if (argc >= 2) { + baud = argv[1].u; + } + dprintf(INFO, "CM_UARTDIV: 0x%x\nCM_UARTCTL: 0x%x\n", *REG32(CM_UARTDIV), *REG32(CM_UARTCTL)); + dprintf(INFO, "UART_IBRD: 0x%x\nUART_FBRD: 0x%x\n", UARTREG(base, UART_IBRD), UARTREG(base, UART_FBRD)); + uint32_t uart_freq = get_uart_base_freq(); + dprintf(INFO, "uart input clock is %d\n", uart_freq); + uint32_t divisor = calculate_baud_divisor(baud); + + dprintf(INFO, "want a uart divisor of 0x%x / 64\n", divisor); + return 0; +} diff --git a/platform/bcm28xx/udelay.c b/platform/bcm28xx/udelay.c new file mode 100644 index 0000000000..2b68356be2 --- /dev/null +++ b/platform/bcm28xx/udelay.c @@ -0,0 +1,13 @@ +#include +#include +#include +#include + +void udelay(uint32_t t) { + uint32_t tv = *REG32(ST_CLO); + for (;;) { + /* nop still takes a cycle i think? */ + __asm__ __volatile__ ("nop" :::); + if ((*REG32(ST_CLO) - tv) > t) return; + } +} diff --git a/platform/bcm28xx/vc4_timer.c b/platform/bcm28xx/vc4_timer.c new file mode 100644 index 0000000000..626b51a4d6 --- /dev/null +++ b/platform/bcm28xx/vc4_timer.c @@ -0,0 +1,2 @@ +lk_bigtime_t current_time_hires(void) { +} diff --git a/platform/bcm28xx/vec/include/platform/bcm28xx/vec.h b/platform/bcm28xx/vec/include/platform/bcm28xx/vec.h new file mode 100644 index 0000000000..a931407bd3 --- /dev/null +++ b/platform/bcm28xx/vec/include/platform/bcm28xx/vec.h @@ -0,0 +1,37 @@ +#pragma once + +#include +#include + +#define VEC_BASE (BCM_PERIPH_BASE_VIRT + 0x806000) + +#define VEC_WSE_RESET (VEC_BASE + 0x0c0) +#define VEC_WSE_CONTROL (VEC_BASE + 0x0c4) +#define VEC_CONFIG0 (VEC_BASE + 0x104) +#define VEC_CONFIG0_NTSC_STD 0 +#define VEC_CONFIG0_PAL_BDGHI_STD 1 +#define VEC_CONFIG0_PDEN BV(6) +#define VEC_SCHPH (VEC_BASE + 0x108) +#define VEC_SOFT_RESET (VEC_BASE + 0x10c) +#define VEC_CLMP0_START (VEC_BASE + 0x144) +#define VEC_CLMP0_END (VEC_BASE + 0x148) +#define VEC_FREQ3_2 (VEC_BASE + 0x180) +#define VEC_FREQ1_0 (VEC_BASE + 0x184) +#define VEC_CONFIG1 (VEC_BASE + 0x188) +#define VEC_CONFIG1_CUSTOM_FREQ BV(0) +#define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) +#define VEC_CONFIG2 (VEC_BASE + 0x18c) +#define VEC_CONFIG2_UV_DIG_DIS BV(6) +#define VEC_CONFIG2_RGB_DIG_DIS BV(5) +#define VEC_CONFIG3 (VEC_BASE + 0x1a0) +#define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) +#define VEC_MASK0 (VEC_BASE + 0x204) +#define VEC_CFG (VEC_BASE + 0x208) +#define VEC_CFG_VEC_EN BV(3) +#define VEC_DAC_CONFIG (VEC_BASE + 0x210) +#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) +#define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) +#define VEC_DAC_CONFIG_DAC_CTRL(x) (x) +#define VEC_DAC_MISC (VEC_BASE + 0x214) +#define VEC_DAC_MISC_DAC_RST_N BV(0) +#define VEC_DAC_MISC_VID_ACT BV(8) diff --git a/platform/bcm28xx/vec/pi-logo.h b/platform/bcm28xx/vec/pi-logo.h new file mode 100644 index 0000000000..4bb62c365d --- /dev/null +++ b/platform/bcm28xx/vec/pi-logo.h @@ -0,0 +1,4308 @@ +uint8_t pilogo[] = { +0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xed, 0x01, 0x6c, 0x02, +0x20, 0x08, 0xff, 0x00, 0x00, 0x00, 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00, +0x40, 0x00, 0x00, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x70, +0x83, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x10, 0xfe, 0x00, 0x00, 0x00, 0x00, 0xed, +0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, +0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x80, 0x00, +0x00, 0x00, 0xaf, 0x00, 0x00, 0x00, 0xbf, 0x00, 0x00, 0x00, 0xef, 0x96, 0x00, 0x00, 0x00, 0xff, +0x05, 0x00, 0x00, 0x00, 0xbf, 0x00, 0x00, 0x00, 0xbf, 0x00, 0x00, 0x00, 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0x60, 0x00, 0x00, 0x00, +0x80, 0x00, 0x00, 0x00, 0x9f, 0x83, 0x00, 0x00, 0x00, 0xbf, 0x02, 0x00, 0x00, 0x00, 0x80, 0x00, +0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x40, 0xe8, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, +0x00, 0x02, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x8f, 0x00, 0x00, 0x00, 0xbf, 0x84, 0x00, +0x00, 0x00, 0xff, 0x03, 0x00, 0x00, 0x00, 0xdf, 0x00, 0x00, 0x00, 0xaf, 0x00, 0x00, 0x00, 0x70, +0x00, 0x00, 0x00, 0x20, 0xfb, 0x00, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, +0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x9f, 0x00, 0x00, 0x00, 0xcf, 0x84, +0x00, 0x00, 0x00, 0xff, 0x02, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x00, 0x9f, 0x00, 0x00, 0x00, +0x50, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/platform/bcm28xx/vec/rules.mk b/platform/bcm28xx/vec/rules.mk new file mode 100644 index 0000000000..6995e03d81 --- /dev/null +++ b/platform/bcm28xx/vec/rules.mk @@ -0,0 +1,7 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) +MODULE := $(LOCAL_DIR) +MODULE_SRCS += $(LOCAL_DIR)/vec.c + +MODULES += platform/bcm28xx/pixelvalve platform/bcm28xx/hvs lib/tga platform/bcm28xx/power + +include make/module.mk diff --git a/platform/bcm28xx/vec/vec.c b/platform/bcm28xx/vec/vec.c new file mode 100644 index 0000000000..206fd20704 --- /dev/null +++ b/platform/bcm28xx/vec/vec.c @@ -0,0 +1,139 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pi-logo.h" + +//extern uint8_t* pilogo; + +enum vec_mode { + ntsc, + ntscj, + pal, + palm, +}; + +gfx_surface *framebuffer; +gfx_surface *logo; +int width; +int height; +int stride; + +static void draw_background_grid(void) { + //hvs_add_plane(framebuffer, 0, 0, false); +} + +static void vec_init(const struct app_descriptor *app) { + power_up_usb(); + hvs_initialize(); + *REG32(CM_VECDIV) = CM_PASSWORD | 4 << 12; + *REG32(CM_VECCTL) = CM_PASSWORD | CM_SRC_PLLC_CORE0; // technically its on the PER tap + *REG32(CM_VECCTL) = CM_PASSWORD | CM_VECCTL_ENAB_SET | CM_SRC_PLLC_CORE0; + int rate = measure_clock(29); + printf("vec rate: %f\n", ((float)rate)/1000/1000); + + *REG32(VEC_WSE_RESET) = 1; + *REG32(VEC_SOFT_RESET) = 1; + *REG32(VEC_WSE_CONTROL) = 0; + + *REG32(VEC_SCHPH) = 0x28; + *REG32(VEC_CLMP0_START) = 0xac; + *REG32(VEC_CLMP0_END) = 0xac; + *REG32(VEC_CONFIG2) = VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS; + *REG32(VEC_CONFIG3) = VEC_CONFIG3_HORIZ_LEN_STD; + *REG32(VEC_DAC_CONFIG) = VEC_DAC_CONFIG_DAC_CTRL(0xc) | VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46); + *REG32(VEC_MASK0) = 0; + enum vec_mode mode = ntsc; + switch (mode) { + case ntsc: + *REG32(VEC_CONFIG0) = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN; + *REG32(VEC_CONFIG1) = VEC_CONFIG1_C_CVBS_CVBS; + break; + case ntscj: + *REG32(VEC_CONFIG0) = VEC_CONFIG0_NTSC_STD; + *REG32(VEC_CONFIG1) = VEC_CONFIG1_C_CVBS_CVBS; + break; + case pal: + *REG32(VEC_CONFIG0) = VEC_CONFIG0_PAL_BDGHI_STD; + *REG32(VEC_CONFIG1) = VEC_CONFIG1_C_CVBS_CVBS; + break; + case palm: + *REG32(VEC_CONFIG0) = VEC_CONFIG0_PAL_BDGHI_STD; + *REG32(VEC_CONFIG1) = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ; + *REG32(VEC_FREQ3_2) = 0x223b; + *REG32(VEC_FREQ1_0) = 0x61d1; + break; + } + *REG32(VEC_DAC_MISC) = VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N; + *REG32(VEC_CFG) = VEC_CFG_VEC_EN; + struct pv_timings t; + bool ntsc = true; + if (ntsc) { + t.vfp = 3; + t.vsync = 4; + t.vbp = 16; + t.vactive = 240; + + t.vfp_even = 4; + t.vsync_even = 3; + t.vbp_even = 16; + t.vactive_even = 240; + + t.interlaced = true; + + t.hfp = 14; + t.hsync = 64; + t.hbp = 60; + t.hactive = 720; + } + setup_pixelvalve(&t, 2); + if (!framebuffer) { + width = t.hactive; + height = t.vactive * 2; + stride = t.hactive; + framebuffer = gfx_create_surface(NULL, width, height, width, GFX_FORMAT_ARGB_8888); + } + int grid = 20; + for (int x=0; x< width; x++) { + for (int y=0; y < height; y++) { + uint color = 0xff000000; + if (y % grid == 0) color |= 0xffffff; + if (y % grid == 1) color |= 0xffffff; + if (x % grid == 0) color |= 0xffffff; + if (x % grid == 1) color |= 0xffffff; + gfx_putpixel(framebuffer, x, y, color); + } + } + int list_start = display_slot; + hvs_add_plane(framebuffer, 0, 0, false); + hvs_terminate_list(); + *REG32(SCALER_DISPLIST1) = list_start; + + hvs_configure_channel(1, width, height, true); + + logo = tga_decode(pilogo, sizeof(pilogo), GFX_FORMAT_ARGB_8888); + list_start = display_slot; + hvs_add_plane(framebuffer, 0, 0, false); + hvs_add_plane_scaled(logo, (width/2) - (logo->width/2), 0, 100, 100, false); + hvs_terminate_list(); + *REG32(SCALER_DISPLIST1) = list_start; + + dance_start(logo, 1, &draw_background_grid); +} + +static void vec_entry(const struct app_descriptor *app, void *args) { +} + +APP_START(vec) + .init = vec_init, + .entry = vec_entry, +APP_END diff --git a/project/rpi1-test.mk b/project/rpi1-test.mk new file mode 100644 index 0000000000..3b1495bfef --- /dev/null +++ b/project/rpi1-test.mk @@ -0,0 +1,13 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi1 + +MODULES += \ + app/shell \ + app/stringtests \ + app/tests \ + lib/cksum \ + lib/debugcommands \ + platform/bcm28xx/pll \ + platform/bcm28xx/hvs-dance \ + lib/tga \ diff --git a/project/rpi2-test.mk b/project/rpi2-test.mk index c71a7e7c25..94483d7103 100644 --- a/project/rpi2-test.mk +++ b/project/rpi2-test.mk @@ -8,4 +8,6 @@ MODULES += \ app/tests \ lib/cksum \ lib/debugcommands \ - + platform/bcm28xx/pll \ + platform/bcm28xx/hvs-dance \ + lib/tga \ diff --git a/project/rpi3-bootcode.mk b/project/rpi3-bootcode.mk new file mode 100644 index 0000000000..540a8e3863 --- /dev/null +++ b/project/rpi3-bootcode.mk @@ -0,0 +1,20 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi3-vpu + +MODULES += \ + app/shell \ + platform/bcm28xx/rpi-ddr2/autoram \ + platform/bcm28xx/otp \ + #platform/bcm28xx/dpi \ + #lib/debugcommands \ + #app/shell \ + #app/tests \ + #app/stringtests \ + #app/rpi-vpu-bootload \ + #lib/cksum \ + +GLOBAL_DEFINES += BOOTCODE=1 + + +BOOTCODE := 1 diff --git a/project/rpi3-start.mk b/project/rpi3-start.mk new file mode 100644 index 0000000000..8cd7630134 --- /dev/null +++ b/project/rpi3-start.mk @@ -0,0 +1,13 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi3-vpu + +MODULES += \ + app/shell \ + app/stringtests \ + app/tests \ + lib/cksum \ + lib/debugcommands \ + platform/bcm28xx/otp \ + platform/bcm28xx/vec \ + platform/bcm28xx/hvs-dance \ diff --git a/project/rpi4-recovery.mk b/project/rpi4-recovery.mk new file mode 100644 index 0000000000..3d8f64afa8 --- /dev/null +++ b/project/rpi4-recovery.mk @@ -0,0 +1,10 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi4-vpu +BOOTCODE := 1 + +MODULES += \ + app/shell \ + lib/cksum \ + platform/bcm28xx/otp \ + lib/debugcommands \ diff --git a/project/rpi4-start4.mk b/project/rpi4-start4.mk new file mode 100644 index 0000000000..32dff7c592 --- /dev/null +++ b/project/rpi4-start4.mk @@ -0,0 +1,14 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi4-vpu + +MODULES += \ + app/shell \ + lib/cksum \ + platform/bcm28xx/otp \ + lib/debugcommands \ + app/stringtests \ + app/tests \ + platform/bcm28xx/arm_control \ + platform/bcm28xx/dpi \ + diff --git a/project/vc4-stage1.mk b/project/vc4-stage1.mk new file mode 100644 index 0000000000..88bc71956a --- /dev/null +++ b/project/vc4-stage1.mk @@ -0,0 +1,11 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi3-vpu + +MODULES += \ + app/vc4-stage1 \ + platform/bcm28xx/otp \ + platform/bcm28xx/rpi-ddr2 \ + +GLOBAL_DEFINES += BOOTCODE=1 WITH_NO_FP=1 NOVM_MAX_ARENAS=2 NOVM_DEFAULT_ARENA=0 +BOOTCODE := 1 diff --git a/project/vc4-stage2.mk b/project/vc4-stage2.mk new file mode 100644 index 0000000000..5ebfbdf6b5 --- /dev/null +++ b/project/vc4-stage2.mk @@ -0,0 +1,15 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +TARGET := rpi3-vpu + +MODULES += \ + app/vc4-stage2 \ + platform/bcm28xx/otp \ + #lib/debugcommands \ + lib/cksum \ + app/stringtests \ + app/tests \ + +#ARCH_COMPILEFLAGS += -fPIE +#ARCH_LDFLAGS += --emit-relocs --discard-none +#ARCH_LDFLAGS += --emit-relocs --discard-none --export-dynamic diff --git a/release.nix b/release.nix new file mode 100644 index 0000000000..bfa6e45091 --- /dev/null +++ b/release.nix @@ -0,0 +1,10 @@ +let + self = import ./.; +in { + arm = { + inherit (self.arm) rpi1-test rpi2-test rpi3-test; + }; + vc4 = { + inherit (self.vc4) rpi3 rpi4 vc4; + }; +} diff --git a/target/rpi1/rules.mk b/target/rpi1/rules.mk new file mode 100644 index 0000000000..9f2922408d --- /dev/null +++ b/target/rpi1/rules.mk @@ -0,0 +1,16 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +GLOBAL_INCLUDES += \ + $(LOCAL_DIR)/include + +PLATFORM := bcm28xx +ARCH := arm +ARM_CPU := arm1176jzf-s +HAVE_ARM_TIMER = 0 + +GLOBAL_DEFINES += CRYSTAL=19200000 BCM2835=1 + +#include make/module.mk + +ENABLE_THUMB := false +ARM_WITHOUT_VFP_NEON := true diff --git a/target/rpi2/rules.mk b/target/rpi2/rules.mk index fe10d50d72..14a8b334db 100644 --- a/target/rpi2/rules.mk +++ b/target/rpi2/rules.mk @@ -5,5 +5,10 @@ GLOBAL_INCLUDES += \ PLATFORM := bcm28xx +GLOBAL_DEFINES += CRYSTAL=19200000 BCM2836=1 +ARCH := arm +ARM_CPU := cortex-a7 +HAVE_ARM_TIMER = 1 + #include make/module.mk diff --git a/target/rpi3-vpu/rules.mk b/target/rpi3-vpu/rules.mk new file mode 100644 index 0000000000..fefce02e0e --- /dev/null +++ b/target/rpi3-vpu/rules.mk @@ -0,0 +1,12 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +GLOBAL_INCLUDES += \ + $(LOCAL_DIR)/include + +GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1 CRYSTAL=19200000 + +PLATFORM := bcm28xx +ARCH := vpu + +#include make/module.mk + diff --git a/target/rpi3/rules.mk b/target/rpi3/rules.mk index fe10d50d72..e2158b124f 100644 --- a/target/rpi3/rules.mk +++ b/target/rpi3/rules.mk @@ -4,6 +4,11 @@ GLOBAL_INCLUDES += \ $(LOCAL_DIR)/include PLATFORM := bcm28xx +ARCH := arm64 +ARM_CPU := cortex-a53 +HAVE_ARM_TIMER = 1 + +GLOBAL_DEFINES += CRYSTAL=19200000 BCM2837=1 #include make/module.mk diff --git a/target/rpi4-vpu/rules.mk b/target/rpi4-vpu/rules.mk new file mode 100644 index 0000000000..c2839c99ae --- /dev/null +++ b/target/rpi4-vpu/rules.mk @@ -0,0 +1,17 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +GLOBAL_INCLUDES += \ + $(LOCAL_DIR)/include + +GLOBAL_DEFINES += TARGET_HAS_DEBUG_LED=1 CRYSTAL=54000000 + +PLATFORM := bcm28xx +ARCH := vpu + +ifeq ($(BOOTCODE),1) +else + MODULES += platform/bcm28xx/start4 +endif + +#include make/module.mk + diff --git a/target/rpi4/rules.mk b/target/rpi4/rules.mk new file mode 100644 index 0000000000..9063edee6c --- /dev/null +++ b/target/rpi4/rules.mk @@ -0,0 +1,6 @@ +LOCAL_DIR := $(GET_LOCAL_DIR) + +GLOBAL_DEFINES += CRYSTAL=54000000 + +PLATFORM := bcm28xx +ARCH ?= arm64 diff --git a/todo.txt b/todo.txt new file mode 100644 index 0000000000..02c2b98531 --- /dev/null +++ b/todo.txt @@ -0,0 +1,4 @@ +use TARGET_HAS_DEBUG_LED on rpi + +fix \r\n issues +an IRQ between \r and \n can lead to text getting overwritten