From 8c34882db2cc21c7a5dfff1e558d4ae8623ffc38 Mon Sep 17 00:00:00 2001
From: hasan <99391294+mhasanbash@users.noreply.github.com>
Date: Fri, 30 Jun 2023 23:07:17 +0330
Subject: [PATCH] connect rgb to vga port

---
 output/clk_divider.v        | 20 +++++++++++++++++
 output/horizontal_counter.v | 44 +++++++++++++++++++++++++++++++++++++
 output/top.ucf              | 29 ++++++++++++++++++++++++
 output/top.v                | 30 +++++++++++++++++++++++++
 output/vertical_counter.v   | 43 ++++++++++++++++++++++++++++++++++++
 5 files changed, 166 insertions(+)
 create mode 100644 output/clk_divider.v
 create mode 100644 output/horizontal_counter.v
 create mode 100644 output/top.ucf
 create mode 100644 output/top.v
 create mode 100644 output/vertical_counter.v

diff --git a/output/clk_divider.v b/output/clk_divider.v
new file mode 100644
index 0000000..f03d574
--- /dev/null
+++ b/output/clk_divider.v
@@ -0,0 +1,20 @@
+`timescale 1ns / 1ps
+
+module clock_divider(
+    input clk,
+    output reg clk_25MH
+    );
+	 
+reg [1:0] counter;
+
+always @(posedge clk)
+begin
+	if (counter == 4)begin 
+		clk_25MH <= ~clk_25MH;
+		counter <= 0;
+		end
+	else
+      counter <= counter + 1;
+end
+
+endmodule
\ No newline at end of file
diff --git a/output/horizontal_counter.v b/output/horizontal_counter.v
new file mode 100644
index 0000000..23961b7
--- /dev/null
+++ b/output/horizontal_counter.v
@@ -0,0 +1,44 @@
+`timescale 1ns / 1ps
+
+module horizontal_counter(
+    input clk_25MHz,
+    output reg enable_V_counter = 0,
+    output reg Hsync = 0,
+    output reg [10:0] H_count_value = 0
+    );
+	 
+	 always @(posedge clk_25MHz)
+	 begin
+		//active video
+		if (H_count_value < 639) begin
+			H_count_value <= H_count_value + 1;
+			enable_V_counter <= 0;
+			Hsync <= 1;
+			end
+
+		//front porch
+		else if (H_count_value < 655 && H_count_value > 638) begin
+			H_count_value <= H_count_value + 1;
+			Hsync <= 1;
+		end
+
+		//sync pulse
+		else if ( H_count_value > 654 && H_count_value < 751) begin
+			H_count_value <= H_count_value + 1;
+			Hsync <= 0;
+		end
+
+		//back porch
+		else if (H_count_value > 750 && H_count_value < 799) begin
+			Hsync <= 1;
+			H_count_value <= H_count_value + 1;
+		end
+		//reset
+		else begin
+			H_count_value <= 0;
+			enable_V_counter <= 1;
+		end
+	 end
+
+
+endmodule
diff --git a/output/top.ucf b/output/top.ucf
new file mode 100644
index 0000000..3321c93
--- /dev/null
+++ b/output/top.ucf
@@ -0,0 +1,29 @@
+
+
+NET "Blue[7]" LOC = AC4;
+NET "Blue[6]" LOC = AC5;
+NET "Blue[5]" LOC = AB6;
+NET "Blue[4]" LOC = AB7;
+NET "Blue[3]" LOC = AA5;
+NET "Blue[2]" LOC = AB5;
+NET "Blue[1]" LOC = AC7;
+NET "Blue[0]" LOC = AD7;
+NET "Green[7]" LOC = Y8;
+NET "Green[6]" LOC = Y9;
+NET "Green[5]" LOC = AD4;
+NET "Green[4]" LOC = AD5;
+NET "Green[3]" LOC = AA6;
+NET "Green[2]" LOC = Y7;
+NET "Green[1]" LOC = AD6;
+NET "Green[0]" LOC = AE6;
+NET "Red[7]" LOC = AG5;
+NET "Red[6]" LOC = AF5;
+NET "Red[5]" LOC = W7;
+NET "Red[4]" LOC = V7;
+NET "Red[3]" LOC = AH5;
+NET "Red[2]" LOC = AG6;
+NET "Red[1]" LOC = Y11;
+NET "Red[0]" LOC = W11;
+NET "clk" LOC = AH17;
+NET "Vsynq" LOC = Y6;
+NET "Hsynq" LOC = AE7;
diff --git a/output/top.v b/output/top.v
new file mode 100644
index 0000000..bed15a6
--- /dev/null
+++ b/output/top.v
@@ -0,0 +1,30 @@
+`timescale 1ns / 1ps
+
+module top(
+    input clk,
+    input [7:0] Red_in,
+    input [7:0] Green_in,
+    input [7:0] Blue_in,
+    output Hsynq,
+    output Vsynq,
+    output [7:0] Red,
+    output [7:0] Green,
+    output [7:0] Blue
+    );
+	
+	wire clk_25;
+	wire enable_v_count;
+	wire [10:0] H_count_value;
+	wire [10:0] V_count_value;
+	clock_divider VGA_CLK(clk, clk_25);
+	horizontal_counter VGA_Hor(clk_25, enable_v_count, Hsynq , H_count_value);
+	vertical_counter VGA_Ver(clk_25, enable_v_count, Vsynq , V_count_value);
+	
+	
+	
+	assign Red = (H_count_value < 639 && H_count_value >=0 && V_count_value < 479 && V_count_value >= 0) ? Red_in:8'h0;
+	assign Green = (H_count_value < 639 && H_count_value >=0 && V_count_value < 479 && V_count_value >= 0) ? Green_in:8'h0;
+	assign Blue = (H_count_value < 639 && H_count_value >=0 && V_count_value < 479 && V_count_value >= 0) ? Blue_in:8'h0;
+
+
+endmodule
diff --git a/output/vertical_counter.v b/output/vertical_counter.v
new file mode 100644
index 0000000..8857bc9
--- /dev/null
+++ b/output/vertical_counter.v
@@ -0,0 +1,43 @@
+`timescale 1ns / 1ps
+
+module vertical_counter(
+    input clk_25MHz,
+    input enable_V_counter,
+    output reg Vsync = 0,
+    output reg [10:0] V_count_value = 0
+    );
+
+	 always @(posedge clk_25MHz)
+	 begin
+		if (enable_V_counter == 1'b1)begin
+			//active video
+			if (V_count_value < 479) begin
+				V_count_value <= V_count_value + 1;
+				Vsync <= 1;
+				end
+			
+			//front porch
+			else if (V_count_value > 478 && V_count_value < 490)begin
+				V_count_value <= V_count_value + 1;
+				Vsync <= 1;
+			end
+			
+			//sync pulse
+			else if (V_count_value > 489 && V_count_value < 492)begin
+				V_count_value <= V_count_value + 1;
+				Vsync <= 0;
+			end
+
+			//back porch
+			else if (V_count_value > 491 && V_count_value < 523)begin
+				V_count_value <= V_count_value + 1;
+				Vsync <= 1;
+			end
+
+			//reset
+			else
+				V_count_value <= 0;
+		end
+	 
+	 end
+endmodule