[AMDGPU] Add TDM Descriptor Optimization Pass

AMDGPU code generation frequently creates tensor and address descriptors using sequences of insertelement instructions. When these patterns have significant field reuse or cross-iteration dependencies, the current approach generates inefficient REG_SEQUENCE operations in MIR, instead of INSERT_SUBREG chains, leading to suboptimal register allocation.

This PR introduces the AMDGPUTDMOptimization pass that:

- Pattern Detection: Identifies descriptor creation chains with reusable constant fields
- Grouping: Groups similar patterns to maximize optimization opportunities
- Transformation: Converts insertelement chains to alloca + field updates in address space 5
- Integration: Works with SROA to generate INSERT_SUBREG operations for optimal register allocation

Author: tyb0807

llvm/lib/Target/AMDGPU/AMDGPU.h

@@ -59,6 +59,7 @@ FunctionPass *createAMDGPUCodeGenPreparePass();
 FunctionPass *createAMDGPULateCodeGenPrepareLegacyPass();
 FunctionPass *createAMDGPUReserveWWMRegsPass();
 FunctionPass *createAMDGPURewriteOutArgumentsPass();
+FunctionPass *createAMDGPUTDMOptimizationPass();
 ModulePass *
 createAMDGPULowerModuleLDSLegacyPass(const AMDGPUTargetMachine *TM = nullptr);
 ModulePass *createAMDGPULowerBufferFatPointersPass();
@@ -170,6 +171,8 @@ extern char &AMDGPUPrepareAGPRAllocLegacyID;
 void initializeAMDGPUReserveWWMRegsLegacyPass(PassRegistry &);
 extern char &AMDGPUReserveWWMRegsLegacyID;
 
+void initializeAMDGPUTDMOptimizationPass(PassRegistry &);
+
 void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
 extern char &AMDGPURewriteOutArgumentsID;