diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index 6153948a6a589..31b2383284f5f 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -1695,7 +1695,7 @@ void SemaRISCV::handleInterruptAttr(Decl *D, const ParsedAttr &AL) { // The QCI interrupt types require Xqciint case RISCVInterruptAttr::qcinest: case RISCVInterruptAttr::qcinonest: { - if (!HasFeature("experimental-xqciint")) { + if (!HasFeature("xqciint")) { Diag(AL.getLoc(), diag::err_riscv_attribute_interrupt_requires_extension) << RISCVInterruptAttr::ConvertInterruptTypeToStr(Type) << "Xqciint"; diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index bcc00d072c2ae..4be310244715e 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -178,6 +178,25 @@ // CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)) // CHECK-NEXT: xmipsexectl 1.0 'XMIPSEXECTL' (MIPS execution control) // CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding) +// CHECK-NEXT: xqci 0.13 'Xqci' (Qualcomm uC Extension) +// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension) +// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) +// CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension) +// CHECK-NEXT: xqcibm 0.8 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) +// CHECK-NEXT: xqcicli 0.3 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) +// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension) +// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) +// CHECK-NEXT: xqcicsr 0.4 'Xqcicsr' (Qualcomm uC CSR Extension) +// CHECK-NEXT: xqciint 0.10 'Xqciint' (Qualcomm uC Interrupts Extension) +// CHECK-NEXT: xqciio 0.1 'Xqciio' (Qualcomm uC External Input Output Extension) +// CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension) +// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension) +// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension) +// CHECK-NEXT: xqcilo 0.3 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension) +// CHECK-NEXT: xqcilsm 0.6 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) +// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension) +// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension) +// CHECK-NEXT: xqcisync 0.3 'Xqcisync' (Qualcomm uC Sync Delay Extension) // CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction) // CHECK-NEXT: xsfmm128t 0.6 'XSfmm128t' (TE=128 configuration) // CHECK-NEXT: xsfmm16t 0.6 'XSfmm16t' (TE=16 configuration) @@ -230,25 +249,6 @@ // CHECK-NEXT: smpmpmt 0.6 'Smpmpmt' (PMP-based Memory Types Extension) // CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-NEXT: xqccmp 0.3 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves) -// CHECK-NEXT: xqci 0.13 'Xqci' (Qualcomm uC Extension) -// CHECK-NEXT: xqcia 0.7 'Xqcia' (Qualcomm uC Arithmetic Extension) -// CHECK-NEXT: xqciac 0.3 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension) -// CHECK-NEXT: xqcibi 0.2 'Xqcibi' (Qualcomm uC Branch Immediate Extension) -// CHECK-NEXT: xqcibm 0.8 'Xqcibm' (Qualcomm uC Bit Manipulation Extension) -// CHECK-NEXT: xqcicli 0.3 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension) -// CHECK-NEXT: xqcicm 0.2 'Xqcicm' (Qualcomm uC Conditional Move Extension) -// CHECK-NEXT: xqcics 0.2 'Xqcics' (Qualcomm uC Conditional Select Extension) -// CHECK-NEXT: xqcicsr 0.4 'Xqcicsr' (Qualcomm uC CSR Extension) -// CHECK-NEXT: xqciint 0.10 'Xqciint' (Qualcomm uC Interrupts Extension) -// CHECK-NEXT: xqciio 0.1 'Xqciio' (Qualcomm uC External Input Output Extension) -// CHECK-NEXT: xqcilb 0.2 'Xqcilb' (Qualcomm uC Long Branch Extension) -// CHECK-NEXT: xqcili 0.2 'Xqcili' (Qualcomm uC Load Large Immediate Extension) -// CHECK-NEXT: xqcilia 0.2 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension) -// CHECK-NEXT: xqcilo 0.3 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension) -// CHECK-NEXT: xqcilsm 0.6 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension) -// CHECK-NEXT: xqcisim 0.2 'Xqcisim' (Qualcomm uC Simulation Hint Extension) -// CHECK-NEXT: xqcisls 0.2 'Xqcisls' (Qualcomm uC Scaled Load Store Extension) -// CHECK-NEXT: xqcisync 0.3 'Xqcisync' (Qualcomm uC Sync Delay Extension) // CHECK-NEXT: xrivosvisni 0.1 'XRivosVisni' (Rivos Vector Integer Small New) // CHECK-NEXT: xrivosvizip 0.1 'XRivosVizip' (Rivos Vector Register Zips) // CHECK-NEXT: xsfmclic 0.1 'XSfmclic' (SiFive CLIC Machine-mode CSRs) diff --git a/clang/test/Sema/riscv-interrupt-attr-qci.c b/clang/test/Sema/riscv-interrupt-attr-qci.c index e54c50c0e25bb..c957963fbc20d 100644 --- a/clang/test/Sema/riscv-interrupt-attr-qci.c +++ b/clang/test/Sema/riscv-interrupt-attr-qci.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple riscv32-unknown-elf -target-feature +experimental-xqciint -emit-llvm -DCHECK_IR < %s | FileCheck %s -// RUN: %clang_cc1 %s -triple riscv32-unknown-elf -target-feature +experimental-xqciint -verify=enabled,both -fsyntax-only +// RUN: %clang_cc1 -triple riscv32-unknown-elf -target-feature +xqciint -emit-llvm -DCHECK_IR < %s | FileCheck %s +// RUN: %clang_cc1 %s -triple riscv32-unknown-elf -target-feature +xqciint -verify=enabled,both -fsyntax-only // RUN: %clang_cc1 %s -triple riscv32-unknown-elf -verify=disabled,both -fsyntax-only -// RUN: %clang_cc1 %s -triple riscv32-unknown-elf -target-feature -experimental-xqciint -verify=disabled,both -fsyntax-only +// RUN: %clang_cc1 %s -triple riscv32-unknown-elf -target-feature -xqciint -verify=disabled,both -fsyntax-only // RUN: %clang_cc1 %s -triple riscv64-unknown-elf -verify=disabled,both -fsyntax-only -DRV64 #if defined(CHECK_IR) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 1e55fea9e1eb8..df5a595e8ec93 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -463,58 +463,61 @@ The current vendor extensions supported are: ``experimental-Xqccmp`` LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification `__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification. -``experimental-Xqcia`` +``Xqci`` + LLVM implements `version 0.13 of the Qualcomm uC extension specification `__ by Qualcomm. These instructions are only available for riscv32. + +``Xqcia`` LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqciac`` +``Xqciac`` LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcibi`` +``Xqcibi`` LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcibm`` +``Xqcibm`` LLVM implements `version 0.8 of the Qualcomm uC Bit Manipulation extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcicli`` +``Xqcicli`` LLVM implements `version 0.3 of the Qualcomm uC Conditional Load Immediate extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcicm`` +``Xqcicm`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcics`` +``Xqcics`` LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcicsr`` +``Xqcicsr`` LLVM implements `version 0.4 of the Qualcomm uC CSR extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqciint`` +``Xqciint`` LLVM implements `version 0.10 of the Qualcomm uC Interrupts extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqciio`` +``Xqciio`` LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcilb`` +``Xqcilb`` LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcili`` +``Xqcili`` LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcilia`` +``Xqcilia`` LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcilo`` +``Xqcilo`` LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcilsm`` +``Xqcilsm`` LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcisim`` +``Xqcisim`` LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcisls`` +``Xqcisls`` LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification `__ by Qualcomm. These instructions are only available for riscv32. -``experimental-Xqcisync`` +``Xqcisync`` LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification `__ by Qualcomm. These instructions are only available for riscv32. ``Xmipscbop`` diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 503cf641a221f..910a50214df2f 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -158,6 +158,7 @@ Changes to the RISC-V Backend * Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension). * DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax` to be used together when building for the RISC-V platform. +* The Xqci Qualcomm uC Vendor Extension is no longger marked as experimental. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 3a76ac6351fdf..66e1b18f37392 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1497,47 +1497,46 @@ def HasVendorXqccmp "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">; def FeatureVendorXqcia - : RISCVExperimentalExtension<0, 7, "Qualcomm uC Arithmetic Extension">; + : RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">; def HasVendorXqcia : Predicate<"Subtarget->hasVendorXqcia()">, AssemblerPredicate<(all_of FeatureVendorXqcia), "'Xqcia' (Qualcomm uC Arithmetic Extension)">; def FeatureVendorXqciac - : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension", + [FeatureStdExtZca]>; def HasVendorXqciac : Predicate<"Subtarget->hasVendorXqciac()">, AssemblerPredicate<(all_of FeatureVendorXqciac), "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">; def FeatureVendorXqcibi - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Branch Immediate Extension", + [FeatureStdExtZca]>; def HasVendorXqcibi : Predicate<"Subtarget->hasVendorXqcibi()">, AssemblerPredicate<(all_of FeatureVendorXqcibi), "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">; def FeatureVendorXqcibm - : RISCVExperimentalExtension<0, 8, "Qualcomm uC Bit Manipulation Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 8, "Qualcomm uC Bit Manipulation Extension", + [FeatureStdExtZca]>; def HasVendorXqcibm : Predicate<"Subtarget->hasVendorXqcibm()">, AssemblerPredicate<(all_of FeatureVendorXqcibm), "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">; def FeatureVendorXqcicli - : RISCVExperimentalExtension<0, 3, - "Qualcomm uC Conditional Load Immediate Extension">; + : RISCVExtension<0, 3, "Qualcomm uC Conditional Load Immediate Extension">; def HasVendorXqcicli : Predicate<"Subtarget->hasVendorXqcicli()">, AssemblerPredicate<(all_of FeatureVendorXqcicli), "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">; def FeatureVendorXqcicm - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Conditional Move Extension", + [FeatureStdExtZca]>; def HasVendorXqcicm : Predicate<"Subtarget->hasVendorXqcicm()">, AssemblerPredicate<(all_of FeatureVendorXqcicm), @@ -1546,7 +1545,7 @@ def NoVendorXqcicm : Predicate<"!Subtarget->hasVendorXqcicm()">; def FeatureVendorXqcics - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">; + : RISCVExtension<0, 2, "Qualcomm uC Conditional Select Extension">; def HasVendorXqcics : Predicate<"Subtarget->hasVendorXqcics()">, AssemblerPredicate<(all_of FeatureVendorXqcics), @@ -1555,102 +1554,100 @@ def NoVendorXqcics : Predicate<"!Subtarget->hasVendorXqcics()">; def FeatureVendorXqcicsr - : RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">; + : RISCVExtension<0, 4, "Qualcomm uC CSR Extension">; def HasVendorXqcicsr : Predicate<"Subtarget->hasVendorXqcicsr()">, AssemblerPredicate<(all_of FeatureVendorXqcicsr), "'Xqcicsr' (Qualcomm uC CSR Extension)">; def FeatureVendorXqciint - : RISCVExperimentalExtension<0, 10, "Qualcomm uC Interrupts Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 10, "Qualcomm uC Interrupts Extension", + [FeatureStdExtZca]>; def HasVendorXqciint : Predicate<"Subtarget->hasVendorXqciint()">, AssemblerPredicate<(all_of FeatureVendorXqciint), "'Xqciint' (Qualcomm uC Interrupts Extension)">; def FeatureVendorXqciio - : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">; + : RISCVExtension<0, 1, "Qualcomm uC External Input Output Extension">; def HasVendorXqciio : Predicate<"Subtarget->hasVendorXqciio()">, AssemblerPredicate<(all_of FeatureVendorXqciio), "'Xqciio' (Qualcomm uC External Input Output Extension)">; def FeatureVendorXqcilb - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Long Branch Extension", + [FeatureStdExtZca]>; def HasVendorXqcilb : Predicate<"Subtarget->hasVendorXqcilb()">, AssemblerPredicate<(all_of FeatureVendorXqcilb), "'Xqcilb' (Qualcomm uC Long Branch Extension)">; def FeatureVendorXqcili - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Load Large Immediate Extension", + [FeatureStdExtZca]>; def HasVendorXqcili : Predicate<"Subtarget->hasVendorXqcili()">, AssemblerPredicate<(all_of FeatureVendorXqcili), "'Xqcili' (Qualcomm uC Load Large Immediate Extension)">; def FeatureVendorXqcilia - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension", + [FeatureStdExtZca]>; def HasVendorXqcilia : Predicate<"Subtarget->hasVendorXqcilia()">, AssemblerPredicate<(all_of FeatureVendorXqcilia), "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">; def FeatureVendorXqcilo - : RISCVExperimentalExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension", + [FeatureStdExtZca]>; def HasVendorXqcilo : Predicate<"Subtarget->hasVendorXqcilo()">, AssemblerPredicate<(all_of FeatureVendorXqcilo), "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">; def FeatureVendorXqcilsm - : RISCVExperimentalExtension<0, 6, - "Qualcomm uC Load Store Multiple Extension">; + : RISCVExtension<0, 6, "Qualcomm uC Load Store Multiple Extension">; def HasVendorXqcilsm : Predicate<"Subtarget->hasVendorXqcilsm()">, AssemblerPredicate<(all_of FeatureVendorXqcilsm), "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">; def FeatureVendorXqcisim - : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 2, "Qualcomm uC Simulation Hint Extension", + [FeatureStdExtZca]>; def HasVendorXqcisim : Predicate<"Subtarget->hasVendorXqcisim()">, AssemblerPredicate<(all_of FeatureVendorXqcisim), "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">; def FeatureVendorXqcisls - : RISCVExperimentalExtension<0, 2, - "Qualcomm uC Scaled Load Store Extension">; + : RISCVExtension<0, 2, "Qualcomm uC Scaled Load Store Extension">; def HasVendorXqcisls : Predicate<"Subtarget->hasVendorXqcisls()">, AssemblerPredicate<(all_of FeatureVendorXqcisls), "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">; def FeatureVendorXqcisync - : RISCVExperimentalExtension<0, 3, "Qualcomm uC Sync Delay Extension", - [FeatureStdExtZca]>; + : RISCVExtension<0, 3, "Qualcomm uC Sync Delay Extension", + [FeatureStdExtZca]>; def HasVendorXqcisync : Predicate<"Subtarget->hasVendorXqcisync()">, AssemblerPredicate<(all_of FeatureVendorXqcisync), "'Xqcisync' (Qualcomm uC Sync Delay Extension)">; def FeatureVendorXqci - : RISCVExperimentalExtension<0, 13, "Qualcomm uC Extension", - [FeatureVendorXqcia, FeatureVendorXqciac, - FeatureVendorXqcibi, FeatureVendorXqcibm, - FeatureVendorXqcicli, FeatureVendorXqcicm, - FeatureVendorXqcics, FeatureVendorXqcicsr, - FeatureVendorXqciint, FeatureVendorXqciio, - FeatureVendorXqcilb, FeatureVendorXqcili, - FeatureVendorXqcilia, FeatureVendorXqcilo, - FeatureVendorXqcilsm, FeatureVendorXqcisim, - FeatureVendorXqcisls, FeatureVendorXqcisync]>; + : RISCVExtension<0, 13, "Qualcomm uC Extension", + [FeatureVendorXqcia, FeatureVendorXqciac, + FeatureVendorXqcibi, FeatureVendorXqcibm, + FeatureVendorXqcicli, FeatureVendorXqcicm, + FeatureVendorXqcics, FeatureVendorXqcicsr, + FeatureVendorXqciint, FeatureVendorXqciio, + FeatureVendorXqcilb, FeatureVendorXqcili, + FeatureVendorXqcilia, FeatureVendorXqcilo, + FeatureVendorXqcilsm, FeatureVendorXqcisim, + FeatureVendorXqcisls, FeatureVendorXqcisync]>; // Rivos Extension(s) diff --git a/llvm/test/CodeGen/RISCV/attributes-qc.ll b/llvm/test/CodeGen/RISCV/attributes-qc.ll index 1c62378dea9ca..4cbf3510b24ec 100644 --- a/llvm/test/CodeGen/RISCV/attributes-qc.ll +++ b/llvm/test/CodeGen/RISCV/attributes-qc.ll @@ -1,24 +1,24 @@ ;; Generate ELF attributes from llc. ; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV32XQCCMP %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibi %s -o - | FileCheck --check-prefix=RV32XQCIBI %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm %s -o - | FileCheck --check-prefix=RV32XQCIBM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqciio %s -o - | FileCheck --check-prefix=RV32XQCIIO %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilb %s -o - | FileCheck --check-prefix=RV32XQCILB %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcia %s -o - | FileCheck --check-prefix=RV32XQCIA %s +; RUN: llc -mtriple=riscv32 -mattr=+xqciac %s -o - | FileCheck --check-prefix=RV32XQCIAC %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcibi %s -o - | FileCheck --check-prefix=RV32XQCIBI %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm %s -o - | FileCheck --check-prefix=RV32XQCIBM %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcicli %s -o - | FileCheck --check-prefix=RV32XQCICLI %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm %s -o - | FileCheck --check-prefix=RV32XQCICM %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcics %s -o - | FileCheck --check-prefix=RV32XQCICS %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcicsr %s -o - | FileCheck --check-prefix=RV32XQCICSR %s +; RUN: llc -mtriple=riscv32 -mattr=+xqciint %s -o - | FileCheck --check-prefix=RV32XQCIINT %s +; RUN: llc -mtriple=riscv32 -mattr=+xqciio %s -o - | FileCheck --check-prefix=RV32XQCIIO %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcilb %s -o - | FileCheck --check-prefix=RV32XQCILB %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcili %s -o - | FileCheck --check-prefix=RV32XQCILI %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcilia %s -o - | FileCheck --check-prefix=RV32XQCILIA %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcilo %s -o - | FileCheck --check-prefix=RV32XQCILO %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcilsm %s -o - | FileCheck --check-prefix=RV32XQCILSM %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcisim %s -o - | FileCheck --check-prefix=RV32XQCISIM %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcisls %s -o - | FileCheck --check-prefix=RV32XQCISLS %s +; RUN: llc -mtriple=riscv32 -mattr=+xqcisync %s -o - | FileCheck --check-prefix=RV32XQCISYNC %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s diff --git a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll index a03a53215be38..14e1ec459dbcb 100644 --- a/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll +++ b/llvm/test/CodeGen/RISCV/cmov-branch-opt.ll @@ -11,7 +11,7 @@ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-NOZICOND,SFB-NOZICOND-C %s ; RUN: llc -mtriple=riscv64 -mattr=+short-forward-branch-ialu,+zicond -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=SHORT_FORWARD,SFB-ZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; The conditional move optimization in sifive-p450 requires that only a diff --git a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll index 220494a4c4ff8..ee313368f4584 100644 --- a/llvm/test/CodeGen/RISCV/codemodel-lowering.ll +++ b/llvm/test/CodeGen/RISCV/codemodel-lowering.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32F-SMALL -; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=small -verify-machineinstrs -mattr=+xqcili < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCILI-SMALL,RV32FXQCILI-SMALL ; RUN: llc -mtriple=riscv32 -mattr=+f,+zfh -target-abi=ilp32f -code-model=medium -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32F-MEDIUM @@ -13,7 +13,7 @@ ; RUN: | FileCheck %s -check-prefixes=RV64I-LARGE,RV64F-LARGE ; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I-SMALL,RV32FINX-SMALL -; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=small -verify-machineinstrs -mattr=+xqcili < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCILI-SMALL,RV32FINXXQCILI-SMALL ; RUN: llc -mtriple=riscv32 -mattr=+zfinx,+zhinx -target-abi=ilp32 -code-model=medium -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I-MEDIUM,RV32FINX-MEDIUM diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 83a9562a69afb..e4e06d579a607 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -30,25 +30,6 @@ ; CHECK-NEXT: experimental-smpmpmt - 'Smpmpmt' (PMP-based Memory Types Extension). ; CHECK-NEXT: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses). ; CHECK-NEXT: experimental-xqccmp - 'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves). -; CHECK-NEXT: experimental-xqci - 'Xqci' (Qualcomm uC Extension). -; CHECK-NEXT: experimental-xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension). -; CHECK-NEXT: experimental-xqciac - 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension). -; CHECK-NEXT: experimental-xqcibi - 'Xqcibi' (Qualcomm uC Branch Immediate Extension). -; CHECK-NEXT: experimental-xqcibm - 'Xqcibm' (Qualcomm uC Bit Manipulation Extension). -; CHECK-NEXT: experimental-xqcicli - 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension). -; CHECK-NEXT: experimental-xqcicm - 'Xqcicm' (Qualcomm uC Conditional Move Extension). -; CHECK-NEXT: experimental-xqcics - 'Xqcics' (Qualcomm uC Conditional Select Extension). -; CHECK-NEXT: experimental-xqcicsr - 'Xqcicsr' (Qualcomm uC CSR Extension). -; CHECK-NEXT: experimental-xqciint - 'Xqciint' (Qualcomm uC Interrupts Extension). -; CHECK-NEXT: experimental-xqciio - 'Xqciio' (Qualcomm uC External Input Output Extension). -; CHECK-NEXT: experimental-xqcilb - 'Xqcilb' (Qualcomm uC Long Branch Extension). -; CHECK-NEXT: experimental-xqcili - 'Xqcili' (Qualcomm uC Load Large Immediate Extension). -; CHECK-NEXT: experimental-xqcilia - 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension). -; CHECK-NEXT: experimental-xqcilo - 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension). -; CHECK-NEXT: experimental-xqcilsm - 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension). -; CHECK-NEXT: experimental-xqcisim - 'Xqcisim' (Qualcomm uC Simulation Hint Extension). -; CHECK-NEXT: experimental-xqcisls - 'Xqcisls' (Qualcomm uC Scaled Load Store Extension). -; CHECK-NEXT: experimental-xqcisync - 'Xqcisync' (Qualcomm uC Sync Delay Extension). ; CHECK-NEXT: experimental-xrivosvisni - 'XRivosVisni' (Rivos Vector Integer Small New). ; CHECK-NEXT: experimental-xrivosvizip - 'XRivosVizip' (Rivos Vector Register Zips). ; CHECK-NEXT: experimental-xsfmclic - 'XSfmclic' (SiFive CLIC Machine-mode CSRs). @@ -211,6 +192,25 @@ ; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)). ; CHECK-NEXT: mipsexectl - 'XMIPSEXECTL' (MIPS execution control). ; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding). +; CHECK-NEXT: xqci - 'Xqci' (Qualcomm uC Extension). +; CHECK-NEXT: xqcia - 'Xqcia' (Qualcomm uC Arithmetic Extension). +; CHECK-NEXT: xqciac - 'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension). +; CHECK-NEXT: xqcibi - 'Xqcibi' (Qualcomm uC Branch Immediate Extension). +; CHECK-NEXT: xqcibm - 'Xqcibm' (Qualcomm uC Bit Manipulation Extension). +; CHECK-NEXT: xqcicli - 'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension). +; CHECK-NEXT: xqcicm - 'Xqcicm' (Qualcomm uC Conditional Move Extension). +; CHECK-NEXT: xqcics - 'Xqcics' (Qualcomm uC Conditional Select Extension). +; CHECK-NEXT: xqcicsr - 'Xqcicsr' (Qualcomm uC CSR Extension). +; CHECK-NEXT: xqciint - 'Xqciint' (Qualcomm uC Interrupts Extension). +; CHECK-NEXT: xqciio - 'Xqciio' (Qualcomm uC External Input Output Extension). +; CHECK-NEXT: xqcilb - 'Xqcilb' (Qualcomm uC Long Branch Extension). +; CHECK-NEXT: xqcili - 'Xqcili' (Qualcomm uC Load Large Immediate Extension). +; CHECK-NEXT: xqcilia - 'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension). +; CHECK-NEXT: xqcilo - 'Xqcilo' (Qualcomm uC Large Offset Load Store Extension). +; CHECK-NEXT: xqcilsm - 'Xqcilsm' (Qualcomm uC Load Store Multiple Extension). +; CHECK-NEXT: xqcisim - 'Xqcisim' (Qualcomm uC Simulation Hint Extension). +; CHECK-NEXT: xqcisls - 'Xqcisls' (Qualcomm uC Scaled Load Store Extension). +; CHECK-NEXT: xqcisync - 'Xqcisync' (Qualcomm uC Sync Delay Extension). ; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction). ; CHECK-NEXT: xsfmm128t - 'XSfmm128t' (TE=128 configuration). ; CHECK-NEXT: xsfmm16t - 'XSfmm16t' (TE=16 configuration). diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll index c367b265ff954..d7e91986b539c 100644 --- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcili< %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqcili< %s \ ; RUN: | FileCheck -check-prefix=RV32IXQCILI %s ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -code-model=medium < %s \ ; RUN: | FileCheck -check-prefix=RV32I-MEDIUM %s diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll index 5bc8b2333764e..78fcd06c99359 100644 --- a/llvm/test/CodeGen/RISCV/i32-icmp.ll +++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcilia < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqcilia < %s \ ; RUN: | FileCheck %s -check-prefix=RV32XQCILIA define i32 @icmp_eq(i32 %a, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index fad51697264f4..9fe834d0fcb35 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32I -; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-xqcili \ +; RUN: llc -mtriple=riscv32 -riscv-disable-using-constant-pool-for-large-ints -mattr=+xqcili \ ; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV32IXQCILI ; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV64I,RV64-NOPOOL diff --git a/llvm/test/CodeGen/RISCV/jumptable.ll b/llvm/test/CodeGen/RISCV/jumptable.ll index a838d54ad5e9b..aea94fb65e92a 100644 --- a/llvm/test/CodeGen/RISCV/jumptable.ll +++ b/llvm/test/CodeGen/RISCV/jumptable.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL -; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -mattr=+experimental-xqcili < %s \ +; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -mattr=+xqcili < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32IXQCILI-SMALL ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM @@ -15,7 +15,7 @@ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV64I-PIC ; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-SMALL-7-ENTRIES -; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 -mattr=+experimental-xqcili < %s \ +; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs -riscv-min-jump-table-entries=7 -mattr=+xqcili < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32IXQCILI-SMALL-7-ENTRIES ; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs -riscv-min-jump-table-entries=7 < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I-MEDIUM-7-ENTRIES diff --git a/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir b/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir index 5b9aad84c354f..09183c57fe0d2 100644 --- a/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir +++ b/llvm/test/CodeGen/RISCV/make-compressible-xqci.mir @@ -1,11 +1,11 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -o - %s -mtriple=riscv32 -mattr=+experimental-xqcilo,+experimental-xqcilia -simplify-mir \ +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+xqcilo,+xqcilia -simplify-mir \ # RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI %s -# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+experimental-xqcilo,+experimental-xqcilia -simplify-mir \ +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+xqcilo,+xqcilia -simplify-mir \ # RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_ZCB %s -# RUN: llc -o - %s -mtriple=riscv32 -mattr=+experimental-xqcilo -simplify-mir \ +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+xqcilo -simplify-mir \ # RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_NOXQCILIA %s -# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+experimental-xqcilo -simplify-mir \ +# RUN: llc -o - %s -mtriple=riscv32 -mattr=+zcb,+xqcilo -simplify-mir \ # RUN: -run-pass=riscv-make-compressible | FileCheck --check-prefixes=RV32XQCI_ZCB_NOXQCILIA %s --- | diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll index 316f626b4bc11..42d7c96230dda 100644 --- a/llvm/test/CodeGen/RISCV/min-max.ll +++ b/llvm/test/CodeGen/RISCV/min-max.ll @@ -5,7 +5,7 @@ ; RUN: FileCheck %s --check-prefixes=ZBB,RV32ZBB ; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | \ ; RUN: FileCheck %s --check-prefixes=ZBB,RV64ZBB -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s | \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s | \ ; RUN: FileCheck %s --check-prefixes=XQCI ; RUN: llc < %s -mtriple=riscv32 -mattr=+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll index 9fa26c74021cb..84ad3bfd1737d 100644 --- a/llvm/test/CodeGen/RISCV/pr148084.ll +++ b/llvm/test/CodeGen/RISCV/pr148084.ll @@ -276,4 +276,4 @@ get_tx_mask.exit: ; preds = %._crit_edge.i, %bb ret void } -attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqccmp,-experimental-xqcia,-experimental-xqciac,-experimental-xqcibi,-experimental-xqcibm,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqciio,-experimental-xqcilb,-experimental-xqcili,-experimental-xqcilia,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisim,-experimental-xqcisls,-experimental-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" } +attributes #0 = { noimplicitfloat nounwind sspstrong uwtable vscale_range(2,1024) "frame-pointer"="non-leaf" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+b,+c,+d,+f,+m,+relax,+unaligned-scalar-mem,+unaligned-vector-mem,+v,+zaamo,+zalrsc,+zba,+zbb,+zbs,+zca,+zcd,+zicsr,+zifencei,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-e,-experimental-p,-experimental-smctr,-experimental-ssctr,-experimental-svukte,-experimental-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscmov,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zbc,-zbkb,-zbkc,-zbkx,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" } diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll index 1b736611cbd1e..6c8037fb0f006 100644 --- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll +++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+f -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+f -o - %s \ ; RUN: -verify-machineinstrs | FileCheck --check-prefix=QCI-F %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+d -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+d -o - %s \ ; RUN: -verify-machineinstrs | FileCheck --check-prefix=QCI-D %s ;; This tests "interrupt"="qci-nest" and "interrupt"="qci-nonest" frame lowering diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll index bcd2c3820328d..20c907c9bc28c 100644 --- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll +++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll @@ -1,24 +1,24 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint -o - %s \ ; RUN: -verify-machineinstrs | FileCheck --check-prefix=QCI %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+save-restore \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+save-restore \ ; RUN: -o - %s -verify-machineinstrs \ ; RUN: | FileCheck --check-prefix=QCI %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint -o - %s \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint -o - %s \ ; RUN: -verify-machineinstrs -frame-pointer=all | FileCheck --check-prefix=QCI-FP %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+zcmp \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+zcmp \ ; RUN: -o - %s -verify-machineinstrs \ ; RUN: | FileCheck --check-prefix=QCI-PUSH-POP %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+experimental-xqccmp \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+experimental-xqccmp \ ; RUN: -o - %s -verify-machineinstrs \ ; RUN: | FileCheck --check-prefix=QCI-QCCMP-PUSH-POP %s -; RUN: llc -mtriple riscv32-unknown-elf -mattr=+experimental-xqciint,+experimental-xqccmp \ +; RUN: llc -mtriple riscv32-unknown-elf -mattr=+xqciint,+experimental-xqccmp \ ; RUN: -o - %s -verify-machineinstrs -frame-pointer=all \ ; RUN: | FileCheck --check-prefix=QCI-QCCMP-PUSH-POP-FP %s diff --git a/llvm/test/CodeGen/RISCV/select-bare.ll b/llvm/test/CodeGen/RISCV/select-bare.ll index fe0f74f5f2fa3..8fec4a7277510 100644 --- a/llvm/test/CodeGen/RISCV/select-bare.ll +++ b/llvm/test/CodeGen/RISCV/select-bare.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s -check-prefix=RV32I ; RUN: llc -mtriple=riscv64 -mattr=+xmipscmov -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I-CCMOV %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind { diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll index a215f893837a8..299fe89a05328 100644 --- a/llvm/test/CodeGen/RISCV/select-cc.ll +++ b/llvm/test/CodeGen/RISCV/select-cc.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -disable-block-placement -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64I %s diff --git a/llvm/test/CodeGen/RISCV/select-cond.ll b/llvm/test/CodeGen/RISCV/select-cond.ll index ab3306e4e78e3..52c21f05e9191 100644 --- a/llvm/test/CodeGen/RISCV/select-cond.ll +++ b/llvm/test/CodeGen/RISCV/select-cond.ll @@ -3,11 +3,11 @@ ; RUN: | FileCheck %s --check-prefixes=RV32 ; RUN: llc -mtriple=riscv32 -mattr=+xtheadcondmov -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32-THEAD -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32-XQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcics -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32-XQCICS -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV64 diff --git a/llvm/test/CodeGen/RISCV/select-const.ll b/llvm/test/CodeGen/RISCV/select-const.ll index 1c6cc6dc97900..5069924eba5b6 100644 --- a/llvm/test/CodeGen/RISCV/select-const.ll +++ b/llvm/test/CodeGen/RISCV/select-const.ll @@ -5,7 +5,7 @@ ; RUN: | FileCheck -check-prefixes=RV32,RV32IF %s ; RUN: llc -mtriple=riscv32 -mattr=+zicond -target-abi=ilp32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32,RV32ZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI ; RUN: llc -mtriple=riscv64 -target-abi=lp64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64,RV64I %s diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll index d7a6056a4feb4..96433f1a077e4 100644 --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m,+xventanacondops -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,RV64IMXVTCONDOPS %s ; RUN: llc -mtriple=riscv32 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV32IMZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zicond -verify-machineinstrs < %s | FileCheck --check-prefixes=CHECK,CHECKZICOND,RV64IMZICOND %s -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i16 @select_xor_1(i16 %A, i8 %cond) { diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll index 4f51e602d1346..452d014766bbc 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili | FileCheck %s --check-prefixes=RV32I +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcili | FileCheck %s --check-prefixes=RV32I ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 | FileCheck %s --check-prefixes=RV64I -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcili,+short-forward-branch-ialu | \ +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcili,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB ; RUN: llc < %s -verify-machineinstrs -mtriple=riscv64 -mattr=+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV64I-SFB diff --git a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll index a82aba1ce5ab9..741e4ce40c544 100644 --- a/llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll +++ b/llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcilo | FileCheck %s --check-prefixes=RV32I -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcilo,+short-forward-branch-ialu | \ +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo | FileCheck %s --check-prefixes=RV32I +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo,+short-forward-branch-ialu | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFB -; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+experimental-xqcilo,+short-forward-branch-iload | \ +; RUN: llc < %s -verify-machineinstrs -mtriple=riscv32 -mattr=+xqcilo,+short-forward-branch-iload | \ ; RUN: FileCheck %s --check-prefixes=RV32I-SFBILOAD define i32 @test_i8_s(ptr %base, i1 zeroext %x, i32 %b) nounwind { diff --git a/llvm/test/CodeGen/RISCV/stack-offset.ll b/llvm/test/CodeGen/RISCV/stack-offset.ll index 79b937a1a292c..e42b868bb80da 100644 --- a/llvm/test/CodeGen/RISCV/stack-offset.ll +++ b/llvm/test/CodeGen/RISCV/stack-offset.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32,RV32I -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcilia < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqcilia < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32XQCILIA ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+zba < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32,RV32ZBA diff --git a/llvm/test/CodeGen/RISCV/xqcia.ll b/llvm/test/CodeGen/RISCV/xqcia.ll index 3bbf33328f529..43987852a98b3 100644 --- a/llvm/test/CodeGen/RISCV/xqcia.ll +++ b/llvm/test/CodeGen/RISCV/xqcia.ll @@ -2,7 +2,7 @@ ; Test that we are able to generate the Xqcia instructions ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcia -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcia -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCIA define i32 @addsat(i32 %a, i32 %b) { diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll index 92be4c977dd82..07fbfd38dbe11 100644 --- a/llvm/test/CodeGen/RISCV/xqciac.ll +++ b/llvm/test/CodeGen/RISCV/xqciac.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IM -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqciac -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+xqciac -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IMXQCIAC -; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-xqciac,+zba -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+m,+xqciac,+zba -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32IZBAMXQCIAC define dso_local i32 @mul(i32 %a, i32 %b) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/RISCV/xqcibi.ll b/llvm/test/CodeGen/RISCV/xqcibi.ll index 518ada6c9e631..5b742791c7387 100644 --- a/llvm/test/CodeGen/RISCV/xqcibi.ll +++ b/llvm/test/CodeGen/RISCV/xqcibi.ll @@ -2,7 +2,7 @@ ; Test that we are able to generate the Xqcibi instructions ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibi -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibi -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCIBI define i32 @beqimm(i32 %a) { diff --git a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll index 5ec403777cedd..a25ed44b805d1 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s -check-prefixes=RV32I ; RUN: llc -mtriple=riscv32 -mattr=+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32ZBB -; RUN: llc -mtriple=riscv32 -mattr=+zbb,experimental-xqcibm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zbb,xqcibm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefix=RV32ZBBXQCIBM define i8 @test_cttz_i8(i8 %a) nounwind { diff --git a/llvm/test/CodeGen/RISCV/xqcibm-extract.ll b/llvm/test/CodeGen/RISCV/xqcibm-extract.ll index 34657baa47f48..5161d3f7f0460 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-extract.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-extract.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XQCIBM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbb -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm,+zbb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=CHECK,RV32XQCIBMZBB define i32 @sexti1_i32(i1 %a) nounwind { diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll b/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll index 54eab0de0465e..647f643ae7fbb 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-insbi.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 --verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm --verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm --verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32XQCIBM define i32 @insb(i32 %in1, i32 %in2) { diff --git a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll index 2a954ae1eb297..2405879437404 100644 --- a/llvm/test/CodeGen/RISCV/xqcibm-insert.ll +++ b/llvm/test/CodeGen/RISCV/xqcibm-insert.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcibm,+zbs -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcibm,+zbs -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCIBMZBS diff --git a/llvm/test/CodeGen/RISCV/xqcicli.ll b/llvm/test/CodeGen/RISCV/xqcicli.ll index 229ef67e208fb..84926cb638dce 100644 --- a/llvm/test/CodeGen/RISCV/xqcicli.ll +++ b/llvm/test/CodeGen/RISCV/xqcicli.ll @@ -2,9 +2,9 @@ ; Test that we are able to generate the Xqcicli instructions ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicli -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicli -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICLI -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_cc_example_eq(i32 %a, i32 %b, i32 %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcicm.ll b/llvm/test/CodeGen/RISCV/xqcicm.ll index dbfbaa7c033a2..f8825e079ccfd 100644 --- a/llvm/test/CodeGen/RISCV/xqcicm.ll +++ b/llvm/test/CodeGen/RISCV/xqcicm.ll @@ -2,11 +2,11 @@ ; Test that we are able to generate the Xqcicm instructions ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_example(i32 %cond, i32 %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcics.ll b/llvm/test/CodeGen/RISCV/xqcics.ll index 123226655de3f..a269a720353ac 100644 --- a/llvm/test/CodeGen/RISCV/xqcics.ll +++ b/llvm/test/CodeGen/RISCV/xqcics.ll @@ -2,11 +2,11 @@ ; Test that we are able to generate the Xqcics instructions ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcics -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICS -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcics,+experimental-xqcicm -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcics,+xqcicm -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCICM -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcicm,+experimental-xqcics,+experimental-xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcicm,+xqcics,+xqcicli,+zca,+short-forward-branch-ialu,+conditional-cmv-fusion -verify-machineinstrs < %s \ ; RUN: | FileCheck %s --check-prefixes=RV32IXQCI define i32 @select_cc_example_eq_s1(i32 %a, i32 %b, i32 %x, i32 %y) { diff --git a/llvm/test/CodeGen/RISCV/xqcilia.ll b/llvm/test/CodeGen/RISCV/xqcilia.ll index 0f14044d62dc8..2d689fc3f6175 100644 --- a/llvm/test/CodeGen/RISCV/xqcilia.ll +++ b/llvm/test/CodeGen/RISCV/xqcilia.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; Test that we are able to generate the Xqcilia instructions ; RUN: llc < %s -mtriple=riscv32 | FileCheck %s -check-prefix=RV32I -; RUN: llc < %s -mtriple=riscv32 -mattr=+experimental-xqcilia | FileCheck %s -check-prefix=RV32XQCILIA +; RUN: llc < %s -mtriple=riscv32 -mattr=+xqcilia | FileCheck %s -check-prefix=RV32XQCILIA define i32 @add(i32 %a, i32 %b) { ; RV32I-LABEL: add: diff --git a/llvm/test/CodeGen/RISCV/xqcilo.ll b/llvm/test/CodeGen/RISCV/xqcilo.ll index fb06f21b3ab98..0e22f8b074bad 100644 --- a/llvm/test/CodeGen/RISCV/xqcilo.ll +++ b/llvm/test/CodeGen/RISCV/xqcilo.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilo -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+xqcilo -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCILO define i32 @lb_ri(i8* %a) { diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir b/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir index 126c1fd442000..977a4d785cb34 100644 --- a/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir +++ b/llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 -# RUN: llc -mtriple=riscv32 -mattr=+experimental-xqcilsm -run-pass=riscv-load-store-opt %s -o - | FileCheck %s +# RUN: llc -mtriple=riscv32 -mattr=+xqcilsm -run-pass=riscv-load-store-opt %s -o - | FileCheck %s --- | diff --git a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll index e0546a41779f7..399d6066c3366 100644 --- a/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll +++ b/llvm/test/CodeGen/RISCV/xqcilsm-memset.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32I -; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+experimental-xqcilsm < %s \ +; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+xqcilsm < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IXQCILSM %struct.anon = type { [16 x i32] } diff --git a/llvm/test/CodeGen/RISCV/xqcisls.ll b/llvm/test/CodeGen/RISCV/xqcisls.ll index 3dea540de4f4e..2ff21b44ad4c3 100644 --- a/llvm/test/CodeGen/RISCV/xqcisls.ll +++ b/llvm/test/CodeGen/RISCV/xqcisls.ll @@ -3,7 +3,7 @@ ; RUN: | FileCheck %s -check-prefixes=RV32I ; RUN: llc -mtriple=riscv32 --mattr=+zba -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IZBA -; RUN: llc -mtriple=riscv32 -mattr=+zba,+experimental-xqcisls -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+zba,+xqcisls -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV32IZBAXQCISLS define i32 @lb_ri(i8* %a, i32 %b) { diff --git a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll index 3916a205dd19c..20d28a07e77e6 100644 --- a/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll +++ b/llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll @@ -158,9 +158,9 @@ define dso_local noundef signext i32 @main() #2 !dbg !28 { ret i32 %6, !dbg !36 } -attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-experimental-xqcia,-experimental-xqciac,-experimental-xqcibi,-experimental-xqcibm,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqciio,-experimental-xqcilb,-experimental-xqcili,-experimental-xqcilia,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisim,-experimental-xqcisls,-experimental-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-experimental-xqcia,-experimental-xqciac,-experimental-xqcibi,-experimental-xqcibm,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqciio,-experimental-xqcilb,-experimental-xqcili,-experimental-xqcilia,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisim,-experimental-xqcisls,-experimental-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } -attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-experimental-xqcia,-experimental-xqciac,-experimental-xqcibi,-experimental-xqcibm,-experimental-xqcicli,-experimental-xqcicm,-experimental-xqcics,-experimental-xqcicsr,-experimental-xqciint,-experimental-xqciio,-experimental-xqcilb,-experimental-xqcili,-experimental-xqcilia,-experimental-xqcilo,-experimental-xqcilsm,-experimental-xqcisim,-experimental-xqcisls,-experimental-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #0 = { mustprogress noinline optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #1 = { mustprogress noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } +attributes #2 = { mustprogress noinline norecurse optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv64" "target-features"="+64bit,+a,+c,+d,+f,+i,+m,+relax,+zaamo,+zalrsc,+zca,+zcd,+zicsr,+zifencei,+zmmul,-b,-e,-experimental-p,-experimental-svukte,-experimental-xqccmp,-xqcia,-xqciac,-xqcibi,-xqcibm,-xqcicli,-xqcicm,-xqcics,-xqcicsr,-xqciint,-xqciio,-xqcilb,-xqcili,-xqcilia,-xqcilo,-xqcilsm,-xqcisim,-xqcisls,-xqcisync,-experimental-xrivosvisni,-experimental-xrivosvizip,-experimental-xsfmclic,-experimental-xsfsclic,-experimental-zalasr,-experimental-zibi,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvfbfa,-experimental-zvfofp8min,-experimental-zvkgs,-experimental-zvqdotq,-h,-q,-sdext,-sdtrig,-sha,-shcounterenw,-shgatpa,-shlcofideleg,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcntrpmf,-smcsrind,-smctr,-smdbltrp,-smepmp,-smmpm,-smnpm,-smrnmi,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssctr,-ssdbltrp,-ssnpm,-sspm,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-supm,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-svvptc,-v,-xandesbfhcvt,-xandesperf,-xandesvbfhcvt,-xandesvdot,-xandesvpackfph,-xandesvsinth,-xandesvsintload,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xmipscbop,-xmipscmov,-xmipsexectl,-xmipslsp,-xsfcease,-xsfmm128t,-xsfmm16t,-xsfmm32a16f,-xsfmm32a32f,-xsfmm32a8f,-xsfmm32a8i,-xsfmm32t,-xsfmm64a64f,-xsfmm64t,-xsfmmbase,-xsfvcp,-xsfvfbfexp16e,-xsfvfexp16e,-xsfvfexp32e,-xsfvfexpa,-xsfvfexpa64e,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xsmtvdot,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zabha,-zacas,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zce,-zcf,-zclsd,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccamoc,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zilsd,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!2, !3, !4, !5, !6, !8, !9} diff --git a/llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt b/llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt index fbbabe8bda832..e11a83a23eebe 100644 --- a/llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt +++ b/llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt @@ -1,8 +1,8 @@ # RUN: llvm-mc -assemble -triple riscv32 \ -# RUN: -mattr=+experimental-xqcilb,+experimental-xqcibi \ +# RUN: -mattr=+xqcilb,+xqcibi \ # RUN: %s -filetype=obj -o - \ # RUN: | llvm-objdump -d -M no-aliases - \ -# RUN: --mattr=+experimental-xqcilb,+experimental-xqcibi \ +# RUN: --mattr=+xqcilb,+xqcibi \ # RUN: | FileCheck %s .option exact diff --git a/llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt b/llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt index 46e6f34be2385..75821399bd107 100644 --- a/llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt +++ b/llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt @@ -1,6 +1,6 @@ -# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+experimental-xqciac %s \ +# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+xqciac %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-XQCIAC %s -# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+experimental-xqcibm %s \ +# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+xqcibm %s \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-XQCIBM %s [0x00,0x00] diff --git a/llvm/test/MC/RISCV/insn_xqci.s b/llvm/test/MC/RISCV/insn_xqci.s index 098745ec22294..90ac5c1c70aeb 100644 --- a/llvm/test/MC/RISCV/insn_xqci.s +++ b/llvm/test/MC/RISCV/insn_xqci.s @@ -1,7 +1,7 @@ # RUN: llvm-mc %s -triple=riscv32 -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM %s # RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilia,+experimental-xqcilo,+experimental-xqcibi,+experimental-xqcilb \ +# RUN: | llvm-objdump --mattr=+xqcilia,+xqcilo,+xqcibi,+xqcilb \ # RUN: -M no-aliases -d -r - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ %s diff --git a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s index b38aa373c90f0..8f525d86ab8ba 100644 --- a/llvm/test/MC/RISCV/rv32-relaxation-xqci.s +++ b/llvm/test/MC/RISCV/rv32-relaxation-xqci.s @@ -1,7 +1,7 @@ # RUN: split-file %s %t -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb %t/pass.s -o - \ -# RUN: | llvm-objdump -dr -M no-aliases - --mattr=+experimental-xqcilb | FileCheck %s -# RUN: not llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb %t/fail.s \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilb %t/pass.s -o - \ +# RUN: | llvm-objdump -dr -M no-aliases - --mattr=+xqcilb | FileCheck %s +# RUN: not llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilb %t/fail.s \ # RUN: 2>&1 | FileCheck %t/fail.s --check-prefix=ERROR ## This testcase shows how `c.j`, `c.jal` and `jal` can be relaxed to `qc.e.j` and `qc.e.jal` diff --git a/llvm/test/MC/RISCV/vendor-symbol.s b/llvm/test/MC/RISCV/vendor-symbol.s index 9595f218d78fa..9391694a8658b 100644 --- a/llvm/test/MC/RISCV/vendor-symbol.s +++ b/llvm/test/MC/RISCV/vendor-symbol.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcibi,+xandesperf %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcibi,+xandesperf %s \ # RUN: -filetype=obj -o - \ # RUN: | llvm-readelf -sr - \ # RUN: | FileCheck %s diff --git a/llvm/test/MC/RISCV/xqci-fixups.s b/llvm/test/MC/RISCV/xqci-fixups.s index 410126d9fd857..4690cf99ad1bf 100644 --- a/llvm/test/MC/RISCV/xqci-fixups.s +++ b/llvm/test/MC/RISCV/xqci-fixups.s @@ -1,10 +1,10 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ -# RUN: --mattr=+experimental-xqcili,+experimental-xqcilb,+experimental-xqcibi \ +# RUN: --mattr=+xqcili,+xqcilb,+xqcibi \ # RUN: -riscv-add-build-attributes \ # RUN: | llvm-objdump --no-print-imm-hex -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INSTR %s # RUN: llvm-mc -filetype=obj -triple=riscv32 %s \ -# RUN: --mattr=+experimental-xqcili,+experimental-xqcilb,+experimental-xqcibi \ +# RUN: --mattr=+xqcili,+xqcilb,+xqcibi \ # RUN: | llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL ## This checks that, if the assembler can resolve the qc fixup, that the fixup diff --git a/llvm/test/MC/RISCV/xqcia-invalid.s b/llvm/test/MC/RISCV/xqcia-invalid.s index 8c341c69e3198..5e679c1900acc 100644 --- a/llvm/test/MC/RISCV/xqcia-invalid.s +++ b/llvm/test/MC/RISCV/xqcia-invalid.s @@ -1,7 +1,7 @@ # Xqcia - Qualcomm uC Arithmetic Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcia < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcia < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcia < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcia < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcia-valid.s b/llvm/test/MC/RISCV/xqcia-valid.s index 18e2a7f29ccaa..7b6df3a10b011 100644 --- a/llvm/test/MC/RISCV/xqcia-valid.s +++ b/llvm/test/MC/RISCV/xqcia-valid.s @@ -1,13 +1,13 @@ # Xqcia - Qualcomm uC Arithmetic Extesnsion -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcia -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcia -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcia < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcia -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcia < %s \ +# RUN: | llvm-objdump --mattr=+xqcia -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcia -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcia -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcia < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcia --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcia < %s \ +# RUN: | llvm-objdump --mattr=+xqcia --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.shlsat a0, gp, a7 diff --git a/llvm/test/MC/RISCV/xqciac-invalid.s b/llvm/test/MC/RISCV/xqciac-invalid.s index d420bc17cb724..e4e16d3cf9152 100644 --- a/llvm/test/MC/RISCV/xqciac-invalid.s +++ b/llvm/test/MC/RISCV/xqciac-invalid.s @@ -1,7 +1,7 @@ # Xqciac - Qualcomm uC Load-Store Address Calculation Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqciac < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqciac < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciac < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqciac < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s # CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqciac-valid.s b/llvm/test/MC/RISCV/xqciac-valid.s index 02e63a0e7f12a..d38aa8b90fe5f 100644 --- a/llvm/test/MC/RISCV/xqciac-valid.s +++ b/llvm/test/MC/RISCV/xqciac-valid.s @@ -1,13 +1,13 @@ # Xqciac - Qualcomm uC Load-Store Address Calculation Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciac,+zba -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciac,+zba -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciac,+zba < %s \ +# RUN: | llvm-objdump --mattr=+xqciac,+zba -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciac,+zba -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciac,+zba --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciac,+zba < %s \ +# RUN: | llvm-objdump --mattr=+xqciac,+zba --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-NOALIAS: qc.c.muliadd a0, a1, 0 diff --git a/llvm/test/MC/RISCV/xqcibi-invalid.s b/llvm/test/MC/RISCV/xqcibi-invalid.s index bbc34dbe5bb65..78568c458dfe3 100644 --- a/llvm/test/MC/RISCV/xqcibi-invalid.s +++ b/llvm/test/MC/RISCV/xqcibi-invalid.s @@ -1,7 +1,7 @@ # Xqcibi - Qualcomm uC Branch Immediate Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcibi < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcibi < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcibi < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcibi < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s index 2066b55b41ad3..f7adedca60224 100644 --- a/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s +++ b/llvm/test/MC/RISCV/xqcibi-linker-relaxation.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+experimental-xqcilb,+experimental-xqcibi \ +# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+xqcilb,+xqcibi \ # RUN: %s -filetype=obj -o - -riscv-add-build-attributes \ # RUN: | llvm-objdump -dr -M no-aliases - \ # RUN: | FileCheck %s diff --git a/llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s b/llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s index 0279c81cea141..0eef04ddcc8f5 100644 --- a/llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s +++ b/llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -filetype=obj --mattr=+experimental-xqcibi -triple=riscv32 %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibi -d -M no-aliases - \ +# RUN: llvm-mc -filetype=obj --mattr=+xqcibi -triple=riscv32 %s \ +# RUN: | llvm-objdump --mattr=+xqcibi -d -M no-aliases - \ # RUN: | FileCheck --check-prefix=CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax,+experimental-xqcibi %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibi -dr -M no-aliases - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax,+xqcibi %s \ +# RUN: | llvm-objdump --mattr=+xqcibi -dr -M no-aliases - \ # RUN: | FileCheck --check-prefix=CHECK-INST-RELAX %s .text diff --git a/llvm/test/MC/RISCV/xqcibi-relocations.s b/llvm/test/MC/RISCV/xqcibi-relocations.s index 931cd7c9314bb..e3bbdc9013b44 100644 --- a/llvm/test/MC/RISCV/xqcibi-relocations.s +++ b/llvm/test/MC/RISCV/xqcibi-relocations.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcibi %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcibi %s \ # RUN: | FileCheck -check-prefix=ASM %s -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcibi %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcibi %s \ # RUN: -filetype=obj -o - \ -# RUN: | llvm-objdump -dr --mattr=+experimental-xqcibi - \ +# RUN: | llvm-objdump -dr --mattr=+xqcibi - \ # RUN: | FileCheck -check-prefix=OBJ %s ## This test checks that we emit the right relocations for Xqcibi diff --git a/llvm/test/MC/RISCV/xqcibi-valid.s b/llvm/test/MC/RISCV/xqcibi-valid.s index 88f7813d50915..97bab484c8a9c 100644 --- a/llvm/test/MC/RISCV/xqcibi-valid.s +++ b/llvm/test/MC/RISCV/xqcibi-valid.s @@ -1,13 +1,13 @@ # Xqcibi - Qualcomm uC Branch Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcibi -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibi < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibi -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcibi < %s \ +# RUN: | llvm-objdump --mattr=+xqcibi -M no-aliases -d - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibi -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcibi -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibi < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibi -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcibi < %s \ +# RUN: | llvm-objdump --mattr=+xqcibi -d - \ # RUN: | FileCheck -check-prefix=CHECK-OBJ %s # CHECK-INST: qc.beqi s0, 12, 346 diff --git a/llvm/test/MC/RISCV/xqcibm-invalid.s b/llvm/test/MC/RISCV/xqcibm-invalid.s index 6ed3ec4c7f65c..b6a74e7cf6c97 100644 --- a/llvm/test/MC/RISCV/xqcibm-invalid.s +++ b/llvm/test/MC/RISCV/xqcibm-invalid.s @@ -1,7 +1,7 @@ # Xqcibm - Qualcomm uC Bit Manipulation Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcibm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcibm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcibm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcibm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:18: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcibm-valid.s b/llvm/test/MC/RISCV/xqcibm-valid.s index 090b72834364b..69ae12fd881e5 100644 --- a/llvm/test/MC/RISCV/xqcibm-valid.s +++ b/llvm/test/MC/RISCV/xqcibm-valid.s @@ -1,14 +1,14 @@ # Xqcibm - Qualcomm uC Bit Manipulation Extension # Zbs is needed for checking compress instructions patterns for bexti/bseti -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm,+zbs -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcibm,+zbs -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm,+zbs < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibm,+zbs -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcibm,+zbs < %s \ +# RUN: | llvm-objdump --mattr=+xqcibm,+zbs -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcibm,+zbs -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcibm,+zbs -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcibm,+zbs < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcibm,+zbs --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcibm,+zbs < %s \ +# RUN: | llvm-objdump --mattr=+xqcibm,+zbs --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.compress2 t2, t0 diff --git a/llvm/test/MC/RISCV/xqcicli-invalid.s b/llvm/test/MC/RISCV/xqcicli-invalid.s index a2f5549a394f4..ff3309cb0555e 100644 --- a/llvm/test/MC/RISCV/xqcicli-invalid.s +++ b/llvm/test/MC/RISCV/xqcicli-invalid.s @@ -1,7 +1,7 @@ # Xqcicli - Qualcomm uC Conditional Load Immediate Instructions -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicli < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcicli < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicli < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcicli < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcicli-valid.s b/llvm/test/MC/RISCV/xqcicli-valid.s index 006151967bcf5..3241d11816717 100644 --- a/llvm/test/MC/RISCV/xqcicli-valid.s +++ b/llvm/test/MC/RISCV/xqcicli-valid.s @@ -1,13 +1,13 @@ # Xqcicli - Qualcomm uC Conditional Load Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicli -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicli < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicli -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicli < %s \ +# RUN: | llvm-objdump --mattr=+xqcicli -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicli -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicli -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicli < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicli --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicli < %s \ +# RUN: | llvm-objdump --mattr=+xqcicli --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.lieq sp, tp, t1, 10 diff --git a/llvm/test/MC/RISCV/xqcicm-invalid.s b/llvm/test/MC/RISCV/xqcicm-invalid.s index c1ee53fb21793..aaf4c8adebcf9 100644 --- a/llvm/test/MC/RISCV/xqcicm-invalid.s +++ b/llvm/test/MC/RISCV/xqcicm-invalid.s @@ -1,7 +1,7 @@ # Xqcicm - Qualcomm uC Conditional Move Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcicm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcicm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s # CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcicm-valid.s b/llvm/test/MC/RISCV/xqcicm-valid.s index a9ce30e150482..b57b0ce5693c0 100644 --- a/llvm/test/MC/RISCV/xqcicm-valid.s +++ b/llvm/test/MC/RISCV/xqcicm-valid.s @@ -1,13 +1,13 @@ # Xqcicm - Qualcomm uC Conditional Move Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicm -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicm -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicm < %s \ +# RUN: | llvm-objdump --mattr=+xqcicm -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicm -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicm -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicm --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicm < %s \ +# RUN: | llvm-objdump --mattr=+xqcicm --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-NOALIAS: qc.c.mveqz s1, a0 diff --git a/llvm/test/MC/RISCV/xqcics-invalid.s b/llvm/test/MC/RISCV/xqcics-invalid.s index e3eda3fcdc193..6d3a41a7fedc9 100644 --- a/llvm/test/MC/RISCV/xqcics-invalid.s +++ b/llvm/test/MC/RISCV/xqcics-invalid.s @@ -1,7 +1,7 @@ # Xqcics - Qualcomm uC Conditional Select Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcics < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcics < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcics < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcics < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s # CHECK-PLUS: :[[@LINE+2]]:14: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcics-valid.s b/llvm/test/MC/RISCV/xqcics-valid.s index 1438f67fd4b85..75d4c0baa9f56 100644 --- a/llvm/test/MC/RISCV/xqcics-valid.s +++ b/llvm/test/MC/RISCV/xqcics-valid.s @@ -1,13 +1,13 @@ # Xqcics - Qualcomm uC Conditional Select Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcics -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcics -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcics < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcics -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcics < %s \ +# RUN: | llvm-objdump --mattr=+xqcics -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcics -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcics -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcics < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcics --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcics < %s \ +# RUN: | llvm-objdump --mattr=+xqcics --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.selecteqi s1, 5, tp, gp diff --git a/llvm/test/MC/RISCV/xqcicsr-invalid.s b/llvm/test/MC/RISCV/xqcicsr-invalid.s index b4119dbf88272..986aad5fae756 100644 --- a/llvm/test/MC/RISCV/xqcicsr-invalid.s +++ b/llvm/test/MC/RISCV/xqcicsr-invalid.s @@ -1,7 +1,7 @@ # Xqcicsr - Qualcomm uC CSR Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcicsr < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcicsr < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcicsr < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcicsr < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:20: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcicsr-valid.s b/llvm/test/MC/RISCV/xqcicsr-valid.s index ab26098fc7ee7..3cae34aee471b 100644 --- a/llvm/test/MC/RISCV/xqcicsr-valid.s +++ b/llvm/test/MC/RISCV/xqcicsr-valid.s @@ -1,13 +1,13 @@ # Xqcicsr - Qualcomm uC CSR Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicsr -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicsr -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicsr < %s \ +# RUN: | llvm-objdump --mattr=+xqcicsr -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcicsr -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcicsr -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcicsr < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcicsr --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcicsr < %s \ +# RUN: | llvm-objdump --mattr=+xqcicsr --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.csrrwr a0, t0, s4 diff --git a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s index a313ba4d52380..5175b8c846ec6 100644 --- a/llvm/test/MC/RISCV/xqciint-csrs-invalid.s +++ b/llvm/test/MC/RISCV/xqciint-csrs-invalid.s @@ -1,190 +1,190 @@ # Xqciint - Qualcomm uC Custom CSRs -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqciint < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-FEATURE %s csrrs t2, qc.mmcr, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mmcr' requires 'xqciint' to be enabled csrrs t2, qc.mntvec, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mntvec' requires 'xqciint' to be enabled csrrs t2, qc.mstktopaddr, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstktopaddr' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstktopaddr' requires 'xqciint' to be enabled csrrs t2, qc.mstkbottomaddr, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstkbottomaddr' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mstkbottomaddr' requires 'xqciint' to be enabled csrrs t2, qc.mthreadptr, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mthreadptr' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mthreadptr' requires 'xqciint' to be enabled csrrs t2, qc.mcause, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mcause' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mcause' requires 'xqciint' to be enabled csrrs t2, qc.mclicip0, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip0' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip0' requires 'xqciint' to be enabled csrrs t2, qc.mclicip1, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip1' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip1' requires 'xqciint' to be enabled csrrs t2, qc.mclicip2, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip2' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip2' requires 'xqciint' to be enabled csrrs t2, qc.mclicip3, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip3' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip3' requires 'xqciint' to be enabled csrrs t2, qc.mclicip4, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip4' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip4' requires 'xqciint' to be enabled csrrs t2, qc.mclicip5, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip5' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip5' requires 'xqciint' to be enabled csrrs t2, qc.mclicip6, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip6' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip6' requires 'xqciint' to be enabled csrrs t2, qc.mclicip7, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip7' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicip7' requires 'xqciint' to be enabled csrrs t2, qc.mclicie0, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie0' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie0' requires 'xqciint' to be enabled csrrs t2, qc.mclicie1, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie1' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie1' requires 'xqciint' to be enabled csrrs t2, qc.mclicie2, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie2' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie2' requires 'xqciint' to be enabled csrrs t2, qc.mclicie3, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie3' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie3' requires 'xqciint' to be enabled csrrs t2, qc.mclicie4, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie4' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie4' requires 'xqciint' to be enabled csrrs t2, qc.mclicie5, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie5' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie5' requires 'xqciint' to be enabled csrrs t2, qc.mclicie6, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie6' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie6' requires 'xqciint' to be enabled csrrs t2, qc.mclicie7, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie7' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicie7' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl00, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl00' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl00' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl01, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl01' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl01' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl02, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl02' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl02' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl03, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl03' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl03' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl04, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl04' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl04' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl05, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl05' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl05' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl06, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl06' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl06' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl07, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl07' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl07' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl08, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl08' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl08' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl09, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl09' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl09' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl10, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl10' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl10' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl11, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl11' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl11' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl12, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl12' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl12' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl13, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl13' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl13' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl14, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl14' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl14' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl15, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl15' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl15' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl16, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl16' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl16' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl17, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl17' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl17' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl18, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl18' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl18' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl19, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl19' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl19' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl20, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl20' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl20' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl21, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl21' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl21' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl22, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl22' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl22' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl23, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl23' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl23' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl24, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl24' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl24' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl25, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl25' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl25' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl26, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl26' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl26' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl27, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl27' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl27' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl28, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl28' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl28' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl29, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl29' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl29' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl30, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl30' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl30' requires 'xqciint' to be enabled csrrs t2, qc.mclicilvl31, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl31' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mclicilvl31' requires 'xqciint' to be enabled csrrs t2, qc.mwpstartaddr0, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr0' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr0' requires 'xqciint' to be enabled csrrs t2, qc.mwpstartaddr1, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr1' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr1' requires 'xqciint' to be enabled csrrs t2, qc.mwpstartaddr2, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr2' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr2' requires 'xqciint' to be enabled csrrs t2, qc.mwpstartaddr3, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr3' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpstartaddr3' requires 'xqciint' to be enabled csrrs t2, qc.mwpendaddr0, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr0' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr0' requires 'xqciint' to be enabled csrrs t2, qc.mwpendaddr1, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr1' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr1' requires 'xqciint' to be enabled csrrs t2, qc.mwpendaddr2, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr2' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr2' requires 'xqciint' to be enabled csrrs t2, qc.mwpendaddr3, zero -// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr3' requires 'experimental-xqciint' to be enabled +// CHECK-FEATURE: :[[@LINE-1]]:11: error: system register 'qc.mwpendaddr3' requires 'xqciint' to be enabled diff --git a/llvm/test/MC/RISCV/xqciint-csrs-valid.s b/llvm/test/MC/RISCV/xqciint-csrs-valid.s index e09dff39cce18..d8376ff973e87 100644 --- a/llvm/test/MC/RISCV/xqciint-csrs-valid.s +++ b/llvm/test/MC/RISCV/xqciint-csrs-valid.s @@ -1,8 +1,8 @@ # Xqciint - Qualcomm uC Custom CSRs -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciint -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciint -M no-aliases -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciint < %s \ +# RUN: | llvm-objdump --mattr=+xqciint -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s csrrs t2, qc.mmcr, zero diff --git a/llvm/test/MC/RISCV/xqciint-invalid.s b/llvm/test/MC/RISCV/xqciint-invalid.s index 4a94551d1d62f..8aeeec3e85214 100644 --- a/llvm/test/MC/RISCV/xqciint-invalid.s +++ b/llvm/test/MC/RISCV/xqciint-invalid.s @@ -1,7 +1,7 @@ # Xqciint - Qualcomm uC Interrupts extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqciint < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqciint < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciint < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqciint < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:12: error: immediate must be an integer in the range [0, 1023] diff --git a/llvm/test/MC/RISCV/xqciint-valid.s b/llvm/test/MC/RISCV/xqciint-valid.s index 39812ab4d2ab4..4c7d73acaccb4 100644 --- a/llvm/test/MC/RISCV/xqciint-valid.s +++ b/llvm/test/MC/RISCV/xqciint-valid.s @@ -1,13 +1,13 @@ # Xqciint - Qualcomm uC Interrupts extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciint -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciint -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciint < %s \ +# RUN: | llvm-objdump --mattr=+xqciint -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciint -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciint -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciint < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciint --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciint < %s \ +# RUN: | llvm-objdump --mattr=+xqciint --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.setinti 500 diff --git a/llvm/test/MC/RISCV/xqciio-aliases-valid.s b/llvm/test/MC/RISCV/xqciio-aliases-valid.s index 4738edb1f7ec7..85434c9cee483 100644 --- a/llvm/test/MC/RISCV/xqciio-aliases-valid.s +++ b/llvm/test/MC/RISCV/xqciio-aliases-valid.s @@ -1,13 +1,13 @@ # Xqciio - Qualcomm uC External Input Output extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciio -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciio -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciio < %s \ +# RUN: | llvm-objdump --mattr=+xqciio -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciio -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciio --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciio < %s \ +# RUN: | llvm-objdump --mattr=+xqciio --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.outw t0, 0(a0) diff --git a/llvm/test/MC/RISCV/xqciio-invalid.s b/llvm/test/MC/RISCV/xqciio-invalid.s index f37e58023c7e1..55f60e44a07ed 100644 --- a/llvm/test/MC/RISCV/xqciio-invalid.s +++ b/llvm/test/MC/RISCV/xqciio-invalid.s @@ -1,7 +1,7 @@ # Xqciio - Qualcomm uC External Input Output Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqciio < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqciio < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqciio < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqciio < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK: :[[@LINE+1]]:18: error: expected register diff --git a/llvm/test/MC/RISCV/xqciio-valid.s b/llvm/test/MC/RISCV/xqciio-valid.s index 516f6219d0907..3d6ecf2560a87 100644 --- a/llvm/test/MC/RISCV/xqciio-valid.s +++ b/llvm/test/MC/RISCV/xqciio-valid.s @@ -1,13 +1,13 @@ # Xqciio - Qualcomm uC External Input Output Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciio -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciio -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciio < %s \ +# RUN: | llvm-objdump --mattr=+xqciio -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciio -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqciio -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciio < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqciio --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqciio < %s \ +# RUN: | llvm-objdump --mattr=+xqciio --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s diff --git a/llvm/test/MC/RISCV/xqcilb-invalid.s b/llvm/test/MC/RISCV/xqcilb-invalid.s index 1c584da890dd3..b7428e679f5bd 100644 --- a/llvm/test/MC/RISCV/xqcilb-invalid.s +++ b/llvm/test/MC/RISCV/xqcilb-invalid.s @@ -1,7 +1,7 @@ # Xqcilb - Qualcomm uC Long Branch Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilb < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcilb < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilb < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilb < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK: :[[@LINE+1]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcilb-relocations.s b/llvm/test/MC/RISCV/xqcilb-relocations.s index 48c8c6931c8af..b31e4822c9549 100644 --- a/llvm/test/MC/RISCV/xqcilb-relocations.s +++ b/llvm/test/MC/RISCV/xqcilb-relocations.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcilb %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcilb %s \ # RUN: | FileCheck -check-prefix=ASM %s -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcilb %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcilb %s \ # RUN: -filetype=obj -o - \ -# RUN: | llvm-objdump -dr --mattr=+experimental-xqcilb - \ +# RUN: | llvm-objdump -dr --mattr=+xqcilb - \ # RUN: | FileCheck -check-prefix=OBJ %s ## This test checks that we emit the right relocations for Xqcilb diff --git a/llvm/test/MC/RISCV/xqcilb-valid.s b/llvm/test/MC/RISCV/xqcilb-valid.s index 3d5b3891ddff6..b434cec0edb59 100644 --- a/llvm/test/MC/RISCV/xqcilb-valid.s +++ b/llvm/test/MC/RISCV/xqcilb-valid.s @@ -1,13 +1,13 @@ # Xqcilb - Qualcomm uC Long Branch Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilb -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilb -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilb < %s \ +# RUN: | llvm-objdump --mattr=+xqcilb -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilb -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilb -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilb < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilb --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilb < %s \ +# RUN: | llvm-objdump --mattr=+xqcilb --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ-ALIAS %s # CHECK-INST: qc.e.j -2147483648 diff --git a/llvm/test/MC/RISCV/xqcili-invalid.s b/llvm/test/MC/RISCV/xqcili-invalid.s index 567ed8ba89736..d4ad16398ed5a 100644 --- a/llvm/test/MC/RISCV/xqcili-invalid.s +++ b/llvm/test/MC/RISCV/xqcili-invalid.s @@ -1,7 +1,7 @@ # Xqcili - Qualcomm uC Load Large Immediate Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcili < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcili < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcili < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcili < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS,CHECK-EXT %s # CHECK-PLUS: :[[@LINE+2]]:9: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcili-li.s b/llvm/test/MC/RISCV/xqcili-li.s index 7f684095cc02e..023efae7a9ff8 100644 --- a/llvm/test/MC/RISCV/xqcili-li.s +++ b/llvm/test/MC/RISCV/xqcili-li.s @@ -1,5 +1,5 @@ # Xqcili - Check aliases for li instruction -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -M no-aliases \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcili -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-INST %s # RUN: llvm-mc %s -triple=riscv32 -M no-aliases \ # RUN: | FileCheck -check-prefixes=CHECK-INST-RISCV32 %s diff --git a/llvm/test/MC/RISCV/xqcili-linker-relaxation.s b/llvm/test/MC/RISCV/xqcili-linker-relaxation.s index ace677979ee13..f133d05fdcb2b 100644 --- a/llvm/test/MC/RISCV/xqcili-linker-relaxation.s +++ b/llvm/test/MC/RISCV/xqcili-linker-relaxation.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+experimental-xqcili \ +# RUN: llvm-mc --triple=riscv32 -mattr=+relax,+xqcili \ # RUN: %s -filetype=obj -o - -riscv-add-build-attributes \ # RUN: | llvm-objdump -dr -M no-aliases - \ # RUN: | FileCheck %s diff --git a/llvm/test/MC/RISCV/xqcili-relocations.s b/llvm/test/MC/RISCV/xqcili-relocations.s index 7eff61fc782d8..03c08fb140c13 100644 --- a/llvm/test/MC/RISCV/xqcili-relocations.s +++ b/llvm/test/MC/RISCV/xqcili-relocations.s @@ -1,8 +1,8 @@ -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcili %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcili %s \ # RUN: | FileCheck -check-prefix=ASM %s -# RUN: llvm-mc -triple riscv32 -mattr=+experimental-xqcili %s \ +# RUN: llvm-mc -triple riscv32 -mattr=+xqcili %s \ # RUN: -filetype=obj -o - \ -# RUN: | llvm-objdump -dr --mattr=+experimental-xqcili - \ +# RUN: | llvm-objdump -dr --mattr=+xqcili - \ # RUN: | FileCheck -check-prefix=OBJ %s ## This test checks that we emit the right relocations for Xqcili diff --git a/llvm/test/MC/RISCV/xqcili-valid.s b/llvm/test/MC/RISCV/xqcili-valid.s index 8e9c164de662c..398493c109944 100644 --- a/llvm/test/MC/RISCV/xqcili-valid.s +++ b/llvm/test/MC/RISCV/xqcili-valid.s @@ -1,16 +1,16 @@ # Xqcili - Qualcomm uC Load Large Immediate Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcili -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcili < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcili -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcili < %s \ +# RUN: | llvm-objdump --mattr=+xqcili -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcili -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcili -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcili < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcili --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcili < %s \ +# RUN: | llvm-objdump --mattr=+xqcili --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s diff --git a/llvm/test/MC/RISCV/xqcilia-invalid.s b/llvm/test/MC/RISCV/xqcilia-invalid.s index 50b56bc0db41d..517eb5ea48224 100644 --- a/llvm/test/MC/RISCV/xqcilia-invalid.s +++ b/llvm/test/MC/RISCV/xqcilia-invalid.s @@ -1,7 +1,7 @@ # Xqcilia - Qualcomm uC Large Immediate Arithmetic extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilia < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcilia < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilia < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilia < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS,CHECK-EXT %s # CHECK-PLUS: :[[@LINE+2]]:12: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcilia-valid.s b/llvm/test/MC/RISCV/xqcilia-valid.s index 2396271d7db69..60525fc5a0129 100644 --- a/llvm/test/MC/RISCV/xqcilia-valid.s +++ b/llvm/test/MC/RISCV/xqcilia-valid.s @@ -1,13 +1,13 @@ # Xqcilia - Qualcomm uC Large Immediate Arithmetic extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilia -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilia -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilia < %s \ +# RUN: | llvm-objdump --mattr=+xqcilia -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilia -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilia -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilia < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilia --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilia < %s \ +# RUN: | llvm-objdump --mattr=+xqcilia --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s .option exact diff --git a/llvm/test/MC/RISCV/xqcilo-aliases-valid.s b/llvm/test/MC/RISCV/xqcilo-aliases-valid.s index 9c62acdb821dd..d23bccfe0546a 100644 --- a/llvm/test/MC/RISCV/xqcilo-aliases-valid.s +++ b/llvm/test/MC/RISCV/xqcilo-aliases-valid.s @@ -1,13 +1,13 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilo -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+xqcilo -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilo -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilo --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+xqcilo --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: lb a1, 0(a0) diff --git a/llvm/test/MC/RISCV/xqcilo-invalid.s b/llvm/test/MC/RISCV/xqcilo-invalid.s index c298f94ece759..c40af77383dbe 100644 --- a/llvm/test/MC/RISCV/xqcilo-invalid.s +++ b/llvm/test/MC/RISCV/xqcilo-invalid.s @@ -1,7 +1,7 @@ # Xqcilo - Qualcomm uC Extension Large Offset Load Store extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilo < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcilo < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-IMM %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilo < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilo < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-EXT %s # CHECK: :[[@LINE+1]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s index b6da8e487152c..6efc5a23345bc 100644 --- a/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s +++ b/llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s @@ -1,7 +1,7 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: not llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo \ +# RUN: not llvm-mc %s -triple=riscv32 -mattr=+xqcilo \ # RUN: 2>&1 | FileCheck -check-prefixes=CHECK-ENABLED %s -# RUN: not llvm-mc %s -triple=riscv32 -mattr=-experimental-xqcilo \ +# RUN: not llvm-mc %s -triple=riscv32 -mattr=-xqcilo \ # RUN: 2>&1 | FileCheck -check-prefixes=CHECK-DISABLED %s # CHECK-ENABLED: [[@LINE+2]]:1: error: too few operands for instruction diff --git a/llvm/test/MC/RISCV/xqcilo-pseudos-valid.s b/llvm/test/MC/RISCV/xqcilo-pseudos-valid.s index b8fc33dc9deb3..2330564351f15 100644 --- a/llvm/test/MC/RISCV/xqcilo-pseudos-valid.s +++ b/llvm/test/MC/RISCV/xqcilo-pseudos-valid.s @@ -1,5 +1,5 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilo \ # RUN: | FileCheck -check-prefixes=CHECK %s # CHECK-LABEL: .Lpcrel_hi0 diff --git a/llvm/test/MC/RISCV/xqcilo-valid.s b/llvm/test/MC/RISCV/xqcilo-valid.s index 1c26c06a870fc..574243ab79f39 100644 --- a/llvm/test/MC/RISCV/xqcilo-valid.s +++ b/llvm/test/MC/RISCV/xqcilo-valid.s @@ -1,24 +1,24 @@ # Xqcilo - Qualcomm uC Large Offset Load Store extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilo -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+xqcilo -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilo -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilo -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilo --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+xqcilo --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcb,+experimental-xqcilo -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcb,+xqcilo -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC-ZCB,CHECK-INST-ZCB,CHECK-NOALIAS-ZCB %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcb,+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+zcb,+experimental-xqcilo -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcb,+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+zcb,+xqcilo -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ZCB %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcb,+experimental-xqcilo -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+zcb,+xqcilo -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC-ZCB,CHECK-INST-ZCB,CHECK-ALIAS-ZCB %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcb,+experimental-xqcilo < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilo --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zcb,+xqcilo < %s \ +# RUN: | llvm-objdump --mattr=+xqcilo --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ZCB %s # CHECK-INST: qc.e.lb a1, 3000(a0) diff --git a/llvm/test/MC/RISCV/xqcilsm-aliases-valid.s b/llvm/test/MC/RISCV/xqcilsm-aliases-valid.s index b65a831a5f4d3..c15224061393d 100644 --- a/llvm/test/MC/RISCV/xqcilsm-aliases-valid.s +++ b/llvm/test/MC/RISCV/xqcilsm-aliases-valid.s @@ -1,13 +1,13 @@ # Xqcilsm - Qualcomm uC Load Store Multiple Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilsm -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilsm -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilsm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilsm -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilsm < %s \ +# RUN: | llvm-objdump --mattr=+xqcilsm -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilsm -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilsm -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilsm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilsm --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilsm < %s \ +# RUN: | llvm-objdump --mattr=+xqcilsm --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.swm t0, s4, 0(gp) diff --git a/llvm/test/MC/RISCV/xqcilsm-invalid.s b/llvm/test/MC/RISCV/xqcilsm-invalid.s index a3421db0eff4f..8a8792a9cee35 100644 --- a/llvm/test/MC/RISCV/xqcilsm-invalid.s +++ b/llvm/test/MC/RISCV/xqcilsm-invalid.s @@ -1,7 +1,7 @@ # Xqcilsm - Qualcomm uC Load Store Multiple Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcilsm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcilsm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcilsm < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcilsm < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK: :[[@LINE+1]]:20: error: expected register diff --git a/llvm/test/MC/RISCV/xqcilsm-valid.s b/llvm/test/MC/RISCV/xqcilsm-valid.s index cbe25a269d19b..eb50d2bcd3dbd 100644 --- a/llvm/test/MC/RISCV/xqcilsm-valid.s +++ b/llvm/test/MC/RISCV/xqcilsm-valid.s @@ -1,13 +1,13 @@ # Xqcilsm - Qualcomm uC Load Store Multiple Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilsm -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilsm -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilsm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilsm -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilsm < %s \ +# RUN: | llvm-objdump --mattr=+xqcilsm -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcilsm -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcilsm -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcilsm < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcilsm --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcilsm < %s \ +# RUN: | llvm-objdump --mattr=+xqcilsm --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.swm t0, s4, 12(gp) diff --git a/llvm/test/MC/RISCV/xqcisim-invalid.s b/llvm/test/MC/RISCV/xqcisim-invalid.s index c8fe925b623f6..0e740a5984538 100644 --- a/llvm/test/MC/RISCV/xqcisim-invalid.s +++ b/llvm/test/MC/RISCV/xqcisim-invalid.s @@ -1,7 +1,7 @@ # Xqcisim - Simulaton Hint Instructions -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisim < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcisim < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisim < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcisim < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+1]]:14: error: immediate must be an integer in the range [0, 1023] diff --git a/llvm/test/MC/RISCV/xqcisim-valid.s b/llvm/test/MC/RISCV/xqcisim-valid.s index ed8e1df0807ca..5927ec6d9733d 100644 --- a/llvm/test/MC/RISCV/xqcisim-valid.s +++ b/llvm/test/MC/RISCV/xqcisim-valid.s @@ -1,13 +1,13 @@ # Xqcisim - Simulation Hint Instructions -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisim -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisim -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisim < %s \ +# RUN: | llvm-objdump --mattr=+xqcisim -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisim -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisim -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisim < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisim --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisim < %s \ +# RUN: | llvm-objdump --mattr=+xqcisim --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s diff --git a/llvm/test/MC/RISCV/xqcisls-invalid.s b/llvm/test/MC/RISCV/xqcisls-invalid.s index 58a0f8ceaab35..4553168405230 100644 --- a/llvm/test/MC/RISCV/xqcisls-invalid.s +++ b/llvm/test/MC/RISCV/xqcisls-invalid.s @@ -1,7 +1,7 @@ # Xqcisls - Qualcomm uC Scaled Load Store Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisls < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcisls < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisls < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcisls < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+2]]:16: error: register must be a GPR excluding zero (x0) diff --git a/llvm/test/MC/RISCV/xqcisls-valid.s b/llvm/test/MC/RISCV/xqcisls-valid.s index d7e80b313c78f..b130c8ad4e067 100644 --- a/llvm/test/MC/RISCV/xqcisls-valid.s +++ b/llvm/test/MC/RISCV/xqcisls-valid.s @@ -1,13 +1,13 @@ # Xqcisls - Qualcomm uC Scaled Load Store Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisls -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisls -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisls < %s \ +# RUN: | llvm-objdump --mattr=+xqcisls -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisls -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisls -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisls < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisls --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisls < %s \ +# RUN: | llvm-objdump --mattr=+xqcisls --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s # CHECK-INST: qc.lrb t0, sp, tp, 4 diff --git a/llvm/test/MC/RISCV/xqcisync-invalid.s b/llvm/test/MC/RISCV/xqcisync-invalid.s index 6c945c9e5cfb0..7f037e01d62ab 100644 --- a/llvm/test/MC/RISCV/xqcisync-invalid.s +++ b/llvm/test/MC/RISCV/xqcisync-invalid.s @@ -1,7 +1,7 @@ # Xqcisync - Qualcomm uC Sync Delay Extension -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-xqcisync < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=+xqcisync < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-PLUS %s -# RUN: not llvm-mc -triple riscv32 -mattr=-experimental-xqcisync < %s 2>&1 \ +# RUN: not llvm-mc -triple riscv32 -mattr=-xqcisync < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK,CHECK-MINUS %s # CHECK-PLUS: :[[@LINE+1]]:12: error: immediate must be an integer in the range [1, 31] diff --git a/llvm/test/MC/RISCV/xqcisync-valid.s b/llvm/test/MC/RISCV/xqcisync-valid.s index 5b4c5061527c2..597b9c67facdf 100644 --- a/llvm/test/MC/RISCV/xqcisync-valid.s +++ b/llvm/test/MC/RISCV/xqcisync-valid.s @@ -1,13 +1,13 @@ # Xqcisync - Qualcomm uC Sync Delay Extension -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -M no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisync -M no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisync -M no-aliases --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisync < %s \ +# RUN: | llvm-objdump --mattr=+xqcisync -M no-aliases --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-NOALIAS %s -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqcisync -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+xqcisync -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s -# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqcisync < %s \ -# RUN: | llvm-objdump --mattr=+experimental-xqcisync --no-print-imm-hex -d - \ +# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+xqcisync < %s \ +# RUN: | llvm-objdump --mattr=+xqcisync --no-print-imm-hex -d - \ # RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ALIAS %s # CHECK-NOALIAS: c.slli zero, 10 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index a2ac67724152b..2d0a3104f416d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1245,6 +1245,25 @@ R"(All available -march extensions for RISC-V xmipscmov 1.0 xmipsexectl 1.0 xmipslsp 1.0 + xqci 0.13 + xqcia 0.7 + xqciac 0.3 + xqcibi 0.2 + xqcibm 0.8 + xqcicli 0.3 + xqcicm 0.2 + xqcics 0.2 + xqcicsr 0.4 + xqciint 0.10 + xqciio 0.1 + xqcilb 0.2 + xqcili 0.2 + xqcilia 0.2 + xqcilo 0.3 + xqcilsm 0.6 + xqcisim 0.2 + xqcisls 0.2 + xqcisync 0.3 xsfcease 1.0 xsfmm128t 0.6 xsfmm16t 0.6 @@ -1297,25 +1316,6 @@ Experimental extensions smpmpmt 0.6 svukte 0.3 xqccmp 0.3 - xqci 0.13 - xqcia 0.7 - xqciac 0.3 - xqcibi 0.2 - xqcibm 0.8 - xqcicli 0.3 - xqcicm 0.2 - xqcics 0.2 - xqcicsr 0.4 - xqciint 0.10 - xqciio 0.1 - xqcilb 0.2 - xqcili 0.2 - xqcilia 0.2 - xqcilo 0.3 - xqcilsm 0.6 - xqcisim 0.2 - xqcisls 0.2 - xqcisync 0.3 xrivosvisni 0.1 xrivosvizip 0.1 xsfmclic 0.1