serial: fix issue where data latched can be invalid

Author: HarryMakes

nmigen_stdio/serial.py

@@ -182,13 +182,21 @@ def elaborate(self, platform):
                     m.d.sync += [
                         self.o.eq(0),       # Issue start bit ASAP
                         shreg.start .eq(0),
-                        shreg.data  .eq(self.data),
                         shreg.parity.eq(_compute_parity_bit(self.data, self._parity)),
                         shreg.stop  .eq(1),
                         bits_left.eq(len(self.shreg)),
                         timer.eq(self.divisor)
                     ]
-                    m.next = "BUSY"
+                    m.next = "LATCH-DATA"
+
+            with m.State("LATCH-DATA"):
+                # Since the data is valid only when ACK is high,
+                # only latch the data now such that it is from the first clock since ACK is high
+                m.d.sync += [
+                    shreg.data.eq(self.data),
+                    timer.eq(timer - 1)
+                ]
+                m.next = "BUSY"
 
             with m.State("BUSY"):
                 with m.If(timer != 0):
@@ -216,13 +224,12 @@ def elaborate(self, platform):
                     m.d.sync += [
                         self.o.eq(0),       # Issue start bit ASAP
                         shreg.start .eq(0),
-                        shreg.data  .eq(self.data),
                         shreg.parity.eq(_compute_parity_bit(self.data, self._parity)),
                         shreg.stop  .eq(1),
                         bits_left.eq(len(self.shreg)),
                         timer.eq(self.divisor)
                     ]
-                    m.next = "BUSY"
+                    m.next = "LATCH-DATA"
                 # Set back to IDLE if ACK is low
                 with m.Else():
                     m.d.sync += self.o.eq(1)