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| 1 | +// |
| 2 | +// USB Power Delivery for Arduino |
| 3 | +// Copyright (c) 2023 Manuel Bleichenbacher |
| 4 | +// |
| 5 | +// Licensed under MIT License |
| 6 | +// https://opensource.org/licenses/MIT |
| 7 | +// |
| 8 | + |
| 9 | +#pragma once |
| 10 | + |
| 11 | +#if defined(STM32F103xB) |
| 12 | +#include "stm32f103xb.h" |
| 13 | +#elif defined(STM32F401xC) |
| 14 | +#include "stm32f401xc.h" |
| 15 | +#elif defined(STM32L4xx) |
| 16 | +#include "stm32l4xx.h" |
| 17 | +#elif defined(STM32G431xx) |
| 18 | +#include "stm32g431xx.h" |
| 19 | +#else |
| 20 | +#pragma GCC error "This board is not supported by usb-pd-arduino. Supported boards: STM32F103xB (aka Bluepill), STM32F401xC (aka Blackpill), STM32L4 family, STM32G431" |
| 21 | +#endif |
| 22 | + |
| 23 | +// --- Register manipulation --- |
| 24 | + |
| 25 | +/** |
| 26 | + * @brief Sets bits of a register |
| 27 | + * |
| 28 | + * @param reg register |
| 29 | + * @param value values to set (must be masked to the relevant bits) |
| 30 | + * @param mask mask of bits to change |
| 31 | + */ |
| 32 | +static inline void setRegBits(volatile uint32_t& reg, uint32_t value, uint32_t mask) { |
| 33 | + reg = (reg & (~mask)) | (value & mask); |
| 34 | +} |
| 35 | + |
| 36 | +/** |
| 37 | + * @brief Clears bits of a register |
| 38 | + * |
| 39 | + * @param reg register |
| 40 | + * @param mask mask of bits to clear |
| 41 | + */ |
| 42 | +static inline void clearRegBits(volatile uint32_t& reg, uint32_t mask) { |
| 43 | + reg = reg & ~mask; |
| 44 | +} |
| 45 | + |
| 46 | + |
| 47 | +#if defined(STM32L4) || defined(STM32F4xx) |
| 48 | + |
| 49 | +// --- GPIO --- |
| 50 | + |
| 51 | +// Helpers to build bits and masks for GPIO registers |
| 52 | +static constexpr uint32_t GPIO_MODER_INPUT(uint8_t gpio) { return 0b00 << (gpio * 2); } |
| 53 | +static constexpr uint32_t GPIO_MODER_OUTPUT(uint8_t gpio) { return 0b01 << (gpio * 2); } |
| 54 | +static constexpr uint32_t GPIO_MODER_ALTERNATE(uint8_t gpio) { return 0b10 << (gpio * 2); } |
| 55 | +static constexpr uint32_t GPIO_MODER_ANALOG(uint8_t gpio) { return 0b11 << (gpio * 2); } |
| 56 | +static constexpr uint32_t GPIO_MODER_Msk(uint8_t gpio) { return 0b11 << (gpio * 2); } |
| 57 | +static constexpr uint32_t GPIO_OTYPER_PUSH_PULL(uint8_t gpio) { return 0 << gpio; } |
| 58 | +static constexpr uint32_t GPIO_OTYPER_OPEN_DRAIN(uint8_t gpio) { return 1 << gpio; } |
| 59 | +static constexpr uint32_t GPIO_OTYPER_Msk(uint8_t gpio) { return 1 << gpio; } |
| 60 | +static constexpr uint32_t GPIO_OSPEEDR_LOW(uint8_t gpio) { return 0b00 << (gpio * 2); } |
| 61 | +static constexpr uint32_t GPIO_OSPEEDR_MEDIUM(uint8_t gpio) { return 0b01 << (gpio * 2); } |
| 62 | +static constexpr uint32_t GPIO_OSPEEDR_HIGH(uint8_t gpio) { return 0b10 << (gpio * 2); } |
| 63 | +static constexpr uint32_t GPIO_OSPEEDR_VERY_HIGH(uint8_t gpio) { return 0b11 << (gpio * 2); } |
| 64 | +static constexpr uint32_t GPIO_OSPEEDR_Msk(uint8_t gpio) { return 0b11 << (gpio * 2); } |
| 65 | +static constexpr uint32_t GPIO_PUPDR_NONE(uint8_t gpio) { return 0b00 << (gpio * 2); } |
| 66 | +static constexpr uint32_t GPIO_PUPDR_PULL_UP(uint8_t gpio) { return 0b01 << (gpio * 2); } |
| 67 | +static constexpr uint32_t GPIO_PUPDR_PULL_DOWN(uint8_t gpio) { return 0b10 << (gpio * 2); } |
| 68 | +static constexpr uint32_t GPIO_PUPDR_Msk(uint8_t gpio) { return 0b11 << (gpio * 2); } |
| 69 | +static constexpr uint32_t GPIO_AFRL(uint8_t gpio, uint8_t af) { return af << (gpio * 4); } |
| 70 | +static constexpr uint32_t GPIO_AFRL_Msk(uint8_t gpio) { return 0b1111 << (gpio * 4); } |
| 71 | +static constexpr uint32_t GPIO_AFRH(uint8_t gpio, uint8_t af) { return af << ((gpio - 8) * 4); } |
| 72 | +static constexpr uint32_t GPIO_AFRH_Msk(uint8_t gpio) { return 0b1111 << ((gpio - 8) * 4); } |
| 73 | +static inline void gpioSetOutputHigh(GPIO_TypeDef* port, uint8_t gpio) { port->BSRR = 1 << gpio; } |
| 74 | +static inline void gpioSetOutputLow(GPIO_TypeDef* port, uint8_t gpio) { port->BSRR = 1 << (16 + gpio); } |
| 75 | + |
| 76 | +#endif |
| 77 | + |
| 78 | + |
| 79 | +// --- EXTI --- |
| 80 | + |
| 81 | +#if defined(STM32L4) |
| 82 | + |
| 83 | +// Additional EXTI constants |
| 84 | +static constexpr uint8_t EXTI_COMP1_Pos = 21; |
| 85 | +static constexpr uint32_t EXTI_COMP1 = 1 << EXTI_COMP1_Pos; |
| 86 | +static constexpr uint32_t EXTI_COMP1_Msk = 1 << EXTI_COMP1_Pos; |
| 87 | +static constexpr uint8_t EXTI_COMP2_Pos = 22; |
| 88 | +static constexpr uint32_t EXTI_COMP2 = 1 << EXTI_COMP2_Pos; |
| 89 | +static constexpr uint32_t EXTI_COMP2_Msk = 1 << EXTI_COMP2_Pos; |
| 90 | + |
| 91 | +#endif |
| 92 | + |
| 93 | +#if defined(STM32F103xB) |
| 94 | + |
| 95 | +// --- GPIO --- |
| 96 | + |
| 97 | +// Helpers to build bits and masks for GPIO registers |
| 98 | +static constexpr uint32_t GPIO_CRL_MODE_INPUT(uint8_t gpio) { return 0b00 << (gpio * 4); } |
| 99 | +static constexpr uint32_t GPIO_CRL_MODE_OUTPUT_10MHZ(uint8_t gpio) { return 0b01 << (gpio * 4); } |
| 100 | +static constexpr uint32_t GPIO_CRL_MODE_OUTPUT_2MHZ(uint8_t gpio) { return 0b10 << (gpio * 4); } |
| 101 | +static constexpr uint32_t GPIO_CRL_MODE_OUTPUT_50MHZ(uint8_t gpio) { return 0b11 << (gpio * 4); } |
| 102 | +static constexpr uint32_t GPIO_CRL_MODE_MASK(uint8_t gpio) { return 0b11 << (gpio * 4); } |
| 103 | +static constexpr uint32_t GPIO_CRL_CNF_ANALOG(uint8_t gpio) { return 0b00 << ((gpio * 4) + 2); } |
| 104 | +static constexpr uint32_t GPIO_CRL_CNF_FLOATING(uint8_t gpio) { return 0b01 << ((gpio * 4) + 2); } |
| 105 | +static constexpr uint32_t GPIO_CRL_CNF_INPUT_PUPD(uint8_t gpio) { return 0b10 << ((gpio * 4) + 2); } |
| 106 | +static constexpr uint32_t GPIO_CRL_CNF_OUTPUT(uint8_t gpio) { return 0b00 << ((gpio * 4) + 2); } |
| 107 | +static constexpr uint32_t GPIO_CRL_CNF_OUTPUT_OPENDRAIN(uint8_t gpio) { return 0b01 << ((gpio * 4) + 2); } |
| 108 | +static constexpr uint32_t GPIO_CRL_CNF_ALTERNATE(uint8_t gpio) { return 0b10 << ((gpio * 4) + 2); } |
| 109 | +static constexpr uint32_t GPIO_CRL_CNF_ALTERNATE_OPENDRAIN(uint8_t gpio) { return 0b11 << ((gpio * 4) + 2); } |
| 110 | +static constexpr uint32_t GPIO_CRL_CNF_MASK(uint8_t gpio) { return 0b11 << ((gpio * 4) + 2); } |
| 111 | +static constexpr uint32_t GPIO_CRH_MODE_INPUT(uint8_t gpio) { return 0b00 << ((gpio - 8) * 4); } |
| 112 | +static constexpr uint32_t GPIO_CRH_MODE_OUTPUT_10MHZ(uint8_t gpio) { return 0b01 << ((gpio - 8) * 4); } |
| 113 | +static constexpr uint32_t GPIO_CRH_MODE_OUTPUT_2MHZ(uint8_t gpio) { return 0b10 << ((gpio - 8) * 4); } |
| 114 | +static constexpr uint32_t GPIO_CRH_MODE_OUTPUT_50MHZ(uint8_t gpio) { return 0b11 << ((gpio - 8) * 4); } |
| 115 | +static constexpr uint32_t GPIO_CRH_MODE_MASK(uint8_t gpio) { return 0b11 << ((gpio - 8) * 4); } |
| 116 | +static constexpr uint32_t GPIO_CRH_CNF_ANALOG(uint8_t gpio) { return 0b00 << (((gpio - 8) * 4) + 2); } |
| 117 | +static constexpr uint32_t GPIO_CRH_CNF_FLOATING(uint8_t gpio) { return 0b01 << (((gpio - 8) * 4) + 2); } |
| 118 | +static constexpr uint32_t GPIO_CRH_CNF_INPUT_PUPD(uint8_t gpio) { return 0b10 << (((gpio - 8) * 4) + 2); } |
| 119 | +static constexpr uint32_t GPIO_CRH_CNF_OUTPUT(uint8_t gpio) { return 0b00 << (((gpio - 8) * 4) + 2); } |
| 120 | +static constexpr uint32_t GPIO_CRH_CNF_OUTPUT_OPENDRAIN(uint8_t gpio) { return 0b01 << (((gpio - 8) * 4) + 2); } |
| 121 | +static constexpr uint32_t GPIO_CRH_CNF_ALTERNATE(uint8_t gpio) { return 0b10 << (((gpio - 8) * 4) + 2); } |
| 122 | +static constexpr uint32_t GPIO_CRH_CNF_ALTERNATE_OPENDRAIN(uint8_t gpio) { return 0b11 << (((gpio - 8) * 4) + 2); } |
| 123 | +static constexpr uint32_t GPIO_CRH_CNF_MASK(uint8_t gpio) { return 0b11 << (((gpio - 8) * 4) + 2); } |
| 124 | +static inline void gpioSetOutputHigh(GPIO_TypeDef* port, uint8_t gpio) { port->BSRR = 1 << gpio; } |
| 125 | +static inline void gpioSetOutputLow(GPIO_TypeDef* port, uint8_t gpio) { port->BSRR = 1 << (16 + gpio); } |
| 126 | + |
| 127 | +#endif |
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