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maksyukimaksyuki
committed
Merge branch 'dev' into main
2 parents 7331f15 + d78ad1d commit 2fcde70

25 files changed

+772
-650
lines changed

‎rtl/tc_l2/src/main/scala/common/ConstVal.scala‎

Lines changed: 0 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -7,32 +7,4 @@ object ConstVal {
77
// addr width
88
val AddrLen = 64
99
val AddrAlignLen = log2Ceil(AddrLen / 8)
10-
11-
val CSRAddrLen = 12
12-
val CLINTAddrLen = 64
13-
// csr addr
14-
val mhartidAddr = 0xf14.U(CSRAddrLen.W)
15-
val mstatusAddr = 0x300.U(CSRAddrLen.W)
16-
val mieAddr = 0x304.U(CSRAddrLen.W)
17-
val mtvecAddr = 0x305.U(CSRAddrLen.W)
18-
val mscratchAddr = 0x340.U(CSRAddrLen.W)
19-
val mepcAddr = 0x341.U(CSRAddrLen.W)
20-
val mcauseAddr = 0x342.U(CSRAddrLen.W)
21-
val mipAddr = 0x344.U(CSRAddrLen.W)
22-
val mcycleAddr = 0xb00.U(CSRAddrLen.W)
23-
val medelegAddr = 0x302.U(CSRAddrLen.W)
24-
25-
val ClintBaseAddr = 0x02000000.U(CLINTAddrLen.W)
26-
val ClintBoundAddr = 0x0200bfff.U(CLINTAddrLen.W)
27-
val MSipOffset = 0x0.U(CLINTAddrLen.W)
28-
val MTimeOffset = 0xbff8.U(CLINTAddrLen.W)
29-
val MTimeCmpOffset = 0x4000.U(CLINTAddrLen.W)
30-
31-
// branch prediction
32-
val GHRLen = 5
33-
val PHTSize = 1 << GHRLen
34-
val BTBIdxLen = 5
35-
val BTBPcLen = AddrLen - BTBIdxLen
36-
val BTBTgtLen = AddrLen
37-
val BTBSize = 1 << BTBIdxLen
3810
}

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,10 +19,116 @@ trait InstConfig {
1919
val DiffRWSize = 3.U
2020
val CacheEna = false
2121

22+
// inst type
23+
// nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
24+
val InstTypeLen = 3
25+
val nopInstType = 2.U(InstTypeLen.W)
26+
val rInstType = 1.U(InstTypeLen.W)
27+
val iInstType = 2.U(InstTypeLen.W)
28+
val sInstType = 3.U(InstTypeLen.W)
29+
val bInstType = 4.U(InstTypeLen.W)
30+
val uInstType = 5.U(InstTypeLen.W)
31+
val jInstType = 6.U(InstTypeLen.W)
32+
val wtRegTrue = true.B
33+
val wtRegFalse = false.B
34+
// inst
35+
val InstValLen = 6
36+
val instADDI = 0.U(InstValLen.W)
37+
val instADDIW = 1.U(InstValLen.W)
38+
val instSLTI = 2.U(InstValLen.W)
39+
val instSLTIU = 3.U(InstValLen.W)
40+
val instANDI = 4.U(InstValLen.W)
41+
val instORI = 5.U(InstValLen.W)
42+
val instXORI = 6.U(InstValLen.W)
43+
val instSLLI = 7.U(InstValLen.W)
44+
val instSLLIW = 8.U(InstValLen.W)
45+
val instSRLI = 9.U(InstValLen.W)
46+
val instSRLIW = 10.U(InstValLen.W)
47+
val instSRAI = 11.U(InstValLen.W)
48+
val instSRAIW = 12.U(InstValLen.W)
49+
val instLUI = 13.U(InstValLen.W)
50+
val instAUIPC = 14.U(InstValLen.W)
51+
val instADD = 15.U(InstValLen.W)
52+
val instADDW = 16.U(InstValLen.W)
53+
val instSLT = 17.U(InstValLen.W)
54+
val instSLTU = 18.U(InstValLen.W)
55+
val instAND = 19.U(InstValLen.W)
56+
val instOR = 20.U(InstValLen.W)
57+
val instXOR = 21.U(InstValLen.W)
58+
val instSLL = 22.U(InstValLen.W)
59+
val instSLLW = 23.U(InstValLen.W)
60+
val instSRL = 24.U(InstValLen.W)
61+
val instSRLW = 25.U(InstValLen.W)
62+
val instSUB = 26.U(InstValLen.W)
63+
val instSUBW = 27.U(InstValLen.W)
64+
val instSRA = 28.U(InstValLen.W)
65+
val instSRAW = 29.U(InstValLen.W)
66+
val instNOP = 30.U(InstValLen.W)
67+
val instJAL = 31.U(InstValLen.W)
68+
val instJALR = 32.U(InstValLen.W)
69+
val instBEQ = 33.U(InstValLen.W)
70+
val instBNE = 34.U(InstValLen.W)
71+
val instBLT = 35.U(InstValLen.W)
72+
val instBLTU = 36.U(InstValLen.W)
73+
val instBGE = 37.U(InstValLen.W)
74+
val instBGEU = 38.U(InstValLen.W)
75+
val instLB = 39.U(InstValLen.W)
76+
val instLBU = 40.U(InstValLen.W)
77+
val instLH = 41.U(InstValLen.W)
78+
val instLHU = 42.U(InstValLen.W)
79+
val instLW = 43.U(InstValLen.W)
80+
val instLWU = 44.U(InstValLen.W)
81+
val instLD = 45.U(InstValLen.W)
82+
val instSB = 46.U(InstValLen.W)
83+
val instSH = 47.U(InstValLen.W)
84+
val instSW = 48.U(InstValLen.W)
85+
val instSD = 49.U(InstValLen.W)
86+
val instCSRRW = 50.U(InstValLen.W)
87+
val instCSRRS = 51.U(InstValLen.W)
88+
val instCSRRC = 52.U(InstValLen.W)
89+
val instCSRRWI = 53.U(InstValLen.W)
90+
val instCSRRSI = 54.U(InstValLen.W)
91+
val instCSRRCI = 55.U(InstValLen.W)
92+
val instECALL = 56.U(InstValLen.W)
93+
val instMRET = 57.U(InstValLen.W)
94+
val instFENCE = 58.U(InstValLen.W)
95+
val instFENCE_I = 59.U(InstValLen.W)
96+
val instCUST = 60.U(InstValLen.W)
97+
98+
// branch prediction
99+
val GHRLen = 5
100+
val PHTSize = 1 << GHRLen
101+
val BTBIdxLen = 5
102+
val BTBPcLen = XLen - BTBIdxLen
103+
val BTBTgtLen = XLen
104+
val BTBSize = 1 << BTBIdxLen
105+
106+
// cache
22107
val NWay = 4
23108
val NBank = 4
24109
val NSet = 32
25110
val CacheLineSize = XLen * NBank
26111
val ICacheSize = NWay * NSet * CacheLineSize
27112
val DCacheSize = NWay * NSet * CacheLineSize
113+
114+
// clint
115+
val ClintBaseAddr = 0x02000000.U(XLen.W)
116+
val ClintBoundAddr = 0x0200bfff.U(XLen.W)
117+
val MSipOffset = 0x0.U(XLen.W)
118+
val MTimeOffset = 0xbff8.U(XLen.W)
119+
val MTimeCmpOffset = 0x4000.U(XLen.W)
120+
// csr addr
121+
val CSRAddrLen = 12
122+
val mhartidAddr = 0xf14.U(CSRAddrLen.W)
123+
val mstatusAddr = 0x300.U(CSRAddrLen.W)
124+
val mieAddr = 0x304.U(CSRAddrLen.W)
125+
val mtvecAddr = 0x305.U(CSRAddrLen.W)
126+
val mscratchAddr = 0x340.U(CSRAddrLen.W)
127+
val mepcAddr = 0x341.U(CSRAddrLen.W)
128+
val mcauseAddr = 0x342.U(CSRAddrLen.W)
129+
val mipAddr = 0x344.U(CSRAddrLen.W)
130+
val mcycleAddr = 0xb00.U(CSRAddrLen.W)
131+
val medelegAddr = 0x302.U(CSRAddrLen.W)
132+
val timeCause = "h8000_0000_0000_0007".U(XLen.W)
133+
val ecallCause = "h0000_0000_0000_000b".U(XLen.W)
28134
}

‎rtl/tc_l2/src/main/scala/core/exec/ACU.scala‎

Lines changed: 36 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,42 @@
1-
package treecorel2
1+
// package treecorel2
22

3-
import chisel3._
4-
import chisel3.util._
3+
// import chisel3._
4+
// import chisel3.util._
55

6-
import treecorel2.common.ConstVal
6+
// import treecorel2.common.ConstVal
77

8-
class AGU extends Module {
9-
val io = IO(new Bundle {
10-
val isa = Input(new ISAIO)
11-
val src1 = Input(UInt(ConstVal.AddrLen.W))
12-
val src2 = Input(UInt(ConstVal.AddrLen.W))
13-
val valid = Output(Bool())
14-
val busy = Output(Bool())
15-
val res = Output(UInt(ConstVal.AddrLen.W))
16-
})
8+
// class AGU extends Module {
9+
// val io = IO(new Bundle {
10+
// val isa = Input(new ISAIO)
11+
// val src1 = Input(UInt(ConstVal.AddrLen.W))
12+
// val src2 = Input(UInt(ConstVal.AddrLen.W))
13+
// val valid = Output(Bool())
14+
// val busy = Output(Bool())
15+
// val res = Output(UInt(ConstVal.AddrLen.W))
16+
// })
1717

18-
// cordic or gcd
19-
// https://zhuanlan.zhihu.com/p/304477416
20-
// https://zhuanlan.zhihu.com/p/365058686
21-
protected val val1Reg = RegInit(0.U(64.W))
22-
protected val val2Reg = RegInit(0.U(64.W))
23-
protected val busyReg = RegInit(false.B)
24-
protected val gcdVis = io.isa.GCD
18+
// // cordic or gcd
19+
// // https://zhuanlan.zhihu.com/p/304477416
20+
// // https://zhuanlan.zhihu.com/p/365058686
21+
// protected val val1Reg = RegInit(0.U(64.W))
22+
// protected val val2Reg = RegInit(0.U(64.W))
23+
// protected val busyReg = RegInit(false.B)
24+
// protected val gcdVis = false.B
2525

26-
when(gcdVis && !busyReg) {
27-
val1Reg := io.src1
28-
val2Reg := io.src2
29-
busyReg := true.B
30-
}.elsewhen(busyReg) {
31-
when(val1Reg > val2Reg) {
32-
val1Reg := val1Reg - val2Reg
33-
}.otherwise {
34-
val2Reg := val2Reg - val1Reg
35-
}
36-
}
26+
// when(gcdVis && !busyReg) {
27+
// val1Reg := io.src1
28+
// val2Reg := io.src2
29+
// busyReg := true.B
30+
// }.elsewhen(busyReg) {
31+
// when(val1Reg > val2Reg) {
32+
// val1Reg := val1Reg - val2Reg
33+
// }.otherwise {
34+
// val2Reg := val2Reg - val1Reg
35+
// }
36+
// }
3737

38-
when(val2Reg === 0.U(64.W)) { busyReg := false.B }
39-
io.valid := (val2Reg === 0.U(64.W) && busyReg)
40-
io.busy := busyReg
41-
io.res := val1Reg
42-
}
38+
// when(val2Reg === 0.U(64.W)) { busyReg := false.B }
39+
// io.valid := (val2Reg === 0.U(64.W) && busyReg)
40+
// io.busy := busyReg
41+
// io.res := val1Reg
42+
// }

‎rtl/tc_l2/src/main/scala/core/exec/ALU.scala‎

Lines changed: 43 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -3,51 +3,50 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
class ALU extends Module {
6+
import treecorel2.common.InstConfig
7+
8+
class ALU extends Module with InstConfig {
79
val io = IO(new Bundle {
8-
val isa = Input(new ISAIO)
9-
val src1 = Input(UInt(64.W))
10-
val src2 = Input(UInt(64.W))
11-
val imm = Input(new IMMIO)
12-
val res = Output(UInt(64.W))
10+
val isa = Input(UInt(InstValLen.W))
11+
val src1 = Input(UInt(XLen.W))
12+
val src2 = Input(UInt(XLen.W))
13+
val imm = Input(UInt(XLen.W))
14+
val res = Output(UInt(XLen.W))
1315
})
1416

15-
protected val addi = SignExt(io.isa.ADDI.asUInt, 64) & (io.src1 + io.imm.I)
16-
protected val add = SignExt(io.isa.ADD.asUInt, 64) & (io.src1 + io.src2)
17-
protected val lui = SignExt(io.isa.LUI.asUInt, 64) & (io.imm.U)
18-
protected val sub = SignExt(io.isa.SUB.asUInt, 64) & (io.src1 - io.src2)
19-
protected val addiw = SignExt(io.isa.ADDIW.asUInt, 64) & SignExt((io.src1 + io.imm.I)(31, 0), 64)
20-
protected val addw = SignExt(io.isa.ADDW.asUInt, 64) & SignExt((io.src1 + io.src2)(31, 0), 64)
21-
protected val subw = SignExt(io.isa.SUBW.asUInt, 64) & SignExt((io.src1 - io.src2)(31, 0), 64)
22-
protected val arith = addi | add | lui | sub | addiw | addw | subw
23-
24-
protected val andi = SignExt(io.isa.ANDI.asUInt, 64) & (io.src1 & io.imm.I)
25-
protected val and = SignExt(io.isa.AND.asUInt, 64) & (io.src1 & io.src2)
26-
protected val ori = SignExt(io.isa.ORI.asUInt, 64) & (io.src1 | io.imm.I)
27-
protected val or = SignExt(io.isa.OR.asUInt, 64) & (io.src1 | io.src2)
28-
protected val xori = SignExt(io.isa.XORI.asUInt, 64) & (io.src1 ^ io.imm.I)
29-
protected val xor = SignExt(io.isa.XOR.asUInt, 64) & (io.src1 ^ io.src2)
30-
protected val logc = andi | and | ori | or | xori | xor
31-
32-
protected val slt = Mux((io.isa.SLT && (io.src1.asSInt < io.src2.asSInt)), 1.U(64.W), 0.U(64.W))
33-
protected val slti = Mux((io.isa.SLTI && (io.src1.asSInt < io.imm.I.asSInt)), 1.U(64.W), 0.U(64.W))
34-
protected val sltu = Mux((io.isa.SLTU && (io.src1.asUInt < io.src2.asUInt)), 1.U(64.W), 0.U(64.W))
35-
protected val sltiu = Mux((io.isa.SLTIU && (io.src1.asUInt < io.imm.I.asUInt)), 1.U(64.W), 0.U(64.W))
36-
protected val comp = slt | slti | sltu | sltiu
37-
38-
protected val sll = SignExt(io.isa.SLL.asUInt, 64) & (io.src1 << io.src2(5, 0))(63, 0)
39-
protected val srl = SignExt(io.isa.SRL.asUInt, 64) & (io.src1 >> io.src2(5, 0))
40-
protected val sra = SignExt(io.isa.SRA.asUInt, 64) & (io.src1.asSInt >> io.src2(5, 0)).asUInt
41-
protected val slli = SignExt(io.isa.SLLI.asUInt, 64) & (io.src1 << io.imm.I(5, 0))(63, 0)
42-
protected val srli = SignExt(io.isa.SRLI.asUInt, 64) & (io.src1 >> io.imm.I(5, 0))
43-
protected val srai = SignExt(io.isa.SRAI.asUInt, 64) & (io.src1.asSInt >> io.imm.I(5, 0)).asUInt
44-
protected val sllw = SignExt(io.isa.SLLW.asUInt, 64) & SignExt((io.src1 << io.src2(4, 0))(31, 0), 64)
45-
protected val srlw = SignExt(io.isa.SRLW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.src2(4, 0)), 64)
46-
protected val sraw = SignExt(io.isa.SRAW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.src2(4, 0)).asUInt, 64)
47-
protected val slliw = SignExt(io.isa.SLLIW.asUInt, 64) & SignExt((io.src1 << io.imm.I(4, 0))(31, 0), 64)
48-
protected val srliw = SignExt(io.isa.SRLIW.asUInt, 64) & SignExt((io.src1(31, 0) >> io.imm.I(4, 0)), 64)
49-
protected val sraiw = SignExt(io.isa.SRAIW.asUInt, 64) & SignExt((io.src1(31, 0).asSInt >> io.imm.I(4, 0)).asUInt, 64)
50-
protected val shift = sll | srl | sra | slli | srli | srai | sllw | srlw | sraw | slliw | srliw | sraiw
51-
52-
io.res := arith | logc | comp | shift
17+
io.res := MuxLookup(
18+
io.isa,
19+
0.U(XLen.W),
20+
Seq(
21+
instADDI -> (io.src1 + io.imm),
22+
instADD -> (io.src1 + io.src2),
23+
instLUI -> (io.imm),
24+
instSUB -> (io.src1 - io.src2),
25+
instADDIW -> SignExt((io.src1 + io.imm)(31, 0), 64),
26+
instADDW -> SignExt((io.src1 + io.src2)(31, 0), 64),
27+
instSUBW -> SignExt((io.src1 - io.src2)(31, 0), 64),
28+
instANDI -> (io.src1 & io.imm),
29+
instAND -> (io.src1 & io.src2),
30+
instORI -> (io.src1 | io.imm),
31+
instOR -> (io.src1 | io.src2),
32+
instXORI -> (io.src1 ^ io.imm),
33+
instXOR -> (io.src1 ^ io.src2),
34+
instSLT -> Mux(io.src1.asSInt < io.src2.asSInt, 1.U(XLen.W), 0.U(XLen.W)),
35+
instSLTI -> Mux(io.src1.asSInt < io.imm.asSInt, 1.U(XLen.W), 0.U(XLen.W)),
36+
instSLTU -> Mux(io.src1.asUInt < io.src2.asUInt, 1.U(XLen.W), 0.U(XLen.W)),
37+
instSLTIU -> Mux(io.src1.asUInt < io.imm.asUInt, 1.U(XLen.W), 0.U(XLen.W)),
38+
instSLL -> (io.src1 << io.src2(5, 0))(63, 0),
39+
instSRL -> (io.src1 >> io.src2(5, 0)),
40+
instSRA -> (io.src1.asSInt >> io.src2(5, 0)).asUInt,
41+
instSLLI -> (io.src1 << io.imm(5, 0))(63, 0),
42+
instSRLI -> (io.src1 >> io.imm(5, 0)),
43+
instSRAI -> (io.src1.asSInt >> io.imm(5, 0)).asUInt,
44+
instSLLW -> SignExt((io.src1 << io.src2(4, 0))(31, 0), 64),
45+
instSRLW -> SignExt((io.src1(31, 0) >> io.src2(4, 0)), 64),
46+
instSRAW -> SignExt((io.src1(31, 0).asSInt >> io.src2(4, 0)).asUInt, 64),
47+
instSLLIW -> SignExt((io.src1 << io.imm(4, 0))(31, 0), 64),
48+
instSRLIW -> SignExt((io.src1(31, 0) >> io.imm(4, 0)), 64),
49+
instSRAIW -> SignExt((io.src1(31, 0).asSInt >> io.imm(4, 0)).asUInt, 64)
50+
)
51+
)
5352
}

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