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maksyukimaksyuki
committed
feat: rewrite all the components
1 parent 600bc6c commit 359b71d

37 files changed

+1546
-19
lines changed

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

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package sim
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import chisel3._
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import chisel3.util._
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import treecorel2._
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import treecorel2.common.AXI4Config
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class AXI4Bridge extends Module with AXI4Config {
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val io = IO(new Bundle {
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val socEn = Input(Bool())
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val runEn = Output(Bool())
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val dxchg = Flipped(new DXCHGIO)
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val axi = if (SoCEna) new SOCAXI4IO else new AXI4IO
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})
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protected val runEn = RegInit(false.B)
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io.runEn := Mux(reset.asBool(), false.B, runEn)
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// handshake
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protected val awHdShk = io.axi.aw.valid && io.axi.aw.ready
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protected val wHdShk = io.axi.w.valid && io.axi.w.ready
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protected val bHdShk = io.axi.b.valid && io.axi.b.ready
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protected val arHdShk = io.axi.ar.valid && io.axi.ar.ready
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protected val rHdShk = io.axi.r.valid && io.axi.r.ready
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protected val arbiter = new Arbiter
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// FSM for read/write
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protected val eumIDLE :: eumStandby :: eumIDLE2 :: eumAW :: eumW :: eumB :: eumAR :: eumR :: Nil = Enum(8)
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protected val stateReg = RegInit(eumIDLE)
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switch(stateReg) {
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is(eumIDLE) {
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arbiter.finished := false.B
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arbiter.ren := io.dxchg.ren
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arbiter.raddr := io.dxchg.raddr
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arbiter.rdata := io.dxchg.rdata
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arbiter.rsize := io.dxchg.rsize
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arbiter.wen := io.dxchg.wen
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arbiter.waddr := io.dxchg.waddr
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arbiter.wdata := io.dxchg.wdata
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arbiter.wmask := io.dxchg.wmask
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stateReg := eumStandby
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}
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is(eumStandby) {
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when(arbiter.finished) {
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runEn := true.B
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stateReg := eumIDLE2
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}.elsewhen(arbiter.wen) {
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stateReg := eumAW
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}.elsewhen(arbiter.ren) {
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stateReg := eumAR
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}.otherwise {
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arbiter.finished := true.B
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stateReg := eumStandby
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}
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}
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is(eumIDLE2) {
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runEn := false.B
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stateReg := eumIDLE
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}
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is(eumAR) {
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when(io.axi.ar.ready) {
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stateReg := eumR
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}
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}
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is(eumR) {
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when(rHdShk) {
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arbiter.rdata := io.axi.r.bits.data
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arbiter.finished := true.B
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stateReg := eumStandby
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}
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}
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is(eumAW) {
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when(awHdShk) {
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stateReg := eumW
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}
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}
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is(eumW) {
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when(wHdShk) {
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stateReg := eumB
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}
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}
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is(eumB) {
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when(bHdShk) {
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arbiter.finished := true.B
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stateReg := eumStandby
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}
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}
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}
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protected val wMask = arbiter.wmask
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protected val bitCnt = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
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protected val socARSize = arbiter.rsize
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protected val socAWSize = MuxLookup(
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bitCnt,
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0.U,
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Array(
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8.U -> 3.U,
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4.U -> 2.U,
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2.U -> 1.U,
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1.U -> 0.U
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)
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)
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protected val arSize = Mux(io.socEn, socARSize, 3.U)
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protected val awSize = Mux(io.socEn, socAWSize, 3.U)
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protected val addrMask = Mux(io.socEn, "hffffffffffffffff".U(64.W), "hfffffffffffffff8".U(64.W))
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when(stateReg === eumAR) {
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io.axi.ar.valid := true.B
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io.axi.ar.bits.size := arSize
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io.axi.ar.bits.addr := arbiter.raddr & addrMask
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io.axi.r.ready := false.B
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io.axi.aw.valid := false.B
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io.axi.aw.bits.size := 0.U
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io.axi.aw.bits.addr := 0.U
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io.axi.w.valid := false.B
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io.axi.w.bits.strb := 0.U
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io.axi.w.bits.data := 0.U
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io.axi.b.ready := false.B
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}.elsewhen(stateReg === eumR) {
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io.axi.ar.valid := false.B
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io.axi.ar.bits.size := arSize
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io.axi.ar.bits.addr := arbiter.raddr & addrMask
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io.axi.r.ready := true.B
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io.axi.aw.valid := false.B
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io.axi.aw.bits.size := 0.U
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io.axi.aw.bits.addr := 0.U
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io.axi.w.valid := false.B
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io.axi.w.bits.strb := 0.U
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io.axi.w.bits.data := 0.U
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io.axi.b.ready := false.B
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}.elsewhen(stateReg === eumAW) {
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io.axi.ar.valid := false.B
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io.axi.ar.bits.size := 0.U
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io.axi.ar.bits.addr := 0.U
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io.axi.r.ready := false.B
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io.axi.aw.valid := true.B
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io.axi.aw.bits.size := awSize
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io.axi.aw.bits.addr := arbiter.waddr & addrMask
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io.axi.w.valid := false.B
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io.axi.w.bits.strb := 0.U
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io.axi.w.bits.data := 0.U
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io.axi.b.ready := false.B
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}.elsewhen(stateReg === eumW) {
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io.axi.ar.valid := false.B
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io.axi.ar.bits.size := 0.U
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io.axi.ar.bits.addr := 0.U
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io.axi.r.ready := false.B
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io.axi.aw.valid := false.B
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io.axi.aw.bits.size := awSize
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io.axi.aw.bits.addr := arbiter.waddr & addrMask
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io.axi.w.valid := true.B
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io.axi.w.bits.strb := wMask
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io.axi.w.bits.data := arbiter.wdata
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io.axi.b.ready := false.B
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}.elsewhen(stateReg === eumB) {
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io.axi.ar.valid := false.B
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io.axi.ar.bits.size := 0.U
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io.axi.ar.bits.addr := 0.U
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io.axi.r.ready := false.B
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io.axi.aw.valid := false.B
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io.axi.aw.bits.size := 0.U
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io.axi.aw.bits.addr := 0.U
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io.axi.w.valid := false.B
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io.axi.w.bits.strb := 0.U
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io.axi.w.bits.data := 0.U
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io.axi.b.ready := true.B
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}.otherwise {
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io.axi.ar.valid := false.B
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io.axi.ar.bits.size := 0.U
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io.axi.ar.bits.addr := 0.U
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io.axi.r.ready := false.B
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io.axi.aw.valid := false.B
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io.axi.aw.bits.size := 0.U
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io.axi.aw.bits.addr := 0.U
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io.axi.w.valid := false.B
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io.axi.w.bits.strb := 0.U
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io.axi.w.bits.data := 0.U
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io.axi.b.ready := false.B
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}
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if (!SoCEna) {
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val sim = io.axi.asInstanceOf[AXI4IO]
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sim.ar.bits.prot := 0.U
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sim.ar.bits.id := 0.U
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sim.ar.bits.len := 0.U
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sim.ar.bits.burst := 1.U
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sim.ar.bits.lock := 0.U
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sim.ar.bits.cache := 0.U
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sim.ar.bits.qos := 0.U
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sim.ar.bits.user := DontCare
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sim.aw.bits.prot := 0.U
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sim.aw.bits.id := 0.U
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sim.aw.bits.len := 0.U
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sim.aw.bits.burst := 1.U
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sim.aw.bits.lock := false.B
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sim.aw.bits.cache := 0.U
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sim.aw.bits.qos := 0.U
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sim.aw.bits.user := DontCare
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sim.w.bits.last := 1.U
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} else {
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io.axi.ar.bits.id := 0.U
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io.axi.ar.bits.len := 0.U
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io.axi.ar.bits.burst := 1.U
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io.axi.aw.bits.id := 0.U
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io.axi.aw.bits.len := 0.U
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io.axi.aw.bits.burst := 1.U
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io.axi.w.bits.last := 1.U
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}
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io.dxchg.rdata := arbiter.rdata
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}

‎rtl/tc_l2/src/main/scala/axi4/Arbiter.scala‎

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package sim
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import chisel3._
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import chisel3.util._
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class Arbiter {
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val finished = RegInit(false.B)
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val ren = RegInit(false.B)
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val raddr = RegInit(0.U(64.W))
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val rdata = RegInit(0.U(64.W))
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val rsize = RegInit(0.U(3.W))
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val wen = RegInit(false.B)
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val waddr = RegInit(0.U(64.W))
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val wdata = RegInit(0.U(64.W))
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val wmask = RegInit(0.U(8.W))
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}

‎rtl/tc_l2/src/main/scala/axi4/Crossbar.scala‎

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package treecorel2
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import chisel3._
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import chisel3.util._
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class Crossbar extends Module {
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val io = IO(new Bundle {
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val socEn = Input(Bool())
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val runEn = Input(Bool())
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val dxchg = new DXCHGIO
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val core = new COREIO
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})
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protected val globalEn = RegInit(false.B)
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protected val inst = RegInit(0.U(32.W))
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protected val rdInst = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
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io.core.globalEn := Mux(io.runEn, globalEn, false.B)
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io.core.fetch.data := inst
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io.core.ld.data := io.dxchg.rdata
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// FSM for inst or mem data xform
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protected val eumInst :: eumMem :: Nil = Enum(2)
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protected val stateReg = RegInit(eumInst)
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switch(stateReg) {
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is(eumInst) {
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when(io.runEn) {
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stateReg := eumMem
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globalEn := true.B
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inst := rdInst
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}
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}
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is(eumMem) {
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when(io.runEn) {
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stateReg := eumInst
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globalEn := false.B
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inst := 0x13.U
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}
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}
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}
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protected val instSize = Mux(io.socEn, 2.U, 3.U)
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// because the difftest's logic addr is 0x000000
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protected val addrOffset = Mux(io.socEn, "h0000000000000000".U(64.W), "h0000000080000000".U(64.W))
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protected val instAddr = io.core.fetch.addr - addrOffset
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protected val loadAddr = io.core.ld.addr - addrOffset
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protected val storeAddr = io.core.sd.addr - addrOffset
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protected val maEn = io.core.ld.en || io.core.sd.en
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io.dxchg.clk := clock
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io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
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io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
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io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
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io.dxchg.waddr := storeAddr
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io.dxchg.wdata := io.core.sd.data
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io.dxchg.wmask := io.core.sd.mask
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io.dxchg.wen := stateReg === eumMem && io.core.sd.en
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}

‎rtl/tc_l2/src/main/scala/common/AXI4Config.scala‎

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package treecorel2.common
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import chisel3._
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import chisel3.util._
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trait AXI4Config extends InstConfig {}

‎rtl/tc_l2/src/main/scala/common/ConstVal.scala‎

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package treecorel2.common
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import chisel3._
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object ConstVal {
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val CSRAddrLen = 12
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val CLINTAddrLen = 64
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// csr addr
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val mhartidAddr = 0xf14.U(CSRAddrLen.W)
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val mstatusAddr = 0x300.U(CSRAddrLen.W)
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val mieAddr = 0x304.U(CSRAddrLen.W)
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val mtvecAddr = 0x305.U(CSRAddrLen.W)
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val mscratchAddr = 0x340.U(CSRAddrLen.W)
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val mepcAddr = 0x341.U(CSRAddrLen.W)
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val mcauseAddr = 0x342.U(CSRAddrLen.W)
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val mipAddr = 0x344.U(CSRAddrLen.W)
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val mcycleAddr = 0xb00.U(CSRAddrLen.W)
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val medelegAddr = 0x302.U(CSRAddrLen.W)
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val ClintBaseAddr = 0x02000000.U(CLINTAddrLen.W)
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val ClintBoundAddr = 0x0200bfff.U(CLINTAddrLen.W)
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val MSipOffset = 0x0.U(CLINTAddrLen.W)
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val MTimeOffset = 0xbff8.U(CLINTAddrLen.W)
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val MTimeCmpOffset = 0x4000.U(CLINTAddrLen.W)
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}

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

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package treecorel2.common
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import chisel3._
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import chisel3.util._
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trait InstConfig {
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val SoCEna = false
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}

‎rtl/tc_l2/src/main/scala/common/NumExten.scala‎

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package treecorel2
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import chisel3._
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import chisel3.util._
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// be careful to call this func, need to set the right msb val!!!
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// to minify the wire unused pin and bits in verilator
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object SignExt {
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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val signBit = a(aLen - 1)
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if (aLen >= len) a(len - 1, 0) else Cat(Fill(len - aLen, signBit), a)
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}
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}
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object ZeroExt {
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def apply(a: UInt, len: Int) = {
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val aLen = a.getWidth
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if (aLen >= len) a(len - 1, 0) else Cat(0.U((len - aLen).W), a)
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}
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}

‎rtl/tc_l2/src/main/scala/common/Timer.scala‎

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package treecorel2
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import chisel3._
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import chisel3.util._
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// generate low speed clock
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class Timer(div: Int = 5) extends Module {
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val io = IO(new Bundle {
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val tick = Output(Bool())
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})
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require(div > 0)
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require(div < 15)
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protected val clockCnt = RegInit(1.U(4.W))
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protected val tickTrigger = clockCnt === div.U
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when(tickTrigger) {
18+
clockCnt := 1.U
19+
}.otherwise {
20+
clockCnt := clockCnt + 1.U
21+
}
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io.tick := tickTrigger
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}

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