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Commit 44cd14b

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feat: delete old verilog code to gen new sig period model
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rtl/tc_l1/core/defines.v

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This file was deleted.

rtl/tc_l1/core/pc_reg.v

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rtl/tc_l1/utils/full_handshake_rx.v

Lines changed: 0 additions & 128 deletions
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