feat: add custom inst decode for the alu

Author: maksyuki

rtl/tc_l2/src/main/scala/core/exec/ACU.scala

@@ -11,27 +11,32 @@ class AGU extends Module {
     val src1  = Input(UInt(ConstVal.AddrLen.W))
     val src2  = Input(UInt(ConstVal.AddrLen.W))
     val valid = Output(Bool())
+    val busy  = Output(Bool())
     val res   = Output(UInt(ConstVal.AddrLen.W))
   })
 
   // cordic or gcd
   // https://zhuanlan.zhihu.com/p/304477416
   // https://zhuanlan.zhihu.com/p/365058686
-  protected val vala   = RegInit(0.U(64.W))
-  protected val valb   = RegInit(0.U(64.W))
-  protected val gcdVis = io.isa.GCD
+  protected val val1Reg = RegInit(0.U(64.W))
+  protected val val2Reg = RegInit(0.U(64.W))
+  protected val busyReg = RegInit(false.B)
+  protected val gcdVis  = io.isa.GCD
 
-  when(gcdVis && io.valid) {
-    vala := io.src1
-    valb := io.src2
-  }.otherwise {
-    when(vala > valb) {
-      vala := vala - valb
+  when(gcdVis && !busyReg) {
+    val1Reg := io.src1
+    val2Reg := io.src2
+    busyReg := true.B
+  }.elsewhen(busyReg) {
+    when(val1Reg > val2Reg) {
+      val1Reg := val1Reg - val2Reg
     }.otherwise {
-      valb := valb - vala
+      val2Reg := val2Reg - val1Reg
     }
   }
 
-  io.valid := valb === 0.U(64.W)
-  io.res   := vala
+  when(val2Reg === 0.U(64.W)) { busyReg := false.B }
+  io.valid := (val2Reg === 0.U(64.W) && busyReg)
+  io.busy  := busyReg
+  io.res   := val1Reg
 }

rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala

@@ -102,10 +102,11 @@ class ISADecoder extends Module {
   protected val env    = io.isa.ECALL || io.isa.EBREAK
   protected val csr    = io.isa.CSRRW || io.isa.CSRRS || io.isa.CSRRC || io.isa.CSRRWI || io.isa.CSRRSI || io.isa.CSRRCI
   protected val priv   = io.isa.MRET || io.isa.SRET || io.isa.WFI || io.isa.SFENCE_VMA
+  protected val custom = io.isa.GCD
 
   protected val immExten = Module(new ImmExten)
   immExten.io.inst := io.inst
   io.imm           := immExten.io.imm
   io.csr           := csr
-  io.wen           := arith || logc || shift || comp || link || load || csr
+  io.wen           := arith || logc || shift || comp || link || load || csr || custom
 }