feat: add needed io port def for branch pred

Author: maksyuki

rtl/tc_l2/src/main/scala/core/ma/Memory.scala

@@ -14,17 +14,19 @@ class Memory extends Module {
     val mtip      = Output(Bool())
   })
 
-  protected val memReg = RegEnable(io.ex2mem, WireInit(0.U.asTypeOf(new EX2MEMIO())), io.globalEn)
-  protected val valid  = memReg.valid
-  protected val inst   = memReg.inst
-  protected val pc     = memReg.pc
-  protected val isa    = memReg.isa
-  protected val imm    = memReg.imm
-  protected val rs1    = memReg.inst(19, 15)
-  protected val rs2    = memReg.inst(24, 20)
-  protected val src1   = memReg.src1
-  protected val src2   = memReg.src2
-  protected val csr    = memReg.csr
+  protected val memReg    = RegEnable(io.ex2mem, WireInit(0.U.asTypeOf(new EX2MEMIO())), io.globalEn)
+  protected val valid     = memReg.valid
+  protected val inst      = memReg.inst
+  protected val pc        = memReg.pc
+  protected val branIdx   = memReg.branIdx
+  protected val predTaken = memReg.predTaken
+  protected val isa       = memReg.isa
+  protected val imm       = memReg.imm
+  protected val rs1       = memReg.inst(19, 15)
+  protected val rs2       = memReg.inst(24, 20)
+  protected val src1      = memReg.src1
+  protected val src2      = memReg.src2
+  protected val csr       = memReg.csr
 
   protected val lsu = Module(new LSU)
   lsu.io.valid := valid
@@ -52,6 +54,8 @@ class Memory extends Module {
   io.mem2wb.valid      := valid
   io.mem2wb.inst       := inst
   io.mem2wb.pc         := pc
+  io.mem2wb.branIdx    := branIdx
+  io.mem2wb.predTaken  := predTaken
   io.mem2wb.isa        := isa
   io.mem2wb.src1       := src1
   io.mem2wb.src2       := src2

rtl/tc_l2/src/main/scala/port/IF2IDIO.scala

@@ -3,8 +3,12 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
+import treecorel2.common.ConstVal
+
 class IF2IDIO extends Bundle {
-  val valid = Output(Bool())
-  val inst  = Output(UInt(32.W))
-  val pc    = Output(UInt(64.W))
+  val valid     = Output(Bool())
+  val inst      = Output(UInt(32.W))
+  val pc        = Output(UInt(64.W))
+  val branIdx   = Output(UInt(ConstVal.GHRLen.W))
+  val predTaken = Output(Bool())
 }

rtl/tc_l2/src/main/scala/port/ISAIO.scala

@@ -80,4 +80,5 @@ class ISAIO extends Bundle {
   val REMU       = Bool()
   val REMUW      = Bool()
   val REMW       = Bool()
+  val GCD        = Bool()
 }