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1 parent 6eee077 commit 6e110edCopy full SHA for 6e110ed
rtl/tc_l2/src/main/scala/utils/AddModulePrefix.scala
@@ -1,6 +1,6 @@
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// ref: https://github.com/OSCPU/ysyxSoC/blob/master/ysyx/module-prefix/AddModulePrefix.scala
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// thanks to (Jiawei Lin)https://github.com/ljwljwljwljw
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-package treecorel2 // modify to your package name
+package sim // modify to your package name
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import firrtl._
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import firrtl.annotations.{ModuleTarget, NoTargetAnnotation}
@@ -26,7 +26,8 @@ class AddModulePrefix extends Transform with DependencyAPIMigration {
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}.get
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val blacklist = List(
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- "S011HD1P_X32Y2D128"
+ "S011HD1P_X32Y2D128",
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+ "ysyx_210324"
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)
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val extModules = state.circuit.modules
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