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maksyukimaksyuki
committed
Merge branch 'dev' into main
2 parents a8859e5 + d5188a7 commit 6f479af

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7 files changed

+148
-188
lines changed

7 files changed

+148
-188
lines changed

‎rtl/tc_l2/src/main/scala/core/Processor.scala‎

Lines changed: 3 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8,15 +8,9 @@ import treecorel2._
88

99
class Processor extends Module {
1010
val io = IO(new Bundle {
11-
val runEn = Input(Bool())
12-
val socEn = Input(Bool())
13-
val dxchg = new DXCHGIO
14-
val instComm = Flipped(new DiffInstrCommitIO)
15-
val archIntRegState = Flipped(new DiffArchIntRegStateIO)
16-
val csrState = Flipped(new DiffCSRStateIO)
17-
val trapEvt = Flipped(new DiffTrapEventIO)
18-
val archFpRegState = Flipped(new DiffArchFpRegStateIO)
19-
val archEvt = Flipped(new DiffArchEventIO)
11+
val runEn = Input(Bool())
12+
val socEn = Input(Bool())
13+
val dxchg = new DXCHGIO
2014
})
2115

2216
protected val cpu = Module(new TreeCoreL2)
@@ -31,11 +25,4 @@ class Processor extends Module {
3125
cpu.io.ld <> crossbar.io.core.ld
3226
cpu.io.sd <> crossbar.io.core.sd
3327
crossbar.io.dxchg <> io.dxchg
34-
35-
cpu.io.instComm <> io.instComm
36-
cpu.io.archIntRegState <> io.archIntRegState
37-
cpu.io.csrState <> io.csrState
38-
cpu.io.trapEvt <> io.trapEvt
39-
cpu.io.archFpRegState <> io.archFpRegState
40-
cpu.io.archEvt <> io.archEvt
4128
}

‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala‎

Lines changed: 3 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -11,21 +11,13 @@ class TreeCoreL2 extends Module {
1111
val fetch = new IFIO
1212
val ld = new LDIO
1313
val sd = new SDIO
14-
15-
// difftest
16-
val instComm = Flipped(new DiffInstrCommitIO)
17-
val archIntRegState = Flipped(new DiffArchIntRegStateIO)
18-
val csrState = Flipped(new DiffCSRStateIO)
19-
val trapEvt = Flipped(new DiffTrapEventIO)
20-
val archFpRegState = Flipped(new DiffArchFpRegStateIO)
21-
val archEvt = Flipped(new DiffArchEventIO)
2214
})
2315

2416
protected val ifu = Module(new IFU)
2517
protected val idu = Module(new IDU)
2618
protected val exu = Module(new EXU)
27-
protected val mau = Module(new Memory)
28-
protected val wbu = Module(new WriteBack)
19+
protected val mau = Module(new MAU)
20+
protected val wbu = Module(new WBU)
2921

3022
ifu.io.socEn := io.socEn
3123
wbu.io.socEn := io.socEn
@@ -92,11 +84,5 @@ class TreeCoreL2 extends Module {
9284
io.sd.data := mau.io.sd.data
9385
io.sd.mask := mau.io.sd.mask
9486

95-
idu.io.gpr <> wbu.io.gpr
96-
io.instComm <> wbu.io.instComm
97-
io.archIntRegState <> wbu.io.archIntRegState
98-
io.csrState <> wbu.io.csrState
99-
io.trapEvt <> wbu.io.trapEvt
100-
io.archFpRegState <> wbu.io.archFpRegState
101-
io.archEvt <> wbu.io.archEvt
87+
idu.io.gpr <> wbu.io.gpr
10288
}

‎rtl/tc_l2/src/main/scala/core/if/Cache.scala‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,4 @@
1-
package treecorel2
1+
// package treecorel2
22

3-
import chisel3._
4-
import chisel3.util._
5-
6-
class Cache extends Module {
7-
8-
}
3+
// import chisel3._
4+
// import chisel3.util._

‎rtl/tc_l2/src/main/scala/core/ma/Memory.scala‎ renamed to ‎rtl/tc_l2/src/main/scala/core/ma/MAU.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
class Memory extends Module {
6+
class MAU extends Module {
77
val io = IO(new Bundle {
88
val globalEn = Input(Bool())
99
val ex2mem = Flipped(new EX2MEMIO)

‎rtl/tc_l2/src/main/scala/core/wb/WBU.scala‎

Lines changed: 136 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,136 @@
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
import difftest._
7+
8+
import treecorel2.common.ConstVal
9+
import treecorel2.common.InstConfig
10+
11+
class WBU extends Module with InstConfig {
12+
val io = IO(new Bundle {
13+
val globalEn = Input(Bool())
14+
val socEn = Input(Bool())
15+
val mem2wb = Flipped(new MEM2WBIO)
16+
val wbdata = new WBDATAIO
17+
val gpr = Input(Vec(32, UInt(64.W)))
18+
})
19+
20+
protected val wbReg = RegEnable(io.mem2wb, WireInit(0.U.asTypeOf(new MEM2WBIO())), io.globalEn)
21+
protected val valid = wbReg.valid
22+
protected val inst = wbReg.inst
23+
protected val pc = wbReg.pc
24+
protected val isa = wbReg.isa
25+
protected val src1 = wbReg.src1
26+
protected val src2 = wbReg.src2
27+
protected val imm = wbReg.imm
28+
protected val wen = wbReg.wen
29+
protected val wdest = wbReg.wdest
30+
protected val aluRes = wbReg.aluRes
31+
protected val branch = wbReg.branch
32+
protected val tgt = wbReg.tgt
33+
protected val link = wbReg.link
34+
protected val auipc = wbReg.auipc
35+
protected val loadData = wbReg.loadData
36+
protected val csrData = wbReg.csrData
37+
protected val cvalid = wbReg.cvalid
38+
protected val timeIntrEn = wbReg.timeIntrEn
39+
protected val ecallEn = wbReg.ecallEn
40+
protected val csr = wbReg.csr
41+
42+
protected val cycleCnt = RegInit(0.U(64.W))
43+
protected val instrCnt = RegInit(0.U(64.W))
44+
cycleCnt := cycleCnt + 1.U
45+
when(io.globalEn && valid) { instrCnt := instrCnt + 1.U }
46+
47+
protected val wbdata = aluRes | link | auipc | loadData | csrData
48+
49+
io.wbdata.wen := valid && wen
50+
io.wbdata.wdest := wdest
51+
io.wbdata.data := wbdata
52+
53+
protected val printVis = inst(6, 0) === "h7b".U(7.W)
54+
protected val haltVis = inst(6, 0) === "h6b".U(7.W)
55+
56+
when(~io.socEn) {
57+
when(io.globalEn && valid && printVis) {
58+
printf("%c", io.gpr(10))
59+
}
60+
}
61+
62+
// for difftest commit
63+
protected val mmioEn = cvalid
64+
protected val csrVis = isa.CSRRW || isa.CSRRS || isa.CSRRC || isa.CSRRWI || isa.CSRRSI || isa.CSRRCI
65+
protected val mcycleVis = csrVis && (inst(31, 20) === ConstVal.mcycleAddr)
66+
protected val mipVis = csrVis && (inst(31, 20) === ConstVal.mipAddr)
67+
protected val timeIntrEnReg = RegEnable(timeIntrEn, false.B, io.globalEn)
68+
protected val diffValid = io.globalEn && (RegEnable(valid, false.B, io.globalEn) || timeIntrEnReg)
69+
70+
if (!SoCEna) {
71+
val instComm = Module(new DifftestInstrCommit)
72+
val archIntRegState = Module(new DifftestArchIntRegState)
73+
val csrState = Module(new DifftestCSRState)
74+
val trapEvt = Module(new DifftestTrapEvent)
75+
val archFpRegState = Module(new DifftestArchFpRegState)
76+
val archEvt = Module(new DifftestArchEvent)
77+
78+
instComm.io.clock := clock
79+
instComm.io.coreid := 0.U
80+
instComm.io.index := 0.U
81+
instComm.io.valid := diffValid && ~timeIntrEnReg
82+
instComm.io.pc := RegEnable(pc, 0.U, io.globalEn)
83+
instComm.io.instr := RegEnable(inst, 0.U, io.globalEn)
84+
instComm.io.special := 0.U
85+
instComm.io.skip := diffValid && RegEnable(printVis || mcycleVis || mmioEn || mipVis, false.B, io.globalEn)
86+
instComm.io.isRVC := false.B
87+
instComm.io.scFailed := false.B
88+
instComm.io.wen := RegEnable(wen, false.B, io.globalEn)
89+
instComm.io.wdata := RegEnable(wbdata, 0.U, io.globalEn)
90+
instComm.io.wdest := RegEnable(wdest, 0.U, io.globalEn)
91+
92+
archIntRegState.io.clock := clock
93+
archIntRegState.io.coreid := 0.U
94+
archIntRegState.io.gpr := io.gpr
95+
96+
csrState.io.clock := clock
97+
csrState.io.coreid := 0.U
98+
csrState.io.mstatus := csr.mstatus
99+
csrState.io.mcause := csr.mcause
100+
csrState.io.mepc := csr.mepc
101+
csrState.io.sstatus := csr.mstatus & "h8000_0003_000d_e122".U
102+
csrState.io.scause := 0.U
103+
csrState.io.sepc := 0.U
104+
csrState.io.satp := 0.U
105+
csrState.io.mip := 0.U
106+
csrState.io.mie := csr.mie
107+
csrState.io.mscratch := csr.mscratch
108+
csrState.io.sscratch := 0.U
109+
csrState.io.mideleg := 0.U
110+
csrState.io.medeleg := csr.medeleg
111+
csrState.io.mtval := 0.U
112+
csrState.io.stval := 0.U
113+
csrState.io.mtvec := csr.mtvec
114+
csrState.io.stvec := 0.U
115+
csrState.io.priviledgeMode := 3.U
116+
117+
archEvt.io.clock := clock
118+
archEvt.io.coreid := 0.U
119+
archEvt.io.intrNO := Mux(diffValid && timeIntrEnReg, 7.U, 0.U)
120+
archEvt.io.cause := 0.U
121+
archEvt.io.exceptionPC := RegEnable(pc, 0.U, io.globalEn)
122+
archEvt.io.exceptionInst := RegEnable(inst, 0.U, io.globalEn)
123+
124+
trapEvt.io.clock := clock
125+
trapEvt.io.coreid := 0.U
126+
trapEvt.io.valid := diffValid && RegEnable(haltVis, false.B, io.globalEn)
127+
trapEvt.io.code := io.gpr(10)(7, 0)
128+
trapEvt.io.pc := RegEnable(pc, 0.U, io.globalEn)
129+
trapEvt.io.cycleCnt := cycleCnt
130+
trapEvt.io.instrCnt := instrCnt
131+
132+
archFpRegState.io.clock := clock
133+
archFpRegState.io.coreid := 0.U
134+
archFpRegState.io.fpr := RegInit(VecInit(Seq.fill(32)(0.U(64.W))))
135+
}
136+
}

‎rtl/tc_l2/src/main/scala/core/wb/WriteBack.scala‎

Lines changed: 0 additions & 132 deletions
This file was deleted.

‎rtl/tc_l2/src/main/scala/top/SimTop.scala‎

Lines changed: 2 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -14,14 +14,8 @@ class SimTop extends Module {
1414
val memAXI_0 = new AXI4IO
1515
})
1616

17-
protected val proc = Module(new Processor)
18-
protected val axiBridge = Module(new AXI4Bridge)
19-
protected val instComm = Module(new DifftestInstrCommit)
20-
protected val archIntRegState = Module(new DifftestArchIntRegState)
21-
protected val csrState = Module(new DifftestCSRState)
22-
protected val trapEvt = Module(new DifftestTrapEvent)
23-
protected val archFpRegState = Module(new DifftestArchFpRegState)
24-
protected val archEvt = Module(new DifftestArchEvent)
17+
protected val proc = Module(new Processor)
18+
protected val axiBridge = Module(new AXI4Bridge)
2519

2620
io.uart.in.valid := false.B
2721
io.uart.out.valid := false.B
@@ -33,11 +27,4 @@ class SimTop extends Module {
3327
axiBridge.io.socEn := false.B
3428

3529
io.memAXI_0 <> axiBridge.io.axi
36-
37-
proc.io.instComm <> instComm.io
38-
proc.io.archIntRegState <> archIntRegState.io
39-
proc.io.csrState <> csrState.io
40-
proc.io.trapEvt <> trapEvt.io
41-
proc.io.archFpRegState <> archFpRegState.io
42-
proc.io.archEvt <> archEvt.io
4330
}

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