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1 | 1 | <p align="center"> |
2 | 2 | <img width="200px" src="./.images/tree_core_logo.svg" align="center" alt="Tree Core CPU" /> |
3 | 3 | <h1 align="center">TreeCore CPU</h1> |
4 | | - <p align="center">A series of RISCV soft core processors written from scratch</p> |
| 4 | + <h2 align="center">A series of riscv processors written from scratch</h2> |
5 | 5 | </p> |
6 | 6 | <p align="center"> |
7 | 7 | <a href="./LICENSE"> |
8 | | - <img alt="license" src="https://img.shields.io/github/license/microdynamics-cpu/tree_core_cpu.svg" /> |
| 8 | + <img src="https://img.shields.io/github/license/microdynamics-cpu/tree_core_cpu?color=brightgreen&logo=github&style=flat-square"> |
| 9 | + </a> |
| 10 | + <a href="https://github.com/microdynamics-cpu/tree-core-cpu"> |
| 11 | + <img alt="stars" src="https://img.shields.io/github/stars/microdynamics-cpu/tree_core_cpu?color=blue&style=flat-square" /> |
| 12 | + </a> |
| 13 | + <a href="https://github.com/microdynamics-cpu/tree-core-cpu"> |
| 14 | + <img src="https://img.shields.io/badge/total%20lines-7k-red?style=flat-square"> |
| 15 | + </a> |
| 16 | + <a href="https://github.com/OSCPU"> |
| 17 | + <img src="https://img.shields.io/badge/test%20framework-verilator%20NEMU%20difftest-red?style=flat-square"> |
| 18 | + </a> |
| 19 | + <a href="./CONTRIBUTING.md"> |
| 20 | + <img src="https://img.shields.io/badge/contribution-welcome-brightgreen?style=flat-square"> |
9 | 21 | </a> |
10 | | - <img alt="stars" src="https://img.shields.io/github/stars/microdynamics-cpu/tree_core_cpu.svg" /> |
11 | | - <img alt="forks" src="https://img.shields.io/github/forks/microdynamics-cpu/tree_core_cpu.svg" /> |
12 | | - <img alt="version" src="https://img.shields.io/badge/version-1.0.0-FF69B4.svg" /> |
13 | | - <img alt="build" src="https://travis-ci.org/microdynamics-cpu/tree_core_cpu.svg?branch=main" /> |
14 | 22 | </p> |
15 | 23 |
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16 | | -<p align="center"> |
17 | | - <a href="./README.md">English</a>· |
18 | | - <a href="./README_zh-CN.md">简体中文</a> |
19 | | -</p> |
20 | 24 |
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21 | 25 | ## Overview |
22 | 26 | The TreeCore processors are the riscv64 software core developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021. |
23 | 27 |
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24 | 28 | Now the TreeCore has two version, TreeCoreL1(**_TreeCore Learning Core 1_**) and TreeCoreL2(**_TreeCore Learning Core 2_**). The TreeCore project is aim to help students to develop a series of riscv processor by step-to-step materials, So not just for high performance. Not like textbooks exhibit the all the knowledges in one time. TreeCore start a very simple model. provide necessary new concepts or knowledge you need to learn. |
25 | 29 |
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26 | 30 |
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| 31 | +## Motivation |
27 | 32 |
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28 | 33 | ## Feature |
29 | 34 | TreeCoreL1(**under development**) |
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