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The TreeCore processors are the riscv64 software core developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021.
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The TreeCore processors are the riscv64 cores developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021.
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Now the TreeCore has two version, TreeCoreL1(**_TreeCore Learning Core 1_**) and TreeCoreL2(**_TreeCore Learning Core 2_**). The TreeCore project is aim to help students to develop a series of riscv processor by step-to-step materials, So not just for high performance. Not like textbooks exhibit the all the knowledges in one time. TreeCore start a very simple model. provide necessary new concepts or knowledge you need to learn.
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Now the TreeCore has two version, TreeCoreL1(**_TreeCore Learning 1_**) and TreeCoreL2(**_TreeCore Learning 2_**). The TreeCore project is aim to help students to develop a series of riscv processor by step-to-step materials, So not just for high performance. Not like textbooks exhibit the all the knowledges in one time. TreeCore start a very simple model. provide necessary new concepts or knowledge you need to learn.
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## Motivation
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I heard the word **_RISCV_** first time in the second semester of my junior year(that is, the summer of 2016). My roommate participated in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISCV instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley. I felt that it was similar to the MIPS, so I didn't take it too seriously. But what is unexpected is that after just a few period of development, the RISCV has been supported by many Internet and semiconductor giants around the world, and more and more research institutions, start-ups begin to design their own proprietary processors based on it. Although now the performance and application of RISCV are still limited, **I believe RISCV will usher in a revolution that can change the old pattern in someday**.
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The ancients once said: **it’s always shallow on paper, and you must do it yourself**. For the learn of the computer architecture, there is no better way to realize it from scratch. So I started to collect materials from the Internet, and I found the learning threshold and cost is very high. In addition, in order to pursue the performance, some open-source CPU cores are very complex(such as using mulit-pipelines, multi-core processing, out-of-order execution technology, etc), it is very difficult for beginners to get started. So I decided to design a series of open source processors from scratch, which has **simple, understandable architecture, high-quality code with step-to-step tutorial**.
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I hope it can become a ABC project like Arduino and make more processor enthusiasts or computer related specialized students enter into the computer architecture field. In the future, under the mutual promotion of the software and hardware ecosystem, I believe more people will like CPU development and be willing to spend time on it.
@@ -73,29 +82,71 @@ Now, the develop schedule is recorded by the **Tencent Document**. You can click
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## Usage
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### Getting Started
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#### Enviroment setup(ubuntu 20.04 LTS)
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install verilator, mill and dep lib:
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### Enviroment Setup
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> NOTE: All of the components are installed under linux operation system. To gurantee the compatibility and stability, I strongly recommend using `ubuntu 20.04 LTS`.
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First, you need to install verilator, mill and dependency libraries:
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```bash
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make install
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make setup
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$ cd rtl
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$ make install
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```
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change the sim memory from 8G to 256MB. need to enter 'make menuconfig' and modify [Memory - Configuration]->[Memory size] to '0x10000000' manually.
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cd in root rtl dir
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Then, download and configuare all components from the github:
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```bash
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make nemuBuild
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make dramsim3Build
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make simpleTestBuild
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make riscvTestBuild
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make cpuTestBuild
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make amTestBuild
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$ make setup
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```
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After that, you need to set the `NEMU_HOME` and `NOOP_HOME` environment variables:
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```bash
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$ NEMU_HOME=$(pwd)/dependency/NEMU
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$ NOOP_HOME=$(pwd)/dependency
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```
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### Software test
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Becuase running the isa test don't need 8G memory, so you need to config the simulation memory size to reduce memory usage. You need to type `make menuconfig` as follow:
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```bash
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$ cd dependency/NEMU
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$ make menuconfig
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```
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> NOTE: if you encount `Your display is too small to run Menuconfig!` error, you need to resize the terminal to match need as the console output: `It must be at least 19 lines by 80 columns`.
Usually, 256MB memory address space is enough for simulation. You need to switch into `[Memory - Configuration]` menu and change `[Memory size]` value into `0x10000000` manually as follow picture shows. It can adjust difftest's simulation memory size from 8G to 256MB.
Last, remember to type `Save` button in bottom menu to save the `.config` file. Then, type `Exit` to exit the menuconfig.
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### Compile runtime libraries
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If you already run above steps correctly, you need to compile runtime libraries as follow:
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```bash
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$ make nemuBuild
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$ make dramsim3Build
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```
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### Recursive test
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When you modify the processor design, you
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```bash
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$ make riscvTestBuild
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$ make cpuTestBuild
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```
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### Software test
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```bash
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$ make amTestBuild
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```
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### SoC test
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### Hardware test
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## Summary
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## Documention
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## Plan
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## Update
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## License
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All of the TreeCore codes are release under the [GPL-3.0 License](LICENSE).
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## Story
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I heard the word **_RISCV_** first time in the second semester of my junior year(that is, the summer of 2016). My roommate participated in the pilot class of "Computer Architecture" organized by the college, and **their task was to design a simple soft-core CPU based on the RISCV instruction set**. At that time, I only knew that it was an open source RISC instruction set launched by the University of Berkeley. I felt that it was similar to the MIPS, so I didn't take it too seriously. But what is unexpected is that after just a few period of development, the RISCV has been supported by many Internet and semiconductor giants around the world, and more and more research institutions, start-ups begin to design their own proprietary processors based on it. Although now the performance and application of RISCV are still limited, **I believe RISCV will usher in a revolution that can change the old pattern in someday**.
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The ancients once said: **it’s always shallow on paper, and you must do it yourself**. For the learn of the computer architecture, there is no better way to realize it from scratch. So I started to collect materials from the Internet, and I found the learning threshold and cost is very high. In addition, in order to pursue the performance, some open-source CPU cores are very complex(such as using mulit-pipelines, multi-core processing, out-of-order execution technology, etc), it is very difficult for beginners to get started. So I decided to design a series of open source processors from scratch, which has **simple, understandable architecture, high-quality code with step-to-step tutorial**.
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I hope it can become a ABC project like Arduino and make more processor enthusiasts or computer related specialized students enter into the computer architecture field. In the future, under the mutual promotion of the software and hardware ecosystem, I believe more people will like CPU development and be willing to spend time on it.
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