feat: modify bpu connect

Author: maksyuki

rtl/tc_l2/src/main/scala/core/if/BPU.scala

@@ -25,7 +25,7 @@ class BPU extends Module {
   ghr.io.taken  := io.branchInfo.taken
 
   // G-share
-  protected val idx = io.lookupPc(ConstVal.GHRLen + ConstVal.AddrAlignLen - 1, ConstVal.AddrAlignLen) ^ ghr.io.idx
+  protected val idx = io.lookupPc(ConstVal.GHRLen - 1, 0) ^ ghr.io.idx
   pht.io.prevBranch := io.branchInfo.branch
   pht.io.prevTaken  := io.branchInfo.taken
   pht.io.prevIdx    := io.branchInfo.idx
@@ -39,7 +39,14 @@ class BPU extends Module {
   btb.io.lookupPc := io.lookupPc
 
   // wire output signals
-  io.predTaken := btb.io.lookupBranch && (pht.io.taken || btb.io.lookupJump)
-  io.predTgt   := btb.io.lookupTgt
-  io.predIdx   := idx
+  // now uncond jump is always no-taken to solve 'ret' inst return 'taken'
+  // when multiple sections call same function
+  when(btb.io.lookupJump) {
+    io.predTaken := false.B
+  }.otherwise {
+    io.predTaken := btb.io.lookupBranch && pht.io.taken
+  }
+  // io.predTaken := btb.io.lookupBranch && (pht.io.taken || btb.io.lookupJump)
+  io.predTgt := btb.io.lookupTgt
+  io.predIdx := idx
 }

rtl/tc_l2/src/main/scala/core/if/IFU.scala

@@ -3,23 +3,27 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
+import treecorel2.common.ConstVal
+
 class IFU extends Module {
   val io = IO(new Bundle {
-    val globalEn = Input(Bool())
-    val stall    = Input(Bool())
-    val socEn    = Input(Bool())
-    val fetch    = new IFIO
-    val if2id    = new IF2IDIO
-    val nxtPC    = Flipped(new NXTPCIO)
+    val globalEn   = Input(Bool())
+    val stall      = Input(Bool())
+    val socEn      = Input(Bool())
+    val branchInfo = Flipped(new BRANCHIO)
+    val fetch      = new IFIO
+    val if2id      = new IF2IDIO
+    val nxtPC      = Flipped(new NXTPCIO)
   })
 
   protected val startAddr = Mux(io.socEn, "h0000000030000000".U(64.W), "h0000000080000000".U(64.W))
   protected val valid     = Mux(reset.asBool(), false.B, true.B)
   protected val inst      = io.fetch.data
   protected val pc        = RegInit(startAddr)
 
-  // protected val bpu = Module(new BPU)
-  // bpu.io.in := 0.U
+  protected val bpu = Module(new BPU)
+  bpu.io.branchInfo <> io.branchInfo
+  bpu.io.lookupPc   := pc
 
   when(io.globalEn) {
     when(io.nxtPC.trap) {
@@ -28,15 +32,18 @@ class IFU extends Module {
       pc := io.nxtPC.mepc
     }.elsewhen(io.nxtPC.branch) {
       pc := io.nxtPC.tgt
+    }.elsewhen(bpu.io.predTaken) {
+      pc := bpu.io.predTgt
     }.otherwise {
       pc := pc + 4.U
     }
   }
 
-  io.if2id.valid := Mux(io.stall, false.B, valid)
-  io.if2id.inst  := inst
-  io.if2id.pc    := pc
-
+  io.if2id.valid     := Mux(io.stall, false.B, valid)
+  io.if2id.inst      := inst
+  io.if2id.pc        := pc
+  io.if2id.branIdx   := bpu.io.predIdx
+  io.if2id.predTaken := bpu.io.predTaken
   // comm with crossbar to get inst back
   io.fetch.en   := valid
   io.fetch.addr := pc