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maksyukimaksyuki
committed
style: modify some var's name
1 parent 119fbb1 commit c4e7f97

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8 files changed

+55
-63
lines changed

8 files changed

+55
-63
lines changed

‎rtl/tc_l2/src/main/scala/axi4/Crossbar.scala‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ class Crossbar extends Module with InstConfig {
1414
})
1515

1616
protected val globalEn = RegInit(false.B)
17-
protected val inst = RegInit(0.U(32.W))
17+
protected val inst = RegInit(0.U(InstLen.W))
1818
protected val rdInst = Mux(io.core.fetch.addr(2).asBool(), io.dxchg.rdata(63, 32), io.dxchg.rdata(31, 0))
1919

2020
io.core.globalEn := Mux(io.runEn, globalEn, false.B)
@@ -37,25 +37,25 @@ class Crossbar extends Module with InstConfig {
3737
when(io.runEn) {
3838
globalEn := false.B
3939
stateReg := eumInst
40-
inst := 0x13.U
40+
inst := NOPInst
4141
}
4242
}
4343
}
4444

4545
// because the difftest's logic addr is 0x000000
46-
protected val instSize = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
47-
protected val baseAddr = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
48-
protected val instAddr = io.core.fetch.addr - baseAddr
49-
protected val loadAddr = io.core.ld.addr - baseAddr
50-
protected val storeAddr = io.core.sd.addr - baseAddr
51-
protected val maEn = io.core.ld.en || io.core.sd.en
46+
protected val instSize = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
47+
protected val baseAddr = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
48+
protected val instAddr = io.core.fetch.addr - baseAddr
49+
protected val ldAddr = io.core.ld.addr - baseAddr
50+
protected val sdAddr = io.core.sd.addr - baseAddr
51+
protected val maEn = io.core.ld.en || io.core.sd.en
5252

5353
// prepare the data exchange io signals
5454
io.dxchg.ren := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
55-
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
55+
io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, ldAddr)
5656
io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
5757
io.dxchg.wen := stateReg === eumMem && io.core.sd.en
58-
io.dxchg.waddr := storeAddr
58+
io.dxchg.waddr := sdAddr
5959
io.dxchg.wdata := io.core.sd.data
6060
io.dxchg.wmask := io.core.sd.mask
6161
}

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ trait InstConfig {
1818
val InstDiffRSize = 3.U
1919
val DiffRWSize = 3.U
2020
val CacheEna = false
21-
21+
val NOPInst = 0x13.U
2222
// inst type
2323
// nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
2424
val InstTypeLen = 3
@@ -131,4 +131,8 @@ trait InstConfig {
131131
val medelegAddr = 0x302.U(CSRAddrLen.W)
132132
val timeCause = "h8000_0000_0000_0007".U(XLen.W)
133133
val ecallCause = "h0000_0000_0000_000b".U(XLen.W)
134+
135+
// special inst
136+
val customInst = "h0000007b".U(InstLen.W)
137+
val haltInst = "h0000006b".U(InstLen.W)
134138
}

‎rtl/tc_l2/src/main/scala/core/exec/EXU.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ class EXU extends Module with InstConfig {
7878
protected val ecallEn = csrReg.io.ecallEn
7979
csrReg.io.globalEn := io.globalEn
8080
csrReg.io.pc := pc
81-
csrReg.io.inst := Mux(valid, inst, 0x13.U)
81+
csrReg.io.inst := Mux(valid, inst, NOPInst)
8282
csrReg.io.src := src1
8383
csrReg.io.mtip := io.mtip
8484

‎rtl/tc_l2/src/main/scala/core/ma/CLINT.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2.common.{ConstVal, InstConfig}
6+
import treecorel2.common.InstConfig
77

88
class CLINT extends Module with InstConfig {
99
val io = IO(new Bundle {

‎rtl/tc_l2/src/main/scala/core/ma/LSU.scala‎

Lines changed: 28 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -7,54 +7,53 @@ import treecorel2.common.InstConfig
77

88
class LSU extends Module with InstConfig {
99
val io = IO(new Bundle {
10-
val valid = Input(Bool())
11-
val isa = Input(UInt(InstValLen.W))
12-
val src1 = Input(UInt(XLen.W))
13-
val src2 = Input(UInt(XLen.W))
14-
val imm = Input(UInt(XLen.W))
15-
val ld = new LDIO
16-
val sd = new SDIO
17-
val loadData = Output(UInt(XLen.W))
10+
val valid = Input(Bool())
11+
val isa = Input(UInt(InstValLen.W))
12+
val src1 = Input(UInt(XLen.W))
13+
val src2 = Input(UInt(XLen.W))
14+
val imm = Input(UInt(XLen.W))
15+
val ld = new LDIO
16+
val sd = new SDIO
17+
val ldData = Output(UInt(XLen.W))
1818
})
1919

2020
protected val ldInstVis = (io.isa === instLD) || (io.isa === instLW) || (io.isa === instLH) || (io.isa === instLB) || (io.isa === instLWU) || (io.isa === instLHU) || (io.isa === instLBU)
2121
protected val sdInstVis = (io.isa === instSD) || (io.isa === instSW) || (io.isa === instSH) || (io.isa === instSB)
2222

2323
io.ld.en := io.valid && ldInstVis
2424
io.ld.addr := io.src1 + io.imm
25-
protected val bSize = 0.U(3.W)
26-
protected val hSize = Mux((io.isa === instLH) || (io.isa === instLHU), 1.U, 0.U)
27-
protected val wSize = Mux((io.isa === instLW) || (io.isa === instLWU), 2.U, 0.U)
28-
protected val dSize = Mux((io.isa === instLD), 3.U, 0.U)
29-
protected val loadSize = bSize | hSize | wSize | dSize
30-
io.ld.size := loadSize
25+
26+
protected val ldSize = MuxLookup(
27+
io.isa,
28+
0.U(3.W),
29+
Seq(
30+
instLH -> 1.U(3.W),
31+
instLHU -> 1.U(3.W),
32+
instLW -> 2.U(3.W),
33+
instLWU -> 2.U(3.W),
34+
instLD -> 3.U(3.W)
35+
)
36+
)
37+
io.ld.size := ldSize
3138

3239
protected val dInstData = io.ld.data
3340
protected val wInstData = Mux(io.ld.addr(2).asBool(), dInstData(63, 32), dInstData(31, 0))
3441
protected val hTypeData = Mux(io.ld.addr(1).asBool(), wInstData(31, 16), wInstData(15, 0))
3542
protected val bTypeData = Mux(io.ld.addr(0).asBool(), hTypeData(15, 8), hTypeData(7, 0))
3643

37-
io.loadData := MuxLookup(
44+
io.ldData := MuxLookup(
3845
io.isa,
3946
0.U(XLen.W),
4047
Seq(
4148
instLD -> dInstData,
42-
instLW -> (SignExt(wInstData, 64)),
43-
instLH -> (SignExt(hTypeData, 64)),
44-
instLB -> (SignExt(bTypeData, 64)),
45-
instLWU -> (ZeroExt(wInstData, 64)),
46-
instLHU -> (ZeroExt(hTypeData, 64)),
47-
instLBU -> (ZeroExt(bTypeData, 64))
49+
instLW -> (SignExt(wInstData, XLen)),
50+
instLH -> (SignExt(hTypeData, XLen)),
51+
instLB -> (SignExt(bTypeData, XLen)),
52+
instLWU -> (ZeroExt(wInstData, XLen)),
53+
instLHU -> (ZeroExt(hTypeData, XLen)),
54+
instLBU -> (ZeroExt(bTypeData, XLen))
4855
)
4956
)
50-
// protected val ldData = SignExt(io.isa.LD.asUInt, 64) & dInstData
51-
// protected val lwData = SignExt(io.isa.LW.asUInt, 64) & (SignExt(wInstData, 64))
52-
// protected val lhData = SignExt(io.isa.LH.asUInt, 64) & (SignExt(hTypeData, 64))
53-
// protected val lbData = SignExt(io.isa.LB.asUInt, 64) & (SignExt(bTypeData, 64))
54-
// protected val lwuData = SignExt(io.isa.LWU.asUInt, 64) & (ZeroExt(wInstData, 64))
55-
// protected val lhuData = SignExt(io.isa.LHU.asUInt, 64) & (ZeroExt(hTypeData, 64))
56-
// protected val lbuData = SignExt(io.isa.LBU.asUInt, 64) & (ZeroExt(bTypeData, 64))
57-
// io.loadData := ldData | lwData | lhData | lbData | lwuData | lhuData | lbuData
5857

5958
// store signals
6059
io.sd.en := io.valid && sdInstVis
@@ -69,11 +68,6 @@ class LSU extends Module with InstConfig {
6968
instSB -> Cat(io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0))
7069
)
7170
)
72-
// protected val sdData = SignExt(io.isa.SD.asUInt, 64) & io.src2
73-
// protected val swData = SignExt(io.isa.SW.asUInt, 64) & Cat(io.src2(31, 0), io.src2(31, 0))
74-
// protected val shData = SignExt(io.isa.SH.asUInt, 64) & Cat(io.src2(15, 0), io.src2(15, 0), io.src2(15, 0), io.src2(15, 0))
75-
// protected val sbData = SignExt(io.isa.SB.asUInt, 64) & Cat(io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0), io.src2(7, 0))
76-
// protected val storeData = sdData | swData | shData | sbData
7771

7872
protected val sdMask = MuxLookup(
7973
io.isa,
@@ -86,12 +80,6 @@ class LSU extends Module with InstConfig {
8680
)
8781
)
8882

89-
// protected val dInstMask = SignExt(io.isa.SD.asUInt, 8) & "b1111_1111".U(8.W)
90-
// protected val wInstMask = SignExt(io.isa.SW.asUInt, 8) & ("b0000_1111".U(8.W) << io.sd.addr(2, 0))
91-
// protected val hInstMask = SignExt(io.isa.SH.asUInt, 8) & ("b0000_0011".U(8.W) << io.sd.addr(2, 0))
92-
// protected val bInstMask = SignExt(io.isa.SB.asUInt, 8) & ("b0000_0001".U(8.W) << io.sd.addr(2, 0))
93-
// protected val sdMask = dInstMask | wInstMask | hInstMask | bInstMask
94-
9583
protected val sdMask0 = Mux(sdMask(0).asBool(), "hff".U(8.W), 0.U(8.W))
9684
protected val sdMask1 = Mux(sdMask(1).asBool(), "hff".U(8.W), 0.U(8.W))
9785
protected val sdMask2 = Mux(sdMask(2).asBool(), "hff".U(8.W), 0.U(8.W))

‎rtl/tc_l2/src/main/scala/core/ma/MAU.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ class MAU extends Module {
2929
lsu.io.src1 := src1
3030
lsu.io.src2 := src2
3131
lsu.io.imm := imm
32-
protected val loadData = lsu.io.loadData
32+
protected val ldData = lsu.io.ldData
3333

3434
protected val clint = Module(new CLINT)
3535
clint.io.valid := valid
@@ -44,7 +44,7 @@ class MAU extends Module {
4444
// bypass path
4545
io.bypassMem.wen := Mux(isLoad, true.B, memReg.wen) && valid
4646
io.bypassMem.wdest := Mux(isLoad, memReg.wdest, memReg.wdest)
47-
io.bypassMem.data := Mux(isLoad, loadData, memWbdata)
47+
io.bypassMem.data := Mux(isLoad, ldData, memWbdata)
4848

4949
io.mem2wb.valid := valid
5050
io.mem2wb.inst := inst
@@ -63,7 +63,7 @@ class MAU extends Module {
6363
io.mem2wb.link := memReg.link
6464
io.mem2wb.auipc := memReg.auipc
6565
io.mem2wb.csrData := memReg.csrData
66-
io.mem2wb.loadData := loadData
66+
io.mem2wb.ldData := ldData
6767
io.mem2wb.cvalid := clint.io.cvalid
6868
io.mem2wb.timeIntrEn := memReg.timeIntrEn
6969
io.mem2wb.ecallEn := memReg.ecallEn

‎rtl/tc_l2/src/main/scala/core/wb/WBU.scala‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ import chisel3.util._
55

66
import difftest._
77

8-
import treecorel2.common.{ConstVal, InstConfig}
8+
import treecorel2.common.InstConfig
99

1010
class WBU extends Module with InstConfig {
1111
val io = IO(new Bundle {
@@ -26,20 +26,20 @@ class WBU extends Module with InstConfig {
2626
protected val aluRes = wbReg.aluRes
2727
protected val link = wbReg.link
2828
protected val auipc = wbReg.auipc
29-
protected val loadData = wbReg.loadData
29+
protected val ldData = wbReg.ldData
3030
protected val csrData = wbReg.csrData
3131
protected val cvalid = wbReg.cvalid
3232
protected val timeIntrEn = wbReg.timeIntrEn
3333
protected val csr = wbReg.csr
3434

35-
protected val wbdata = aluRes | link | auipc | loadData | csrData
35+
protected val wbdata = aluRes | link | auipc | ldData | csrData
3636

3737
io.wbdata.wen := valid && wen
3838
io.wbdata.wdest := wdest
3939
io.wbdata.data := wbdata
4040

41-
protected val printVis = inst(6, 0) === "h7b".U(7.W)
42-
protected val haltVis = inst(6, 0) === "h6b".U(7.W)
41+
protected val printVis = inst === customInst
42+
protected val haltVis = inst === haltInst
4343

4444
when(~io.socEn) {
4545
when(io.globalEn && valid && printVis) {

‎rtl/tc_l2/src/main/scala/port/MEM2WBIO.scala‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,6 @@ import chisel3._
44
import chisel3.util._
55

66
class MEM2WBIO extends EX2MEMIO {
7-
val loadData = Output(UInt(64.W))
8-
val cvalid = Output(Bool())
7+
val ldData = Output(UInt(64.W))
8+
val cvalid = Output(Bool())
99
}

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