style: add common config

Author: maksyuki

rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala

@@ -25,10 +25,10 @@ class AXI4Bridge extends Module with AXI4Config {
   arbiter.io.rHdShk   := io.axi.r.fire()
 
   protected val wMask     = arbiter.io.dxchg.wmask
-  protected val bitCnt    = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
+  protected val byteSize  = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
   protected val socARSize = arbiter.io.dxchg.rsize
   protected val socAWSize = MuxLookup(
-    bitCnt,
+    byteSize,
     0.U,
     Array(
       8.U -> 3.U,

rtl/tc_l2/src/main/scala/axi4/Crossbar.scala

@@ -3,7 +3,9 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class Crossbar extends Module {
+import treecorel2.common.InstConfig
+
+class Crossbar extends Module with InstConfig {
   val io = IO(new Bundle {
     val socEn = Input(Bool())
     val runEn = Input(Bool())
@@ -26,34 +28,34 @@ class Crossbar extends Module {
   switch(stateReg) {
     is(eumInst) {
       when(io.runEn) {
-        stateReg := eumMem
         globalEn := true.B
+        stateReg := eumMem
         inst     := rdInst
       }
     }
     is(eumMem) {
       when(io.runEn) {
-        stateReg := eumInst
         globalEn := false.B
+        stateReg := eumInst
         inst     := 0x13.U
       }
     }
   }
 
-  protected val instSize = Mux(io.socEn, 2.U, 3.U)
   // because the difftest's logic addr is 0x000000
-  protected val addrOffset = Mux(io.socEn, "h0000000000000000".U(64.W), "h0000000080000000".U(64.W))
-
-  protected val instAddr  = io.core.fetch.addr - addrOffset
-  protected val loadAddr  = io.core.ld.addr - addrOffset
-  protected val storeAddr = io.core.sd.addr - addrOffset
+  protected val instSize  = Mux(io.socEn, instSoCRSize, instDiffRSize)
+  protected val baseAddr  = Mux(io.socEn, socStartBaseAddr, socStartBaseAddr)
+  protected val instAddr  = io.core.fetch.addr - baseAddr
+  protected val loadAddr  = io.core.ld.addr - baseAddr
+  protected val storeAddr = io.core.sd.addr - baseAddr
   protected val maEn      = io.core.ld.en || io.core.sd.en
 
+  // prepare the data exchange io signals
   io.dxchg.ren   := ((stateReg === eumInst) || (stateReg === eumMem && maEn))
   io.dxchg.raddr := Mux(stateReg === eumInst, instAddr, loadAddr)
   io.dxchg.rsize := Mux(stateReg === eumMem && io.core.ld.en, io.core.ld.size, instSize)
+  io.dxchg.wen   := stateReg === eumMem && io.core.sd.en
   io.dxchg.waddr := storeAddr
   io.dxchg.wdata := io.core.sd.data
   io.dxchg.wmask := io.core.sd.mask
-  io.dxchg.wen   := stateReg === eumMem && io.core.sd.en
 }

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -4,17 +4,21 @@ import chisel3._
 import chisel3.util._
 
 trait InstConfig {
-  val SoCEna = false
+  val SoCEna            = false
+  val XLen              = 64
+  val diffStartBaseAddr = "h0000000080000000".U(XLen.W)
+  val socStartBaseAddr  = "h0000000000000000".U(XLen.W)
+  val difftestAddrMask  = "hfffffffffffffff8".U(XLen.W)
+  val socAddrMask       = "hffffffffffffffff".U(XLen.W)
+  val instSoCRSize      = 2.U
+  val instDiffRSize     = 3.U
+  val diffRWSize        = 3.U
+  val CacheEna          = false
 
-  val difftestAddrMask = "hfffffffffffffff8".U(64.W)
-  val socAddrMask      = "hffffffffffffffff".U(64.W)
-  val diffRWSize       = 3.U
-  val CacheEna         = false
-  val XLen             = 64
-  val NWay             = 4
-  val NBank            = 4
-  val NSet             = 32
-  val CacheLineSize    = 64 * NBank
-  val ICacheSize       = NWay * NSet * CacheLineSize
-  val DCacheSize       = NWay * NSet * CacheLineSize
+  val NWay          = 4
+  val NBank         = 4
+  val NSet          = 32
+  val CacheLineSize = XLen * NBank
+  val ICacheSize    = NWay * NSet * CacheLineSize
+  val DCacheSize    = NWay * NSet * CacheLineSize
 }