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maksyukimaksyuki
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feat: change inst axi oper in 0x8000_0000 higher addr
1 parent b71a2db commit fbd4a99

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2 files changed

+72
-31
lines changed

2 files changed

+72
-31
lines changed

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 71 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -258,6 +258,20 @@ class AXI4Bridge() extends Module with AXI4Config {
258258
rdStateReg := eumIfRDwithMemIDLE
259259
}
260260
}
261+
}.otherwise {
262+
switch(rdStateReg) {
263+
is(eumIfRDwithMemIDLE) {
264+
// printf("[axi] if-rd mem-idle!!!!!!!!!!!!!!!!!!!!\n")
265+
// printf(p"[axi] io.axi.aw.bits.len = 0x${Hexadecimal(io.axi.aw.bits.len)}\n")
266+
when(io.mem.valid && memRdTrans && (~instRdDone)) {
267+
rdStateReg := eumIfRDwithMemAR
268+
}.elsewhen((~(io.mem.valid && memRdTrans)) && instRdDone) {
269+
rdStateReg := eumRdIDLE
270+
}.elsewhen(io.mem.valid && memRdTrans && instRdDone) {
271+
rdStateReg := eumIfIDLEwithMemAR
272+
}
273+
}
274+
}
261275
}
262276

263277
protected val instTransLen = RegInit(0.U(8.W))
@@ -271,24 +285,23 @@ class AXI4Bridge() extends Module with AXI4Config {
271285
instTransLen := instTransLen + 1.U
272286
}
273287

274-
protected val ALIGNED_INST_WIDTH = log2Ceil(AxiInstDataWidth / 8)
275-
protected val OFFSET_INST_WIDTH = log2Ceil(AxiInstDataWidth)
276-
protected val MASK_INST_WIDTH = AxiInstDataWidth * 2
277-
protected val AXI_INST_SIZE = if (SoCEna) 2.U else 3.U // because the flash only support 4 bytes access
278-
protected val TRANS_LEN = 1
288+
protected val ALIGNED_INST_WIDTH = log2Ceil(AxiDataWidth / 8)
289+
protected val OFFSET_INST_WIDTH = log2Ceil(AxiDataWidth)
290+
protected val MASK_INST_WIDTH = AxiDataWidth * 2
291+
protected val AXI_INST_SIZE = 3.U
292+
protected val ALIGNED_FLASH_INST_WIDTH = log2Ceil(AxiFlashDataWidth / 8)
293+
protected val OFFSET_FLASH_INST_WIDTH = log2Ceil(AxiFlashDataWidth)
294+
protected val MASK_FLASH_INST_WIDTH = AxiFlashDataWidth * 2
295+
protected val AXI_FLASH_INST_SIZE = 2.U // because the flash only support 4 bytes access
296+
protected val TRANS_LEN = 1
279297

280298
// no-aligned visit
281-
protected val instTransAligned = WireDefault(io.inst.addr(ALIGNED_INST_WIDTH - 1, 0) === 0.U)
299+
protected val instTransAligned = Wire(Bool())
282300
protected val instSizeByte = WireDefault(io.inst.size === AXI4Bridge.SIZE_B)
283301
protected val instSizeHalf = WireDefault(io.inst.size === AXI4Bridge.SIZE_H)
284302
protected val instSizeWord = WireDefault(io.inst.size === AXI4Bridge.SIZE_W)
285303
protected val instSizeDouble = WireDefault(io.inst.size === AXI4Bridge.SIZE_D)
286-
// opa: 0xxx
287-
// opb: b: 0000
288-
// h: 0001
289-
// w: 0011
290-
// d: 0111
291-
protected val instAddrOpA = WireDefault(UInt(4.W), Cat(0.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)))
304+
protected val instAddrOpA = Wire(UInt(4.W))
292305
protected val instAddrOpB = WireDefault(
293306
UInt(4.W),
294307
(Fill(4, instSizeByte) & "b0000".U(4.W))
@@ -298,45 +311,68 @@ class AXI4Bridge() extends Module with AXI4Config {
298311
)
299312

300313
protected val instAddrEnd = WireDefault(UInt(4.W), instAddrOpA + instAddrOpB)
301-
protected val instOverstep = WireDefault(instAddrEnd(3, ALIGNED_INST_WIDTH) =/= 0.U)
302-
protected val instAxiSize = AXI_INST_SIZE
314+
protected val instOverstep = Wire(Bool())
315+
protected val instAxiSize = Wire(UInt(3.W))
303316
protected val instAxiAddr = Wire(UInt(AxiAddrWidth.W))
304317
protected val instAlignedOffsetLow = Wire(UInt(OFFSET_INST_WIDTH.W))
305318
protected val instAlignedOffsetHig = Wire(UInt(OFFSET_INST_WIDTH.W))
306319
protected val instMask = Wire(UInt(MASK_INST_WIDTH.W))
307320

308-
instAxiAddr := Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_INST_WIDTH), Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)))
309-
instAxiLen := Mux(instTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), instOverstep))
310-
instAlignedOffsetLow := Cat(OFFSET_INST_WIDTH.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)) << 3
311-
instAlignedOffsetHig := AxiInstDataWidth.U - instAlignedOffsetLow
321+
instAxiLen := Mux(instTransAligned.asBool(), (TRANS_LEN - 1).U, Cat(Fill(7, "b0".U(1.W)), instOverstep))
312322
instMask := (
313323
(Fill(MASK_INST_WIDTH, instSizeByte) & Cat(Fill(8, "b0".U(1.W)), "hff".U(8.W)))
314324
| (Fill(MASK_INST_WIDTH, instSizeHalf) & Cat(Fill(16, "b0".U(1.W)), "hffff".U(16.W)))
315325
| (Fill(MASK_INST_WIDTH, instSizeWord) & Cat(Fill(32, "b0".U(1.W)), "hffffffff".U(32.W)))
316326
| (Fill(MASK_INST_WIDTH, instSizeDouble) & Cat(Fill(64, "b0".U(1.W)), "hffffffff_ffffffff".U(64.W)))
317327
) << instAlignedOffsetLow
318328

319-
protected val instMaskLow = instMask(AxiInstDataWidth - 1, 0)
320-
protected val instMaskHig = instMask(MASK_INST_WIDTH - 1, AxiInstDataWidth)
329+
protected val instMaskLow = Wire(UInt(AxiDataWidth.W))
330+
protected val instMaskHig = Wire(UInt(AxiDataWidth.W))
321331
protected val instAxiUser = WireDefault(UInt(AxiUserLen.W), Fill(AxiUserLen, "b0".U(1.W)))
322332
protected val instReady = RegInit(false.B)
323333
protected val instReadyNxt = WireDefault(instTransDone)
324334
protected val instReadyEna = WireDefault(instTransDone || instReady)
335+
protected val instResp = RegInit(0.U(2.W))
336+
protected val instRespNxt = io.axi.r.bits.resp
337+
protected val instRespEna = WireDefault(instTransDone)
325338

326339
when(instReadyEna) {
327340
instReady := instReadyNxt
328341
}
329342
io.inst.ready := instReady
330343

331-
protected val instResp = RegInit(0.U(2.W))
332-
protected val instRespNxt = io.axi.r.bits.resp
333-
protected val instRespEna = WireDefault(instTransDone)
334-
335344
when(instRespEna) {
336345
instResp := instRespNxt
337346
}
338347
io.inst.resp := instResp
339348

349+
when(
350+
(io.inst.addr >= UartBaseAddr && io.inst.addr <= UartBoundAddr) ||
351+
(io.inst.addr >= SpiBaseAddr && io.inst.addr <= SpiBoundAddr) ||
352+
(io.inst.addr >= FlashBaseAddr && io.inst.addr <= FlashBoundAddr) ||
353+
(io.inst.addr >= ChiplinkBaseAddr && io.inst.addr <= ChiplinkBoundAddr)
354+
) {
355+
instTransAligned := io.inst.addr(ALIGNED_FLASH_INST_WIDTH - 1, 0) === 0.U
356+
instAddrOpA := Cat(0.U, io.inst.addr(ALIGNED_FLASH_INST_WIDTH - 1, 0))
357+
instOverstep := instAddrEnd(3, ALIGNED_FLASH_INST_WIDTH) =/= 0.U
358+
instAxiSize := AXI_FLASH_INST_SIZE
359+
instAxiAddr := Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_FLASH_INST_WIDTH), Fill(ALIGNED_FLASH_INST_WIDTH, "b0".U(1.W)))
360+
instAlignedOffsetLow := Cat(io.inst.addr(ALIGNED_FLASH_INST_WIDTH - 1, 0), 0.U, 0.U, 0.U)
361+
instAlignedOffsetHig := AxiFlashDataWidth.U - instAlignedOffsetLow
362+
instMaskLow := instMask(AxiFlashDataWidth - 1, 0)
363+
instMaskHig := instMask(MASK_FLASH_INST_WIDTH - 1, AxiFlashDataWidth)
364+
}.otherwise {
365+
instTransAligned := io.inst.addr(ALIGNED_INST_WIDTH - 1, 0) === 0.U
366+
instAddrOpA := Cat(0.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0))
367+
instOverstep := instAddrEnd(3, ALIGNED_INST_WIDTH) =/= 0.U
368+
instAxiSize := AXI_INST_SIZE
369+
instAxiAddr := Cat(io.inst.addr(AxiAddrWidth - 1, ALIGNED_INST_WIDTH), Fill(ALIGNED_INST_WIDTH, "b0".U(1.W)))
370+
instAlignedOffsetLow := Cat(OFFSET_INST_WIDTH.U, io.inst.addr(ALIGNED_INST_WIDTH - 1, 0)) << 3
371+
instAlignedOffsetHig := AxiDataWidth.U - instAlignedOffsetLow
372+
instMaskLow := instMask(AxiDataWidth - 1, 0)
373+
instMaskHig := instMask(MASK_INST_WIDTH - 1, AxiDataWidth)
374+
}
375+
340376
// ================================mem================================
341377
protected val memTransLen = RegInit(0.U(8.W))
342378
protected val memTransLenReset = WireDefault(this.reset.asBool() || (wtTrans && wtStateIdle) || (memRdTrans && rdStateIdle))
@@ -466,16 +502,15 @@ class AXI4Bridge() extends Module with AXI4Config {
466502
protected val memReady = RegInit(false.B)
467503
protected val memReadyNxt = WireDefault(memTransDone)
468504
protected val memReadyEna = WireDefault(memTransDone || memReady)
505+
protected val memResp = RegInit(0.U(2.W))
506+
protected val memRespNxt = Mux(wtTrans, io.axi.b.bits.resp, io.axi.r.bits.resp)
507+
protected val memRespEna = WireDefault(memTransDone)
469508

470509
when(memReadyEna) {
471510
memReady := memReadyNxt
472511
}
473512
io.mem.ready := memReady
474513

475-
protected val memResp = RegInit(0.U(2.W))
476-
protected val memRespNxt = Mux(wtTrans, io.axi.b.bits.resp, io.axi.r.bits.resp)
477-
protected val memRespEna = WireDefault(memTransDone)
478-
479514
when(memRespEna) {
480515
memResp := memRespNxt
481516
}
@@ -524,8 +559,14 @@ class AXI4Bridge() extends Module with AXI4Config {
524559
io.axi.b.ready := wtStateResp
525560

526561
// Read address channel signals
527-
io.axi.ar.valid := rdIfARwithMemIDLE || rdIfIDLEwithMemAR || rdIfRDwithMemAR || rdIfARwithMemRD
528-
io.axi.ar.bits.addr := (Fill(AxiAddrWidth, rdIfARwithMemIDLE || rdIfARwithMemRD) & instAxiAddr) | (Fill(AxiAddrWidth, rdIfIDLEwithMemAR || rdIfRDwithMemAR) & memAxiAddr)
562+
io.axi.ar.valid := rdIfARwithMemIDLE || rdIfIDLEwithMemAR || rdIfRDwithMemAR || rdIfARwithMemRD
563+
// loader: 0x8000_0000~0x8xxxx_xxxx program is loaded from flash
564+
// when(loaderReg && (rdIfARwithMemIDLE || rdIfARwithMemRD) && io.inst.addr >= "h8000_0004".U) {
565+
// io.axi.ar.bits.addr := instAxiAddr + 4.U
566+
// }.otherwise {
567+
io.axi.ar.bits.addr := (Fill(AxiAddrWidth, rdIfARwithMemIDLE || rdIfARwithMemRD) & instAxiAddr) | (Fill(AxiAddrWidth, rdIfIDLEwithMemAR || rdIfRDwithMemAR) & memAxiAddr)
568+
// }
569+
529570
io.axi.ar.bits.id := (Fill(AxiIdLen, rdIfARwithMemIDLE || rdIfARwithMemRD) & instAxiId) | (Fill(AxiIdLen, rdIfIDLEwithMemAR || rdIfRDwithMemAR) & memAxiId)
530571
io.axi.ar.bits.len := (Fill(8, rdIfARwithMemIDLE || rdIfARwithMemRD) & instAxiLen) | (Fill(8, rdIfIDLEwithMemAR || rdIfRDwithMemAR) & memAxiLen)
531572
io.axi.ar.bits.size := (Fill(3, rdIfARwithMemIDLE || rdIfARwithMemRD) & instAxiSize) | (Fill(3, rdIfIDLEwithMemAR || rdIfRDwithMemAR) & memAxiSize)

‎rtl/tc_l2/src/main/scala/common/AXI4Config.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ trait AXI4Config extends InstConfig {
1010
val AxiReqNop = 2
1111

1212
val AxiDataWidth = 64
13-
val AxiInstDataWidth = if (SoCEna) 32 else 64
13+
val AxiFlashDataWidth = 32
1414
val AxiPerifDataWidth = 32
1515
val AxiAddrWidth = 32 // FIME: is right? the original val is 64
1616
val AxiProtLen = 3

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