From ed297eab60563dcb8b53abb76e8878dee22c7134 Mon Sep 17 00:00:00 2001 From: tlhonmey Date: Sun, 24 Oct 2021 02:30:55 +0000 Subject: [PATCH] Adjust stepping and CPU map to eschew rewiring. Very simple really, GRBL does its step timing calculations and scheduling on one set of bitmasks, therefore in the original setup, all GPIO pins for each operation must be on the same port. However, it is simple enough to create the bitmask as 32-bits wide, let GRBL do all its math, and then split it in half and write it to two separate ports as necessary. --- README.md | 4 +++- grbl/cpu_map.h | 22 ++++++++++++++++------ grbl/grbl.h | 2 +- grbl/planner.h | 2 +- grbl/stepper.c | 32 ++++++++++++++++++++++---------- 5 files changed, 43 insertions(+), 19 deletions(-) diff --git a/README.md b/README.md index c1585ab6..42ba5465 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,9 @@ this is my fork of usbcnc for STM32F103 specially for board in my chinnese machi ![Board](https://github.com/mirecta/grbl/blob/edge/doc/media/usbmach_pins.jpg?raw=true) -U must remove three capacitors and solder 3 wires, because this would recquire masive sw patches , so better is patch with three wires +NOTE: On my usbmach v2.0 the SWD pin order, left to right as pictured below, is actually VCC,GND,SWDIO,SWCLK Once I figured that out (with the STM32 chip pinout and a multimeter) it programmed just fine with an ST-LINK V2 and STM32CubeProgrammer + +Ignore the wire patch lines, that is no longer necessary. ![patch](https://github.com/mirecta/grbl/blob/edge/doc/media/usbmach_patch.jpg?raw=true) diff --git a/grbl/cpu_map.h b/grbl/cpu_map.h index 179fca86..8d78b054 100644 --- a/grbl/cpu_map.h +++ b/grbl/cpu_map.h @@ -285,20 +285,30 @@ #ifdef CPU_MAP_STM32F103 - // Define step pulse output pins. NOTE: All step bit pins must be on the same port. + // Define step pulse output pins. NOTE: All step bit pins must be on the same port... Or must they? + // Attempt to split potential pins onto two ports without mucking about with the rest of the code for STM32... + // This could be tricky... +#define H_PORT_OFFSET 16 +#define L_PORT_MASK 0xFFFF //Sorry, too tired to bother with deriving one from the other. You get what you pay for. #define STEP_PORT GPIOB #define RCC_STEP_PORT RCC_APB2Periph_GPIOB -#define X_STEP_BIT 7 -#define Y_STEP_BIT 5 +#define H_STEP_PORT GPIOA //We're going to stack the pins on the A controller to the +#define H_RCC_STEP_PORT RCC_APB2Periph_GPIOA //left of the pins on the B controller +#define X_STEP_BIT ( 5 + H_PORT_OFFSET ) +#define Y_STEP_BIT ( 7 + H_PORT_OFFSET ) #define Z_STEP_BIT 1 #define A_STEP_BIT 11 #define B_STEP_BIT 14 #define STEP_MASK ((1<> H_PORT_OFFSET) ) | ((st.dir_outbits & DIRECTION_MASK) >> H_PORT_OFFSET )); TIM_ClearITPendingBit(TIM3, TIM_IT_Update); #endif @@ -477,7 +478,8 @@ void Timer1Proc() STEP_PORT = (STEP_PORT & ~STEP_MASK) | st.step_outbits; #endif #ifdef STM32F103C8 - GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~STEP_MASK) | st.step_outbits); + GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~(STEP_MASK & L_PORT_MASK) ) | (st.step_outbits) & L_PORT_MASK ); + GPIO_Write(H_STEP_PORT, (GPIO_ReadOutputData(H_STEP_PORT) & ~(STEP_MASK >> H_PORT_OFFSET) ) | (st.step_outbits >> H_PORT_OFFSET) ); #endif #endif @@ -702,7 +704,8 @@ void Timer0Proc() TIM3->SR &= ~(1<<0); // clear UIF flag TIM3->CNT = 0; NVIC_DisableIRQ(TIM3_IRQn); - GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~STEP_MASK) | (step_port_invert_mask & STEP_MASK)); + GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~(STEP_MASK & L_PORT_MASK) ) | ((step_port_invert_mask & STEP_MASK) & L_PORT_MASK)); + GPIO_Write(H_STEP_PORT, (GPIO_ReadOutputData(H_STEP_PORT) & ~(STEP_MASK >> H_PORT_OFFSET) ) | ((step_port_invert_mask & STEP_MASK) >> H_PORT_OFFSET)); } #endif #ifdef AVRTARGET @@ -765,8 +768,11 @@ void st_reset() DIRECTION_PORT = (DIRECTION_PORT & ~DIRECTION_MASK) | dir_port_invert_mask; #endif #ifdef STM32F103C8 - GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~STEP_MASK) | (step_port_invert_mask & STEP_MASK)); - GPIO_Write(DIRECTION_PORT, (GPIO_ReadOutputData(DIRECTION_PORT) & ~DIRECTION_MASK) | (dir_port_invert_mask & DIRECTION_MASK)); + GPIO_Write(STEP_PORT, (GPIO_ReadOutputData(STEP_PORT) & ~(STEP_MASK & L_PORT_MASK) ) | ((step_port_invert_mask & STEP_MASK) & L_PORT_MASK)); + GPIO_Write(H_STEP_PORT, (GPIO_ReadOutputData(H_STEP_PORT) & ~(STEP_MASK >> H_PORT_OFFSET) ) | ((step_port_invert_mask & STEP_MASK) >> H_PORT_OFFSET)); + + GPIO_Write(DIRECTION_PORT, (GPIO_ReadOutputData(DIRECTION_PORT) & ~(DIRECTION_MASK & L_PORT_MASK) ) | ((dir_port_invert_mask & DIRECTION_MASK) & L_PORT_MASK)); + GPIO_Write(H_DIRECTION_PORT, (GPIO_ReadOutputData(H_DIRECTION_PORT) & ~(DIRECTION_MASK >> H_PORT_OFFSET) ) | ((dir_port_invert_mask & DIRECTION_MASK) >> H_PORT_OFFSET)); #endif } @@ -813,7 +819,7 @@ void Timer0Thread(void *pVoid) void stepper_init() { // Configure step and direction interface pins -#ifdef STM32F103C8 +#ifdef STM32F103C8 GPIO_InitTypeDef GPIO_InitStructure; RCC_APB2PeriphClockCmd(RCC_STEPPERS_DISABLE_PORT, ENABLE); GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; @@ -822,12 +828,18 @@ void stepper_init() GPIO_Init(STEPPERS_DISABLE_PORT, &GPIO_InitStructure); RCC_APB2PeriphClockCmd(RCC_STEP_PORT, ENABLE); - GPIO_InitStructure.GPIO_Pin = STEP_MASK; + RCC_APB2PeriphClockCmd(H_RCC_STEP_PORT, ENABLE); + GPIO_InitStructure.GPIO_Pin = STEP_MASK & L_PORT_MASK; GPIO_Init(STEP_PORT, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = STEP_MASK >> H_PORT_OFFSET; + GPIO_Init(H_STEP_PORT, &GPIO_InitStructure); RCC_APB2PeriphClockCmd(RCC_DIRECTION_PORT, ENABLE); - GPIO_InitStructure.GPIO_Pin = DIRECTION_MASK; + RCC_APB2PeriphClockCmd(H_RCC_DIRECTION_PORT, ENABLE); + GPIO_InitStructure.GPIO_Pin = DIRECTION_MASK & L_PORT_MASK; GPIO_Init(DIRECTION_PORT, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = DIRECTION_MASK >> H_PORT_OFFSET; + GPIO_Init(H_DIRECTION_PORT, &GPIO_InitStructure); RCC->APB1ENR |= RCC_APB1Periph_TIM2; TIM_Configuration(TIM2, 1, 1, 1);