BRK sets I flag a half cycle earlier than in visual6502

[szabadulas]

The BRK instruction in perfect6502 sets the I flag a half cycle earlier than in visual6502. perfect6502 does it in phase 2 of the PCL-loading cycle, while visual6502 does it in phase 1 of the PCH-loading cycle (cycle 8, phase 1 in this simulation). The C code below shows what perfect6502 does.

I don't know if the difference in simulation is crucial; I certainly did not expect it, though.

TEST.c:

#include <stdio.h>
#include "types.h"
#include "perfect6502.h"
#include "netlist_sim.h"

int main(void)
{
    memory[0] = 0x58; /* CLI */
    memory[1] = 0x00; /* BRK */

    state_t *state = initAndResetChip();

    /* Cycle through the loading of the RESET vector. */
    for (int i = 0; i < 16; i++)
        step(state);

    printf("-- Fetching CLI:\n");
    for (int i = 0; i < 2; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing CLI:\n");
    for (int i = 0; i < 4; i++) {
        step(state);
        chipStatus(state);
    }

    printf("-- Executing BRK (I flag cleared above [node p2=%d]):\n", isNodeHigh(state, 1421));
    for (int i = 0; i < 10; i++) {
        step(state);
        chipStatus(state);
    }

    printf("   perfect6502 sets I in phase 2 of PCL-loading cycle, -------------^^\n");
    printf("   but visual6502 sets I in phase 1 of PCH-loading cycle (below).\n");
    for (int i = 0; i < 2; i++) {
        step(state);
        chipStatus(state);
    }

    destroyChip(state);
    return 0;
}

$ gcc -Wall -o TEST TEST.c perfect6502.c netlist_sim.c

$ ./TEST output:

-- Fetching CLI:
halfcyc:17 phi0:0 AB:0000 D:00 RnW:1 PC:0000 A:00 X:C0 Y:00 SP:BD P:16 IR:00
halfcyc:18 phi0:1 AB:0000 D:58 RnW:1 PC:0000 A:00 X:C0 Y:00 SP:BD P:16 IR:00 R$0000=$58
-- Executing CLI:
halfcyc:19 phi0:0 AB:0001 D:58 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:16 IR:58
halfcyc:20 phi0:1 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:16 IR:58 R$0001=$00
halfcyc:21 phi0:0 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:12 IR:58
halfcyc:22 phi0:1 AB:0001 D:00 RnW:1 PC:0001 A:00 X:C0 Y:00 SP:BD P:12 IR:58 R$0001=$00
-- Executing BRK (I flag cleared above [node p2=0]):
halfcyc:23 phi0:0 AB:0002 D:00 RnW:1 PC:0002 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:24 phi0:1 AB:0002 D:00 RnW:1 PC:0002 A:00 X:C0 Y:00 SP:BD P:12 IR:00 R$0002=$00
halfcyc:25 phi0:0 AB:01BD D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:26 phi0:1 AB:01BD D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BD=$00
halfcyc:27 phi0:0 AB:01BC D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:28 phi0:1 AB:01BC D:03 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BC=$03
halfcyc:29 phi0:0 AB:01BB D:00 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00
halfcyc:30 phi0:1 AB:01BB D:32 RnW:0 PC:0003 A:00 X:C0 Y:00 SP:BD P:12 IR:00 W$01BB=$32
halfcyc:31 phi0:0 AB:FFFE D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:12 IR:00
halfcyc:32 phi0:1 AB:FFFE D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00 R$FFFE=$00
   perfect6502 sets I in phase 2 of PCL-loading cycle, -------------^^
   but visual6502 sets I in phase 1 of PCH-loading cycle (below).
halfcyc:33 phi0:0 AB:FFFF D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00
halfcyc:34 phi0:1 AB:FFFF D:00 RnW:1 PC:0003 A:00 X:C0 Y:00 SP:BA P:16 IR:00 R$FFFF=$00

[leonardoInf]

Interesting. I don't know if the goal is to have identical timing with visual6502 but if yes then this needs to be fixed.