Find and test flip flops with critical delay between their complementary clock inputs #8
Description
With the delay settings as of commit e5baa8d, APU channel 1 produces 2x the expected frequency. This happens, because the delay between the two inputs /clk and clk of flip flop EROS is 1 puny little picosecond too long. When the delay is too long, those flip flops misbehave and trigger on both edges instead of just the posedge of clk.
Here is the wave diagram of a clk 1 to 0 transition of EROS, which makes the flip flop erroneously propagate d to q:
We see that and1 falls right before clk.
In contrast, here is the wave diagram of a clk 1 to 0 transition of DAPE, which correctly ignores the clock edge:
We see that and1 falls after clk.
To fix this we either have to increase the delay of and1 to make if fall after clk in both cases, or we have to somehow decrease the delay between /clk and clk.
This can't be tested by test ROMs, because there is no way of reading the current audio output of a channel by software. So we need to find another way to catch flip flops that broke down due to too big clock delays.