@@ -84,19 +84,19 @@ expr9 = aiger.BoolExpr(circ)
8484import aiger
8585from aiger import utils
8686
87-
88- aag1 = aiger.load(path_to_aag1_file )
89- aag2 = aiger.load(path_to_aag2_file )
87+ # Parser for ascii AIGER format.
88+ aig1 = aiger.load(path_to_aig1_file.aag )
89+ aig2 = aiger.load(path_to_aig2_file.aag )
9090```
9191
9292## Sequential composition
9393``` python
94- aag3 = aag1 >> aag2
94+ aig3 = aig1 >> aig2
9595```
9696
9797## Parallel composition
9898``` python
99- aig4 = aag1 | aag2
99+ aig4 = aig1 | aig2
100100```
101101
102102## Circuits with Latches/Feedback/Delay
@@ -120,7 +120,7 @@ aig1['i', {'x': 'z'}]
120120aig1[' o' , {' y' : ' w' }]
121121
122122# Relabel latches 'l1' to 'l2'.
123- aig1[' o ' , {' l1' : ' l2' }]
123+ aig1[' l ' , {' l1' : ' l2' }]
124124```
125125
126126## Evaluation
@@ -148,13 +148,13 @@ aig4 = aig3.unroll(steps=10, init=True)
148148## Useful circuits
149149``` python
150150# Fix input x to be False.
151- aag4 = aiger.source({' x' : False }) >> aag3
151+ aig4 = aiger.source({' x' : False }) >> aig3
152152
153153# Remove output y.
154- aag4 = aag3 >> aiger.sink([' y' ])
154+ aig4 = aig3 >> aiger.sink([' y' ])
155155
156156# Create duplicate w of output y.
157- aag4 = aag3 >> aiger.tee({' y' : [' y' , ' w' ]})
157+ aig4 = aig3 >> aiger.tee({' y' : [' y' , ' w' ]})
158158
159159# Make an AND gate.
160160aiger.and_gate([' x' , ' y' ], out = ' name' )
@@ -163,16 +163,16 @@ aiger.and_gate(['x', 'y'], out='name')
163163aiger.or_gate([' x' , ' y' ]) # Default output name is #or_output.
164164
165165# And outputs.
166- aig1 >> aiger.and_gate(aag1 .outputs) # Default output name is #and_output.
166+ aig1 >> aiger.and_gate(aig1 .outputs) # Default output name is #and_output.
167167
168168# Or outputs.
169- aig1 >> aiger.or_gate(inputs = aag1 .outputs, output = ' my_output' )
169+ aig1 >> aiger.or_gate(inputs = aig1 .outputs, output = ' my_output' )
170170
171171# Flip outputs.
172- aig1 >> aiger.bit_flipper(inputs = aag1 .outputs)
172+ aig1 >> aiger.bit_flipper(inputs = aig1 .outputs)
173173
174174# Flip inputs.
175- aiger.bit_flipper(inputs = aag1 .inputs) >> aig1
175+ aiger.bit_flipper(inputs = aig1 .inputs) >> aig1
176176
177177# ITE circuit
178178# ['o1', 'o2'] = ['i1', 'i2'] if 'test' Else ['i3', 'i4']
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