diff --git a/arch/arm/boot/dts/xilinx/ni-coralreef.dts b/arch/arm/boot/dts/xilinx/ni-coralreef.dts new file mode 100644 index 0000000000000..e38a307f11d1c --- /dev/null +++ b/arch/arm/boot/dts/xilinx/ni-coralreef.dts @@ -0,0 +1,127 @@ +/dts-v1/; +/include/ "ni-zynq.dtsi" + +/* NIDEVCODE 7A4B */ + +/ { + model = "NI Coral Reef"; + compatible = "ni,zynq", "xlnx,zynq-7000"; + + leds { + compatible = "gpio-leds"; + + /* LED_STATUSy on GPIO46 */ + status { + label = "nilrt:status:yellow"; + gpios = <&gpio0 46 0>; + default-state = "on"; + }; + + /* LED_POWERb on GPIO47 */ + active { + label = "nilrt:status:blue"; + gpios = <&gpio0 47 0>; + default-state = "off"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + /* Reset switch is on GPIO48 */ + reset_sw@0 { + label = "reset_sw"; + gpios = <&gpio0 48 1 /* GPIO_ACTIVE_LOW */>; + linux,code = <408>; /* KEY_RESTART */ + gpio-key,wakeup; + }; + }; + + gpio_restart { + compatible = "gpio-restart"; + + /* ~PS_FORCE_RESET is on GPIO44 */ + gpios = <&gpio0 44 1 /* GPIO_ACTIVE_LOW */>; + priority = <200>; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <&gem0>; + dsa,mii-bus = <&gem0>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + /* MDIO addr 0x0 (single-chip addressing), switch 0 */ + reg = <0 0>; + + port@0 { + reg = <0x0>; + label = "cpu"; + }; + + port@1 { + reg = <0x1>; + label = "sw3"; + }; + + port@2 { + reg = <0x2>; + label = "sw2"; + }; + + port@3 { + reg = <0x3>; + label = "sw1"; + }; + + port@4 { + reg = <0x4>; + label = "sw0"; + }; + }; + }; +}; + +&i2c0 { + /* Override ni-zynq.dtsi; we do not have a CPLD at 0x40. */ + nicpld@40 { + status = "disabled"; + }; + + tmp451@4C { + compatible = "ti,tmp451"; + reg = <0x4C>; + vcc-supply = <®ulator_vccpint>; + }; +}; + +&gem0 { + status = "okay"; + emio-speed-gpios = <0>, + <&gpio0 54 0>; + + #address-cells = <0x1>; + #size-cells = <0x0>; + + fixed-link { + speed = <1000>; + full-duplex; + reg = <0>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; + reset-on-timeout; +};