From 9ad8cf9f8418a897d90d05ae895b521749372d26 Mon Sep 17 00:00:00 2001 From: Theo Hussey Date: Sun, 23 Mar 2025 18:05:03 +0000 Subject: [PATCH 1/2] Add Servant support for tang nano 20k --- data/tang_nano_20k.cst | 8 +++++ data/tang_nano_20k.sdc | 1 + fusesoc.conf | 6 ++++ servant.core | 20 +++++++++++ servant/servant_tang_nano_20k.v | 41 ++++++++++++++++++++++ servant/tang_nano_20k_clock_gen.v | 58 +++++++++++++++++++++++++++++++ 6 files changed, 134 insertions(+) create mode 100644 data/tang_nano_20k.cst create mode 100644 data/tang_nano_20k.sdc create mode 100644 fusesoc.conf create mode 100644 servant/servant_tang_nano_20k.v create mode 100644 servant/tang_nano_20k_clock_gen.v diff --git a/data/tang_nano_20k.cst b/data/tang_nano_20k.cst new file mode 100644 index 00000000..0cf0e08f --- /dev/null +++ b/data/tang_nano_20k.cst @@ -0,0 +1,8 @@ +IO_LOC "i_clk" 4; +IO_PORT "i_clk" IO_TYPE=LVCMOS33 PULL_MODE=NONE BANK_VCCIO=3.3; +IO_LOC "i_rst" 88; +IO_PORT "i_rst" PULL_MODE=DOWN BANK_VCCIO=3.3; +IO_LOC "o_uart_tx" 69; +IO_PORT "o_uart_tx" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; +IO_LOC "led" 15; +IO_PORT "led" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3; diff --git a/data/tang_nano_20k.sdc b/data/tang_nano_20k.sdc new file mode 100644 index 00000000..a895389d --- /dev/null +++ b/data/tang_nano_20k.sdc @@ -0,0 +1 @@ +create_clock -name i_clk -period 37.04 [get_nets {i_clk}] // 27 Mhz diff --git a/fusesoc.conf b/fusesoc.conf new file mode 100644 index 00000000..0995ab1a --- /dev/null +++ b/fusesoc.conf @@ -0,0 +1,6 @@ +[library..] +location = /home/theo/Source/fpga/serv +sync-uri = . +sync-type = local +auto-sync = true + diff --git a/servant.core b/servant.core index 901250fc..33d2fd34 100644 --- a/servant.core +++ b/servant.core @@ -218,6 +218,13 @@ filesets: - servant/servive_clock_gen.v : {file_type : verilogSource} - servant/servive.v : {file_type : verilogSource} + tang_nano_20k: + files: + - servant/tang_nano_20k_clock_gen.v: { file_type: verilogSource } + - servant/servant_tang_nano_20k.v: { file_type: verilogSource } + - data/tang_nano_20k.sdc: { file_type: SDC } + - data/tang_nano_20k.cst: { file_type: CST } + te0802: files: - servant/servant_te0802_clock_gen.v : {file_type : verilogSource} @@ -603,6 +610,19 @@ targets: device : 5CSXFC6D6F31C6 toplevel: servive + tang_nano_20k: + # Use openFPGALoader to program the project.fs file to the FPGA + default_tool: gowin + description: Sipeed Tang Nano 20K Development board + filesets: [mem_files, soc, tang_nano_20k] + flow: gowin + flow_options: + tool: gowin + part: GW2AR-LV18QN88C8/I7 + gowin_options: + - -multi_boot 1 + toplevel: servant_tang_nano_20k + te0802: default_tool: vivado description : Trenz Electronic TE0802 diff --git a/servant/servant_tang_nano_20k.v b/servant/servant_tang_nano_20k.v new file mode 100644 index 00000000..0edd5696 --- /dev/null +++ b/servant/servant_tang_nano_20k.v @@ -0,0 +1,41 @@ +`default_nettype none +module servant_tang_nano_20k( + input wire i_clk, + input wire i_rst, + output wire led, + output wire o_uart_tx +); + + wire wb_clk; + wire locked; + wire q; + reg wb_rst = 1'b1; + + // UART output to LED + assign led = o_uart_tx; + assign o_uart_tx = q; + + parameter memfile = "zephyr_hello.hex"; + parameter memsize = 8192; + + // Create a 16MHz clock from 27MHz using PLL + tang_nano_20k_clock_gen pll ( + .lock (locked), + .clkoutd (wb_clk), + .reset(i_rst), + .clkin (i_clk) + ); + + always @(posedge wb_clk) + wb_rst <= !locked; + + servant + #(.memfile (memfile), + .memsize (memsize)) + servant + (.wb_clk (wb_clk), + .wb_rst (wb_rst), + .q (q)); + +endmodule + diff --git a/servant/tang_nano_20k_clock_gen.v b/servant/tang_nano_20k_clock_gen.v new file mode 100644 index 00000000..c9c51249 --- /dev/null +++ b/servant/tang_nano_20k_clock_gen.v @@ -0,0 +1,58 @@ +// Input 27MHz Output 16MHz + +module tang_nano_20k_clock_gen (lock, clkoutd, reset, clkin); + +output wire lock; +output wire clkoutd; +input wire reset; +input wire clkin; + +wire lock_o; +wire clkoutp_o; +wire clkoutd3_o; +wire gw_gnd; + +assign gw_gnd = 1'b0; + +rPLL rpll_inst ( + .CLKOUT(), + .LOCK(lock), + .CLKOUTP(clkoutp_o), + .CLKOUTD(clkoutd), + .CLKOUTD3(clkoutd3_o), + .RESET(reset), + .RESET_P(gw_gnd), + .CLKIN(clkin), + .CLKFB(gw_gnd), + .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}), + .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}) +); + +defparam rpll_inst.FCLKIN = "27"; +defparam rpll_inst.DYN_IDIV_SEL = "false"; +defparam rpll_inst.IDIV_SEL = 2; +defparam rpll_inst.DYN_FBDIV_SEL = "false"; +defparam rpll_inst.FBDIV_SEL = 31; +defparam rpll_inst.DYN_ODIV_SEL = "false"; +defparam rpll_inst.ODIV_SEL = 2; +defparam rpll_inst.PSDA_SEL = "0000"; +defparam rpll_inst.DYN_DA_EN = "true"; +defparam rpll_inst.DUTYDA_SEL = "1000"; +defparam rpll_inst.CLKOUT_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUTP_FT_DIR = 1'b1; +defparam rpll_inst.CLKOUT_DLY_STEP = 0; +defparam rpll_inst.CLKOUTP_DLY_STEP = 0; +defparam rpll_inst.CLKFB_SEL = "internal"; +defparam rpll_inst.CLKOUT_BYPASS = "false"; +defparam rpll_inst.CLKOUTP_BYPASS = "false"; +defparam rpll_inst.CLKOUTD_BYPASS = "false"; +defparam rpll_inst.DYN_SDIV_SEL = 18; +defparam rpll_inst.CLKOUTD_SRC = "CLKOUT"; +defparam rpll_inst.CLKOUTD3_SRC = "CLKOUT"; +defparam rpll_inst.DEVICE = "GW2AR-18C"; + +endmodule \ No newline at end of file From 7e725be77fda7cce8f6f02f55a44c5675e9bbed7 Mon Sep 17 00:00:00 2001 From: Theo Hussey Date: Sun, 23 Mar 2025 18:33:36 +0000 Subject: [PATCH 2/2] added doc for tang nano 20k --- doc/servant.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/doc/servant.rst b/doc/servant.rst index e5061bfd..a1884fcd 100644 --- a/doc/servant.rst +++ b/doc/servant.rst @@ -248,6 +248,16 @@ FPGA Pin F14 (HSTC GPIO addon connector J2, pin 2) is used for UART output with fusesoc run --target=sockit servant +Sipeed Tang Nano 20k +^^^^^^^^^^^^^^^^^^^^ + +57600 baud UART output is connected to then onboard UART to USB controller, as well as LED0. +If a large amount of UART data is output, the onboard UART does not work well, use an external FTDI adapter. + + fusesoc run --target=tang_nano_20k servant + openFPGALoader build/servant_1.3.0/tang_nano_20k/impl/pnr/project.fs + + Trenz Electronic TE0802 ^^^^^^^^^^^^^^^^^^^^^^^