8357551: RISC-V: support CMoveF/D vectorization

src/hotspot/cpu/aarch64/matcher_aarch64.hpp

@@ -204,4 +204,9 @@
   static bool is_feat_fp16_supported() {
     return (VM_Version::supports_fphp() && VM_Version::supports_asimdhp());
   }
+
+  static bool supports_vector_different_use_def_size() {
+    return false;
+  }
+
 #endif // CPU_AARCH64_MATCHER_AARCH64_HPP

src/hotspot/cpu/arm/matcher_arm.hpp

@@ -193,4 +193,8 @@
     return false;
   }
 
+  static bool supports_vector_different_use_def_size() {
+    return false;
+  }
+
 #endif // CPU_ARM_MATCHER_ARM_HPP

src/hotspot/cpu/ppc/matcher_ppc.hpp

@@ -203,4 +203,8 @@
     return false;
   }
 
+  static bool supports_vector_different_use_def_size() {
+    return false;
+  }
+
 #endif // CPU_PPC_MATCHER_PPC_HPP

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp

@@ -2067,6 +2067,87 @@ void C2_MacroAssembler::enc_cmove_cmp_fp(int cmpFlag, FloatRegister op1, FloatRe
   }
 }
 
+void C2_MacroAssembler::enc_cmove_fp_cmp(int cmpFlag,
+                        Register op1, Register op2, Register tmp1, Register tmp2,
+                        FloatRegister dst, FloatRegister src, bool is_single) {
+  bool is_unsigned = (cmpFlag & unsigned_branch_mask) == unsigned_branch_mask;
+  int op_select = cmpFlag & (~unsigned_branch_mask);
+
+  switch (op_select) {
+    case BoolTest::eq:
+      cmov_fp_eq(op1, op2, tmp1, tmp2, dst, src, is_single);
+      break;
+    case BoolTest::ne:
+      cmov_fp_ne(op1, op2, tmp1, tmp2, dst, src, is_single);
+      break;
+    case BoolTest::le:
+      if (is_unsigned) {
+        cmov_fp_leu(op1, op2, tmp1, tmp2, dst, src, is_single);
+      } else {
+        cmov_fp_le(op1, op2, tmp1, tmp2, dst, src, is_single);
+      }
+      break;
+    case BoolTest::ge:
+      if (is_unsigned) {
+        cmov_fp_geu(op1, op2, tmp1, tmp2, dst, src, is_single);
+      } else {
+        cmov_fp_ge(op1, op2, tmp1, tmp2, dst, src, is_single);
+      }
+      break;
+    case BoolTest::lt:
+      if (is_unsigned) {
+        cmov_fp_ltu(op1, op2, tmp1, tmp2, dst, src, is_single);
+      } else {
+        cmov_fp_lt(op1, op2, tmp1, tmp2, dst, src, is_single);
+      }
+      break;
+    case BoolTest::gt:
+      if (is_unsigned) {
+        cmov_fp_gtu(op1, op2, tmp1, tmp2, dst, src, is_single);
+      } else {
+        cmov_fp_gt(op1, op2, tmp1, tmp2, dst, src, is_single);
+      }
+      break;
+    default:
+      assert(false, "unsupported compare condition");
+      ShouldNotReachHere();
+  }
+}
+
+void C2_MacroAssembler::enc_cmove_fp_cmp_fp(int cmpFlag,
+                           FloatRegister op1, FloatRegister op2,
+                           Register tmp1, Register tmp2,
+                           FloatRegister dst, FloatRegister src,
+                           bool cmp_single, bool cmov_single) {
+  int op_select = cmpFlag & (~unsigned_branch_mask);
+
+  switch (op_select) {
+    case BoolTest::eq:
+      cmov_fp_cmp_fp_eq(op1, op2, tmp1, tmp2, dst, src, cmp_single, cmov_single);
+      break;
+    case BoolTest::ne:
+      cmov_fp_cmp_fp_ne(op1, op2, tmp1, tmp2, dst, src, cmp_single, cmov_single);
+      break;
+    case BoolTest::le:
+      cmov_fp_cmp_fp_le(op1, op2, tmp1, tmp2, dst, src, cmp_single, cmov_single);
+      break;
+    case BoolTest::ge:
+      assert(false, "Should go to BoolTest::le case");
+      ShouldNotReachHere();
+      break;
+    case BoolTest::lt:
+      cmov_fp_cmp_fp_lt(op1, op2, tmp1, tmp2, dst, src, cmp_single, cmov_single);
+      break;
+    case BoolTest::gt:
+      assert(false, "Should go to BoolTest::lt case");
+      ShouldNotReachHere();
+      break;
+    default:
+      assert(false, "unsupported compare condition");
+      ShouldNotReachHere();
+  }
+}
+
 // Set dst to NaN if any NaN input.
 void C2_MacroAssembler::minmax_fp(FloatRegister dst, FloatRegister src1, FloatRegister src2,
                                   FLOAT_TYPE ft, bool is_min) {

src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.hpp

@@ -132,6 +132,16 @@
                         FloatRegister op1, FloatRegister op2,
                         Register dst, Register src, bool is_single);
 
+  void enc_cmove_fp_cmp(int cmpFlag,
+                        Register op1, Register op2, Register tmp1, Register tmp2,
+                        FloatRegister dst, FloatRegister src, bool is_single);
+
+  void enc_cmove_fp_cmp_fp(int cmpFlag,
+                           FloatRegister op1, FloatRegister op2,
+                           Register tmp1, Register tmp2,
+                           FloatRegister dst, FloatRegister src,
+                           bool cmp_single, bool cmov_single);
+
   void spill(Register r, bool is64, int offset) {
     is64 ? sd(r, Address(sp, offset))
          : sw(r, Address(sp, offset));