From 8ae4cfdc048316f8f6fea728e00d797545ae025d Mon Sep 17 00:00:00 2001 From: nicogtm Date: Mon, 5 Sep 2016 11:09:47 +0200 Subject: [PATCH 1/4] Reduced MAM-WB interface functionality to WB Classic Cycles For that, CTI_O and BTE_O are set to be always zeros. --- modules/mam/wishbone/osd_mam_wb_if.sv | 29 +++------------------------ 1 file changed, 3 insertions(+), 26 deletions(-) diff --git a/modules/mam/wishbone/osd_mam_wb_if.sv b/modules/mam/wishbone/osd_mam_wb_if.sv index df9bdb1..637e1b3 100644 --- a/modules/mam/wishbone/osd_mam_wb_if.sv +++ b/modules/mam/wishbone/osd_mam_wb_if.sv @@ -58,8 +58,6 @@ module osd_mam_wb_if STATE_READ_WAIT } state, nxt_state; logic nxt_we_o; - logic [2:0] nxt_cti_o; - logic [1:0] nxt_bte_o; reg [DATA_WIDTH-1:0] read_data_reg; logic [DATA_WIDTH-1:0] nxt_read_data_reg; @@ -81,8 +79,6 @@ module osd_mam_wb_if end we_o <= nxt_we_o; - cti_o <= nxt_cti_o; - bte_o <= nxt_bte_o; read_data_reg <= nxt_read_data_reg; dat_o_reg <= nxt_dat_o_reg; addr_o <= nxt_addr_o; @@ -90,13 +86,13 @@ module osd_mam_wb_if end assign cyc_o = stb_o; - + assign cti_o = 3'b0; + assign bte_o = 2'b0; + //state & output logic always_comb begin nxt_state = state; nxt_we_o = we_o; - nxt_cti_o = cti_o; - nxt_bte_o = 2'b0; nxt_read_data_reg = read_data_reg; nxt_dat_o_reg = dat_o_reg; nxt_addr_o = addr_o; @@ -121,7 +117,6 @@ module osd_mam_wb_if nxt_we_o = 1; if (req_burst) begin if (nxt_beats == 1) begin - nxt_cti_o = 3'b111; if (write_valid) begin nxt_state = STATE_WRITE_LAST; nxt_dat_o_reg = write_data; @@ -129,8 +124,6 @@ module osd_mam_wb_if nxt_state = STATE_WRITE_LAST_WAIT; end end else begin - nxt_cti_o = 3'b010; - nxt_bte_o = 2'b00; if (write_valid) begin nxt_state = STATE_WRITE; nxt_dat_o_reg = write_data; @@ -139,7 +132,6 @@ module osd_mam_wb_if end end end else begin // !req_burst - nxt_cti_o = 3'b111; if (write_valid) begin nxt_state = STATE_WRITE_LAST; nxt_dat_o_reg = write_data; @@ -150,15 +142,6 @@ module osd_mam_wb_if end else begin // req_rw == 0 nxt_we_o = 0; nxt_state = STATE_READ; - if (req_burst) begin - if (nxt_beats == 1) begin - nxt_cti_o = 3'b111; - end else begin - nxt_cti_o = 3'b010; - end - end else begin // !req_burst - nxt_cti_o = 3'b111; - end // if (req_burst) end // if (req_rw) end // if (req_valid) end //STATE_IDLE @@ -173,7 +156,6 @@ module osd_mam_wb_if stb_o = 1; if (ack_i) begin nxt_state = STATE_IDLE; - nxt_cti_o = 3'b000; end end //STATE_WRITE_LAST STATE_WRITE_WAIT: begin @@ -190,7 +172,6 @@ module osd_mam_wb_if write_ready = 1; nxt_addr_o = addr_o + DATA_WIDTH/8; if (beats == 1) begin - nxt_cti_o=3'b111; if (write_valid) begin nxt_state = STATE_WRITE_LAST; nxt_dat_o_reg = write_data; @@ -220,10 +201,6 @@ module osd_mam_wb_if STATE_READ_WAIT: begin read_valid = 1; if (read_ready) begin - if (beats == 1) begin - nxt_cti_o = 3'b111; - end - if (beats == 0) begin nxt_state = STATE_IDLE; end else begin From 3526fad598637e800a741dfa87604f01979a7830 Mon Sep 17 00:00:00 2001 From: nicogtm Date: Mon, 5 Sep 2016 12:18:06 +0200 Subject: [PATCH 2/4] Simplified MAM-WB State Machine Reduced Write states. --- modules/mam/wishbone/osd_mam_wb_if.sv | 81 ++++++++------------------- 1 file changed, 22 insertions(+), 59 deletions(-) diff --git a/modules/mam/wishbone/osd_mam_wb_if.sv b/modules/mam/wishbone/osd_mam_wb_if.sv index 637e1b3..6eeb2ad 100644 --- a/modules/mam/wishbone/osd_mam_wb_if.sv +++ b/modules/mam/wishbone/osd_mam_wb_if.sv @@ -53,9 +53,8 @@ module osd_mam_wb_if (DATA_WIDTH == 16) ? 2 : (DATA_WIDTH == 8) ? 1 : 'hx; - enum { STATE_IDLE, STATE_WRITE_LAST, STATE_WRITE_LAST_WAIT, - STATE_WRITE, STATE_WRITE_WAIT, STATE_READ, - STATE_READ_WAIT } state, nxt_state; + enum { STATE_IDLE, STATE_WRITE, STATE_WRITE_WAIT, + STATE_READ, STATE_READ_WAIT } state, nxt_state; logic nxt_we_o; @@ -114,50 +113,19 @@ module osd_mam_wb_if nxt_addr_o = req_addr; if (req_valid) begin if (req_rw) begin - nxt_we_o = 1; - if (req_burst) begin - if (nxt_beats == 1) begin - if (write_valid) begin - nxt_state = STATE_WRITE_LAST; - nxt_dat_o_reg = write_data; - end else begin - nxt_state = STATE_WRITE_LAST_WAIT; - end - end else begin - if (write_valid) begin - nxt_state = STATE_WRITE; - nxt_dat_o_reg = write_data; - end else begin - nxt_state = STATE_WRITE_WAIT; - end - end - end else begin // !req_burst - if (write_valid) begin - nxt_state = STATE_WRITE_LAST; - nxt_dat_o_reg = write_data; - end else begin - nxt_state = STATE_WRITE_LAST_WAIT; - end - end // if (req_burst) + nxt_we_o = 1; + if (write_valid) begin + nxt_state = STATE_WRITE; + nxt_dat_o_reg = write_data; + end else begin + nxt_state = STATE_WRITE_WAIT; + end end else begin // req_rw == 0 nxt_we_o = 0; nxt_state = STATE_READ; end // if (req_rw) end // if (req_valid) end //STATE_IDLE - STATE_WRITE_LAST_WAIT: begin - write_ready = 1; - if (write_valid) begin - nxt_state = STATE_WRITE_LAST; - nxt_dat_o_reg = write_data; - end - end //STATE_WRITE_LAST_WAIT - STATE_WRITE_LAST: begin - stb_o = 1; - if (ack_i) begin - nxt_state = STATE_IDLE; - end - end //STATE_WRITE_LAST STATE_WRITE_WAIT: begin write_ready = 1; if (write_valid) begin @@ -169,24 +137,19 @@ module osd_mam_wb_if STATE_WRITE: begin stb_o = 1; if (ack_i) begin - write_ready = 1; - nxt_addr_o = addr_o + DATA_WIDTH/8; - if (beats == 1) begin - if (write_valid) begin - nxt_state = STATE_WRITE_LAST; - nxt_dat_o_reg = write_data; - end else begin - nxt_state = STATE_WRITE_LAST_WAIT; - end - end else begin // beats != 1 - if (write_valid) begin - nxt_state = STATE_WRITE; - nxt_dat_o_reg = write_data; - nxt_beats = beats - 1; - end else begin - nxt_state = STATE_WRITE_WAIT; - end - end // if (beats == 1) + if (beats == 0) begin + nxt_state = STATE_IDLE; + end else begin // beats != 1 + write_ready = 1; + nxt_addr_o = addr_o + DATA_WIDTH/8; + if (write_valid) begin + nxt_state = STATE_WRITE; + nxt_dat_o_reg = write_data; + nxt_beats = beats - 1; + end else begin + nxt_state = STATE_WRITE_WAIT; + end + end // if (beats == 0) end // if (ack_i) end // STATE_WRITE STATE_READ: begin From d8253523940d2ee13782a5d76df5114cac57907c Mon Sep 17 00:00:00 2001 From: nicogtm Date: Mon, 5 Sep 2016 13:46:55 +0200 Subject: [PATCH 3/4] Further reduced number of states Removed unneccessary write states. --- modules/mam/wishbone/osd_mam_wb_if.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/modules/mam/wishbone/osd_mam_wb_if.sv b/modules/mam/wishbone/osd_mam_wb_if.sv index 6eeb2ad..505a98f 100644 --- a/modules/mam/wishbone/osd_mam_wb_if.sv +++ b/modules/mam/wishbone/osd_mam_wb_if.sv @@ -139,7 +139,7 @@ module osd_mam_wb_if if (ack_i) begin if (beats == 0) begin nxt_state = STATE_IDLE; - end else begin // beats != 1 + end else begin // beats != 0 write_ready = 1; nxt_addr_o = addr_o + DATA_WIDTH/8; if (write_valid) begin From f8e305d6df6392ec0bb254f6c60c9bbd8005fba2 Mon Sep 17 00:00:00 2001 From: nicogtm Date: Mon, 5 Sep 2016 19:32:27 +0200 Subject: [PATCH 4/4] Removed reg type from cti_o and bte_o --- modules/mam/wishbone/osd_mam_wb_if.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/modules/mam/wishbone/osd_mam_wb_if.sv b/modules/mam/wishbone/osd_mam_wb_if.sv index 505a98f..78a4101 100644 --- a/modules/mam/wishbone/osd_mam_wb_if.sv +++ b/modules/mam/wishbone/osd_mam_wb_if.sv @@ -43,8 +43,8 @@ module osd_mam_wb_if output reg [ADDR_WIDTH-1:0] addr_o, output reg [DATA_WIDTH-1:0] dat_o, input [DATA_WIDTH-1:0] dat_i, - output reg [2:0] cti_o, - output reg [1:0] bte_o, + output [2:0] cti_o, + output [1:0] bte_o, output reg [SW-1:0] sel_o );