diff --git a/crs/BaseDeTiempo2.vhd b/crs/BaseDeTiempo2.vhd index 3521d46..7ceb310 100644 --- a/crs/BaseDeTiempo2.vhd +++ b/crs/BaseDeTiempo2.vhd @@ -19,8 +19,8 @@ architecture Behavioral of BasedeTiempo2 is begin comb : process(P_S) begin - --if(P_S = "11101110011010110010100000000") then - if(P_S = "0011") then + if(P_S = "11101110011010110010100000000") then + --if(P_S = "0011") then N_S <= (others => '0'); rst_out <= '1'; else diff --git "a/crs/Dise\303\261o2v1.vhd" b/crs/Diseno.vhd similarity index 67% rename from "crs/Dise\303\261o2v1.vhd" rename to crs/Diseno.vhd index 21c81b3..64697aa 100644 --- "a/crs/Dise\303\261o2v1.vhd" +++ b/crs/Diseno.vhd @@ -3,16 +3,18 @@ use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; -entity Diseno is +entity MD is port( sensores : IN STD_LOGIC_VECTOR(8 downto 0); clk : IN STD_LOGIC; resetAbsoluto: IN STD_LOGIC; + prueba: out std_logic_vector(3 downto 0); + p2: out std_logic; abre : OUT STD_LOGIC ); -end Diseno; +end MD; -architecture Behavioral of Diseno is +architecture Behavioral of MD is component BaseDeTiempo is generic( @@ -54,6 +56,7 @@ component comparador is A: in STD_LOGIC_VECTOR(n-1 downto 0); B: in STD_LOGIC_VECTOR(n-1 downto 0); CLK: in STD_LOGIC; + CE: in STD_LOGIC; Clr : in STD_LOGIC; Count : in STD_LOGIC_VECTOR(3 downto 0); Bool: out STD_LOGIC @@ -77,6 +80,7 @@ component Contador is port( clk : IN STD_LOGIC; clr : IN STD_LOGIC; + CE : IN STD_LOGIC; Count : OUT STD_LOGIC_VECTOR(n-1 downto 0) --Indica el turno en que se detecto un sensor. ); end component; @@ -93,6 +97,17 @@ component val2 is ); end component; +component val1 is + generic( + n:integer:=9 + ); + port( + NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0); --cadena recien hecha + Clk : IN STD_LOGIC; + rst : IN STD_LOGIC; + GoodWord : OUT STD_LOGIC_VECTOR(n-1 downto 0) --palabra que saldra si pasa los filtros + ); +end component; --SIGNALS-- signal CE,CE2,rst,rstComp,rstTB2 : STD_LOGIC; @@ -103,17 +118,17 @@ begin --port map-- - TimeBasis: BaseDeTiempo port map(NewWord=>sensores,CE=>CE2);--genera el clk para el val + TimeBasis: BaseDeTiempo port map(NewWord=>GoodWord,CE=>CE);--genera el clk para el val TimeBasis2: BaseDeTiempo2 port map(CLK=>CLK,rst_in=>rstTB2,rst_out=>rstComp); - BTN: bitsToNumbers port map(cadenaOriginalDeBits=>GoodWord,numero=>numero); - Comp: comparador port map(A=>valor,B=>numero,CLK=>CE,Clr=>rst,Count=>Count,Bool=>abre); - Cont: Contador port map(CLK=>CE,clr=>rst,count=>count); + BTN: bitsToNumbers port map(cadenaOriginalDeBits=>sensores,numero=>numero); + Comp: comparador port map(A=>valor,B=>numero,CLK=>CLK,CE=>CE,Clr=>rst,Count=>Count,Bool=>abre); + Cont: Contador port map(CLK=>CLK,CE=>CE,clr=>rst,count=>count); Ro: ROM port map (Count=>count,valor=>valor); - Val: val2 port map(NewWord=>sensores,clk=>CE2,rst=>rst,GoodWord=>GoodWord);--genera la palabra que el timeBasis va a procesar - TimeBasis12:BaseDeTiempo port map(NewWord=>GoodWord,CE=>CE);--generea el clk del sistema + Val: val1 port map(NewWord=>sensores,clk=>clk,rst=>rst,GoodWord=>GoodWord);--genera la palabra que el timeBasis va a procesar + --TimeBasis12:BaseDeTiempo port map(NewWord=>GoodWord,CE=>CE);--generea el clk del sistema -- En las prubas con botones se encontraron pulsos inesperados y se espera que el val solucione estos problemas -comb : process( resetAbsoluto,rstComp,CE2) +comb : process( resetAbsoluto,rstComp,CE,count) begin if (ResetAbsoluto='1') then @@ -121,9 +136,11 @@ begin rstTB2 <= ResetAbsoluto; else rst <= rstComp; - rstTB2 <= CE2; + rstTB2 <= CE; end if ; + prueba <= count; + p2 <= CE; end process ; -- comb diff --git a/crs/comparador.vhd b/crs/comparador.vhd index 1324fb1..ae2137e 100644 --- a/crs/comparador.vhd +++ b/crs/comparador.vhd @@ -13,6 +13,8 @@ entity comparador is CLK: in STD_LOGIC; Clr : in STD_LOGIC; Count : in STD_LOGIC_VECTOR(3 downto 0); + --A_out : out std_logic_vector(n-1 downto 0); + --B_out : out std_logic_vector(n-1 downto 0); Bool: out STD_LOGIC ); end comparador; @@ -20,21 +22,29 @@ end comparador; architecture Behavioral of comparador is signal N_S : std_logic_vector(9 downto 0); begin - process (A,B,CLK,Clr,Count) + process (A,B,CLK,Clr,Count,N_S) begin - if(CLK'event AND CLK = '1') then + if(Clr = '1')then + N_S <= (others => '0'); + Bool <= '0';-- + elsif(CLK'event AND CLK = '1') then if( A = B) then N_S(conv_integer(Count)) <= '1'; else N_S(conv_integer(Count)) <= '0'; - end if; - elsif(N_S(6 downto 0) = "1111111" )then + end if; + end if; + + if(N_S(6 downto 0) = "1111111" )then Bool <= '1'; - elsif(Clr = '1')then - N_S <= (others => '0'); - Bool <= '0';-- - else - Bool <= '0'; + else + Bool <= '0'; end if; + + --A_out <= A; + --B_out <= B; + --else + -- Bool <= '0'; + end process; -end Behavioral; \ No newline at end of file +end Behavioral; diff --git a/crs/val1.vhd b/crs/val1.vhd index bf3ac6e..85df216 100644 --- a/crs/val1.vhd +++ b/crs/val1.vhd @@ -8,22 +8,25 @@ entity val1 is port( NewWord : IN STD_LOGIC_VECTOR(n-1 downto 0); --cadena recien hecha Clk : IN STD_LOGIC; + rst : IN STD_LOGIC; GoodWord : OUT STD_LOGIC_VECTOR(n-1 downto 0) --palabra que saldra si pasa los filtros ); end val1; architecture Behavioral of val1 is -begin - signal AlreadyInWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion o estado presente + + signal AlreadyInWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion o estado presente signal FinalWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion nueva o proximo estado + signal GoodWord2 : STD_LOGIC_VECTOR(n-1 downto 0); +begin comb: process (NewWord,AlreadyInWord) begin for I in 0 to n-1 loop if(AlreadyInWord(I)='0') then - GoodWord(I)<=NewWord(I); + GoodWord2(I)<=NewWord(I); else - GoodWord(I)<='0'; + GoodWord2(I)<='0'; end if; FinalWord(I) <= NewWord(I) OR AlreadyInWord(I); @@ -33,11 +36,13 @@ begin end loop; end process; - sequ: process(CE,Clk,FinalWord) + sequ: process(Clk,FinalWord,rst) begin - - if(Clk'event AND Clk='1') then - AlreadyInWord<=FinalWord; + if(rst = '1') then + AlreadyInWord <= "000000000"; + elsif(Clk'event AND Clk='1') then + AlreadyInWord<=FinalWord; + GoodWord<=GoodWord2; end if; end process; diff --git a/crs/val2.vhd b/crs/val2.vhd index fa09020..907ca12 100644 --- a/crs/val2.vhd +++ b/crs/val2.vhd @@ -16,31 +16,38 @@ end val2; architecture Behavioral of val2 is signal AlreadyInWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion o estado presente - signal FinalWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion nueva o proximo estado + signal FinalWord : STD_LOGIC_VECTOR(n-1 downto 0); --cadena de comprobacion nueva o proximo estado + signal GoodWord2 : STD_LOGIC_VECTOR(n-1 downto 0); begin comb: process (NewWord,AlreadyInWord) begin - + if( NewWord /= "000000000")then if (NewWord = AlreadyInWord) then - GoodWord <= (others => '0'); + GoodWord2 <= (others => '0'); FinalWord <= AlreadyInWord; else - GoodWord <= NewWord; + GoodWord2 <= NewWord; FinalWord <= NewWord; end if ; + else + FinalWord <= AlreadyInWord; + GoodWord2 <= (others => '0'); + end if; + end process; - sequ: process(Clk,FinalWord,rst) + sequ: process(Clk,rst) begin if(rst = '1') then AlreadyInWord <= (others => '0'); elsif(Clk'event AND Clk='1') then - AlreadyInWord<=FinalWord; + AlreadyInWord<=FinalWord; + GoodWord <= GoodWord2; end if; end process sequ;