From b6c4a814c36be39f453c18eb1150314b6faaf0c6 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 21 Feb 2025 15:50:49 +0100 Subject: [PATCH 1/9] tb: Fix HyperRAM sdf annotation string --- target/sim/src/vip_chimera_soc.sv | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/target/sim/src/vip_chimera_soc.sv b/target/sim/src/vip_chimera_soc.sv index 0fd65e6..ae69db4 100644 --- a/target/sim/src/vip_chimera_soc.sv +++ b/target/sim/src/vip_chimera_soc.sv @@ -629,11 +629,10 @@ module vip_chimera_soc for (genvar l = 0; l < HypNumChips; l++) begin : sdf_annotation initial begin `ifndef PATH_TO_HYP_SDF - automatic string sdf_file_path = "../models/s27ks0641/s27ks0641.sdf"; + $sdf_annotate("../models/s27ks0641/s27ks0641.sdf", hyperrams[p].chips[l].dut); `else - automatic string sdf_file_path = `PATH_TO_HYP_SDF; + $sdf_annotate(`PATH_TO_HYP_SDF, hyperrams[p].chips[l].dut); `endif - $sdf_annotate(sdf_file_path, hyperrams[p].chips[l].dut); $display("Mem (%d,%d)", p, l); end end From 6f5a4b806dec56c4e4f243b694d7dd8460ab8eea Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Thu, 20 Feb 2025 13:19:51 +0100 Subject: [PATCH 2/9] [WIP] bender,makefile: Add PULP Cluster dep and update dependencies - add pulp_cluster dependency to Bender.yml manifest - update resolved dependencies in Bender.lock - fix issues with some dependencies with overrides in Bender.local - fix Snitch cluster's icache version due to outdated datatypes --- Bender.local | 7 ++ Bender.lock | 242 ++++++++++++++++++++++++++++++++++++++++++++++++--- Bender.yml | 6 +- 3 files changed, 239 insertions(+), 16 deletions(-) create mode 100644 Bender.local diff --git a/Bender.local b/Bender.local new file mode 100644 index 0000000..b652748 --- /dev/null +++ b/Bender.local @@ -0,0 +1,7 @@ +# Related to issue https://github.com/pulp-platform/bender/issues/182 +overrides: + # Should use the one from `pulp_cluster` dependency, supporting TNN ISA extension + riscv: { git: "git@iis-git.ee.ethz.ch:pulpissimov2/riscv-nn.git", rev: "53b053cd0be8dae25caa24bd57824e81cf87ba21" } + # Override with the correct remote where `pulp-v0.1.3` can be found; + # note that the name is `cvfpu` but we want to override `fpnew` which has the issue with remotes + fpnew: { git: "https://github.com/pulp-platform/cvfpu.git", rev: "pulp-v0.1.3" } diff --git a/Bender.lock b/Bender.lock index 6d9e886..0ed25f1 100644 --- a/Bender.lock +++ b/Bender.lock @@ -15,17 +15,32 @@ packages: - apb - register_interface axi: - revision: 853ede23b2a9837951b74dbdc6d18c3eef5bac7d - version: 0.39.5 + revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7 + version: 0.39.6 source: Git: https://github.com/pulp-platform/axi.git dependencies: - common_cells - common_verification - tech_cells_generic + axi2mem: + revision: be0c696709acaee579787ba2432d26ad27640594 + version: 1.0.2 + source: + Git: https://github.com/pulp-platform/axi2mem.git + dependencies: + - axi_slice + - common_cells + axi2per: + revision: e8ca052a745e184ca960933b2fe416b725e9ca81 + version: 1.0.2 + source: + Git: https://github.com/pulp-platform/axi2per.git + dependencies: + - axi_slice axi_llc: - revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39 - version: 0.2.1 + revision: 59bb8a681347e1133f11a82190fbf4bc11900d9e + version: 0.2.2 source: Git: https://github.com/pulp-platform/axi_llc.git dependencies: @@ -52,6 +67,13 @@ packages: - axi - common_cells - register_interface + axi_slice: + revision: a4f72bc21ac4d7da631e8309d9f8d0c34b735c23 + version: 1.1.4 + source: + Git: https://github.com/pulp-platform/axi_slice.git + dependencies: + - common_cells axi_stream: revision: 54891ff40455ca94a37641b9da4604647878cc07 version: 0.1.1 @@ -109,22 +131,30 @@ packages: - common_cells - register_interface cluster_icache: - revision: 0e1fb6751d9684d968ba7fb40836e6118b448ecd - version: 0.1.1 + revision: dd0e8f3497903a9ca99fc9f349d5a4f688ceb3ae + version: null source: Git: https://github.com/pulp-platform/cluster_icache.git dependencies: - axi - common_cells + - register_interface - scm - tech_cells_generic cluster_interconnect: - revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27 - version: 1.2.1 + revision: 1284def6c0b7f7e9355eb093d00883ad9dead1b7 + version: null source: Git: https://github.com/pulp-platform/cluster_interconnect.git dependencies: - common_cells + cluster_peripherals: + revision: e464eb9ddcc39e5a50009819601c4f213b1d4ba3 + version: 2.2.0 + source: + Git: https://github.com/pulp-platform/cluster_peripherals.git + dependencies: + - hci common_cells: revision: c27bce39ebb2e6bae52f60960814a2afca7bd4cb version: 1.37.0 @@ -134,11 +164,20 @@ packages: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] + cv32e40p: + revision: 1a93f340e9dadb9f7c8c471f27a40932c8b1c62e + version: null + source: + Git: https://github.com/pulp-platform/cv32e40p.git + dependencies: + - common_cells + - fpnew + - tech_cells_generic cva6: revision: 630bd959c9cc69a35d461a2abc205310d2edacf8 version: null @@ -149,6 +188,13 @@ packages: - common_cells - fpnew - tech_cells_generic + event_unit_flex: + revision: 28e0499374117c7b0ef4c6ad81b60d7526af886f + version: null + source: + Git: https://github.com/pulp-platform/event_unit_flex.git + dependencies: + - common_cells fpnew: revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315 version: null @@ -164,6 +210,44 @@ packages: Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git dependencies: - common_cells + hci: + revision: 4257a73b391731d94077ad72fc528c27f5b11392 + version: null + source: + Git: https://github.com/pulp-platform/hci.git + dependencies: + - cluster_interconnect + - common_cells + - hwpe-stream + - l2_tcdm_hybrid_interco + - redundancy_cells + - register_interface + hier-icache: + revision: 7243834d2407ca23cff583d57641c84b982bd9bc + version: 1.3.0 + source: + Git: https://github.com/pulp-platform/hier-icache.git + dependencies: + - axi + - axi_slice + - common_cells + - icache-intc + - scm + - tech_cells_generic + hwpe-ctrl: + revision: a5966201aeeb988d607accdc55da933a53c6a56e + version: null + source: + Git: https://github.com/pulp-platform/hwpe-ctrl.git + dependencies: + - tech_cells_generic + hwpe-stream: + revision: b3d33afdd27e79bcda1348d0ab5f4afd52c03106 + version: 1.9.0 + source: + Git: https://github.com/pulp-platform/hwpe-stream.git + dependencies: + - tech_cells_generic hyperbus: revision: f039e601c8b6590181734e6d26ff8b77aa380412 version: null @@ -174,8 +258,21 @@ packages: - common_cells - register_interface - tech_cells_generic + ibex: + revision: b18f7ef178ed07f5085051f96042c670a919fd5c + version: null + source: + Git: https://github.com/pulp-platform/ibex.git + dependencies: + - tech_cells_generic + icache-intc: + revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985 + version: 1.0.1 + source: + Git: https://github.com/pulp-platform/icache-intc.git + dependencies: [] idma: - revision: 9edf489f57389dce5e71252c79e337f527d3aded + revision: 92799c5fabcf2cd1f224f970bbb040b290d08fd5 version: null source: Git: https://github.com/pulp-platform/iDMA.git @@ -195,6 +292,19 @@ packages: - axi - common_cells - register_interface + l2_tcdm_hybrid_interco: + revision: fa55e72859dcfb117a2788a77352193bef94ff2b + version: 1.0.0 + source: + Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git + dependencies: [] + mchan: + revision: 3f2ae92f78e2ddbd0e079cbb4f81fcc248171c12 + version: 1.2.4 + source: + Git: https://github.com/pulp-platform/mchan.git + dependencies: + - common_cells memory_island: revision: 64828cb7a9ccc1f1656ec92d06129072f445c319 version: null @@ -206,9 +316,19 @@ packages: - common_cells - common_verification - tech_cells_generic + neureka: + revision: 8e0883bd0c19c6844122456c749c2bdfde18011f + version: null + source: + Git: https://github.com/pulp-platform/neureka.git + dependencies: + - hci + - hwpe-ctrl + - hwpe-stream + - zeroriscy obi: - revision: 5321106817e177d6c16ecc4daa922b96b1bc946b - version: 0.1.5 + revision: c2141a653c755461ff44f61d12aeb5d99fc8e760 + version: 0.1.3 source: Git: https://github.com/pulp-platform/obi.git dependencies: @@ -223,6 +343,68 @@ packages: - common_cells - register_interface - tech_cells_generic + per2axi: + revision: 18cf4f2ad51b73de0448843ce0def54ab5fb274b + version: 1.0.5 + source: + Git: https://github.com/pulp-platform/per2axi.git + dependencies: + - axi_slice + pulp_cluster: + revision: d16ac0afcb4081eb5379c74e397f0cc9d2b88e5e + version: null + source: + Git: https://github.com/pulp-platform/pulp_cluster.git + dependencies: + - axi + - axi2mem + - axi2per + - cluster_icache + - cluster_interconnect + - cluster_peripherals + - common_cells + - cv32e40p + - event_unit_flex + - hci + - hier-icache + - ibex + - idma + - mchan + - neureka + - obi + - per2axi + - redmule + - redundancy_cells + - register_interface + - riscv + - scm + - softex + - tech_cells_generic + - timer_unit + redmule: + revision: 9223ccc932e21d0667e9c2d30831db41eec9299e + version: null + source: + Git: https://github.com/pulp-platform/redmule.git + dependencies: + - common_cells + - cv32e40p + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - register_interface + - tech_cells_generic + redundancy_cells: + revision: 9e31f7c6c24877eaf58279903e7a162b16c9a721 + version: null + source: + Git: https://github.com/pulp-platform/redundancy_cells.git + dependencies: + - common_cells + - common_verification + - register_interface + - tech_cells_generic register_interface: revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467 version: 0.4.5 @@ -233,6 +415,14 @@ packages: - axi - common_cells - common_verification + riscv: + revision: 53b053cd0be8dae25caa24bd57824e81cf87ba21 + version: null + source: + Git: git@iis-git.ee.ethz.ch:pulpissimov2/riscv-nn.git + dependencies: + - fpnew + - tech_cells_generic riscv-dbg: revision: 358f90110220adf7a083f8b65d157e836d706236 version: 0.8.1 @@ -257,7 +447,7 @@ packages: - common_cells - register_interface snitch_cluster: - revision: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225 + revision: bad609605fd1bff5c982b47d5886d06b29b38a72 version: null source: Git: https://github.com/pulp-platform/snitch_cluster.git @@ -271,6 +461,18 @@ packages: - register_interface - riscv-dbg - tech_cells_generic + softex: + revision: 11dd29e85d40e29fea0481b471f1c0cc967df1a4 + version: null + source: + Git: https://github.com/belanoa/softex.git + dependencies: + - common_cells + - fpnew + - hci + - hwpe-ctrl + - hwpe-stream + - ibex tech_cells_generic: revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf version: 0.2.13 @@ -278,6 +480,12 @@ packages: Git: https://github.com/pulp-platform/tech_cells_generic.git dependencies: - common_verification + timer_unit: + revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc + version: 1.0.3 + source: + Git: https://github.com/pulp-platform/timer_unit.git + dependencies: [] unbent: revision: e9c9d5cfb635f2d4668c816ce9235798cfecb297 version: 0.1.6 @@ -287,3 +495,9 @@ packages: - axi - common_cells - register_interface + zeroriscy: + revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36 + version: null + source: + Git: https://github.com/yvantor/ibex.git + dependencies: [] diff --git a/Bender.yml b/Bender.yml index 2e33723..73639c5 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,18 +7,20 @@ package: authors: - "Moritz Scherer " - "Lorenzo Leone " + - "Sergio Mazzola " dependencies: register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.3 } axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 } cheshire: { git: "https://github.com/pulp-platform/cheshire.git", rev: 586cb0225be5c57f5ffcf67bd490763efd9b4d24} - snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: c12ce9b2af1ac8edf3d4feb18939e1ad20c42225} + snitch_cluster: { git: "https://github.com/pulp-platform/snitch_cluster.git", rev: bad609605fd1bff5c982b47d5886d06b29b38a72} # branch: smazzola/chimera common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1} idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded} - memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch + memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 } hyperbus: { git: "https://github.com/pulp-platform/hyperbus.git", rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 } + pulp_cluster: { git: "https://github.com/pulp-platform/pulp_cluster.git", rev: d16ac0afcb4081eb5379c74e397f0cc9d2b88e5e } # branch: smazzola/chimera export_include_dirs: - hw/include From 188cc0da6158c4f5e70dd25c0b3253b657d4439d Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Thu, 27 Feb 2025 14:30:13 +0100 Subject: [PATCH 3/9] makefile: Integrate PULP Cluster build flow --- .gitignore | 2 +- Bender.yml | 4 +++- Makefile | 2 ++ bender.mk | 27 +++++++++++++++++++++++++-- target/sim/sim.mk | 5 +++-- 5 files changed, 34 insertions(+), 6 deletions(-) diff --git a/.gitignore b/.gitignore index 5a63bac..b7f7148 100644 --- a/.gitignore +++ b/.gitignore @@ -35,7 +35,7 @@ utils/verible-verilog target/sim/models target/sim/vsim/work target/sim/vsim/transcript -target/sim/vsim/*.do +target/sim/vsim/*.log target/sim/vsim/trace* modelsim.ini compile.tcl diff --git a/Bender.yml b/Bender.yml index 73639c5..4724c97 100644 --- a/Bender.yml +++ b/Bender.yml @@ -34,7 +34,9 @@ sources: - hw/chimera_pkg.sv - hw/regs/chimera_reg_pkg.sv - hw/regs/chimera_reg_top.sv - - hw/bootrom/snitch/snitch_bootrom.sv + - target: snitch_cluster + files: + - hw/bootrom/snitch/snitch_bootrom.sv - hw/narrow_adapter.sv - hw/chimera_cluster_adapter.sv - hw/chimera_cluster.sv diff --git a/Makefile b/Makefile index 4b354f7..0ee3572 100644 --- a/Makefile +++ b/Makefile @@ -15,6 +15,7 @@ VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-form ifeq ($(shell test -d $(CHIM_ROOT)/.bender || echo 1),) CHS_ROOT ?= $(shell $(BENDER) path cheshire) SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster) +PULP_ROOT ?= $(shell $(BENDER) path pulp_cluster) IDMA_ROOT ?= $(shell $(BENDER) path idma) HYPERB_ROOT ?= $(shell $(BENDER) path hyperbus) endif @@ -22,6 +23,7 @@ endif # Fall back to safe defaults if dependencies are not cloned yet CHS_ROOT ?= . SNITCH_ROOT ?= . +PULP_ROOT ?= . IDMA_ROOT ?= . HYPERB_ROOT ?= . diff --git a/bender.mk b/bender.mk index 2039e68..32ce399 100644 --- a/bender.mk +++ b/bender.mk @@ -4,8 +4,31 @@ # # Moritz Scherer # Lorenzo Leone +# Sergio Mazzola + +# Bender defines + +COMMON_DEFS ?= +# PULP Cluster defines +COMMON_DEFS += -D FEATURE_ICACHE_STAT +COMMON_DEFS += -D PRIVATE_ICACHE +COMMON_DEFS += -D HIERARCHY_ICACHE_32BIT +COMMON_DEFS += -D ICAHE_USE_FF +COMMON_DEFS += -D CLUSTER_ALIAS +COMMON_DEFS += -D USE_PULP_PARAMETERS + +# Bender targets COMMON_TARGS ?= -COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl +# PULP Cluster targets +COMMON_TARGS += -t pulp_cluster +COMMON_TARGS += -t cluster_standalone +# Other targets +COMMON_TARGS += -t rtl +COMMON_TARGS += -t cv32a6_convolve -t cva6 +#COMMON_TARGS += -t snitch_cluster + +# Bender sim arguments -SIM_TARGS = $(COMMON_TARGS) -t test -t sim +SIM_DEFS ?= +SIM_TARGS ?= -t test -t sim diff --git a/target/sim/sim.mk b/target/sim/sim.mk index d056952..8819ff2 100644 --- a/target/sim/sim.mk +++ b/target/sim/sim.mk @@ -25,8 +25,9 @@ $(CHIM_SIM_DIR)/models/s27ks0641/s27ks0641.sv: HYP_USER_PRELOAD ?= 0 HYP0_PRELOAD_MEM_FILE ?= "" - +# vsim compilation arguments (options, macros) CHIM_VLOG_ARGS += -suppress 2583 -suppress 13314 +CHIM_VLOG_ARGS += \"+incdir+$(CHIM_ROOT)/hw/include\" CHIM_VLOG_ARGS += +define+HYP_USER_PRELOAD="$(HYP_USER_PRELOAD)" CHIM_VLOG_ARGS += +define+HYP0_PRELOAD_MEM_FILE=\"$(HYP0_PRELOAD_MEM_FILE)\" # this path should be kept relative to the vsim directory to avoid CI issues: @@ -35,7 +36,7 @@ CHIM_VLOG_ARGS += +define+PATH_TO_HYP_SDF=\"../models/s27ks0641/s27ks0641.sdf\" # Generate vsim compilation script $(CHIM_SIM_DIR)/vsim/compile.tcl: chs-hw-init snitch-hw-init - @bender script vsim $(SIM_TARGS) --vlog-arg="$(CHIM_VLOG_ARGS)" > $@ + bender script vsim $(COMMON_DEFS) $(COMMON_TARGS) $(SIM_DEFS) $(SIM_TARGS) --vlog-arg="$(CHIM_VLOG_ARGS)" > $@ echo 'vlog "$(realpath $(CHS_ROOT))/target/sim/src/elfloader.cpp" -ccflags "-std=c++11"' >> $@ # Clean From 51d535b161ffbd1397a0515f114a5ec66e7578b0 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Thu, 27 Feb 2025 14:30:37 +0100 Subject: [PATCH 4/9] [WIP] bender: Disable FF icache due to version problems --- bender.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bender.mk b/bender.mk index 32ce399..895a177 100644 --- a/bender.mk +++ b/bender.mk @@ -13,7 +13,7 @@ COMMON_DEFS ?= COMMON_DEFS += -D FEATURE_ICACHE_STAT COMMON_DEFS += -D PRIVATE_ICACHE COMMON_DEFS += -D HIERARCHY_ICACHE_32BIT -COMMON_DEFS += -D ICAHE_USE_FF +# COMMON_DEFS += -D ICAHE_USE_FF COMMON_DEFS += -D CLUSTER_ALIAS COMMON_DEFS += -D USE_PULP_PARAMETERS From e5f69b58dda0fbecb3d39db05d0e02598dc27f76 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 21 Feb 2025 16:50:30 +0100 Subject: [PATCH 5/9] hw: Integrate PULP Cluster in chimera_cluster and config --- hw/chimera_clu_domain.sv | 1 + hw/chimera_cluster.sv | 204 +++++++++++++++++++++++++++++++++- hw/chimera_cluster_adapter.sv | 35 +++++- hw/chimera_pkg.sv | 78 ++++++++++--- 4 files changed, 298 insertions(+), 20 deletions(-) diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index d208b13..22eff25 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -176,6 +176,7 @@ module chimera_clu_domain chimera_cluster #( .Cfg (Cfg), .NrCores (`NRCORES(extClusterIdx)), + .ClusterId (extClusterIdx), .narrow_in_req_t (narrow_in_req_t), .narrow_in_resp_t (narrow_in_resp_t), .narrow_out_req_t (narrow_out_req_t), diff --git a/hw/chimera_cluster.sv b/hw/chimera_cluster.sv index ba45bc2..0bb1a27 100644 --- a/hw/chimera_cluster.sv +++ b/hw/chimera_cluster.sv @@ -12,6 +12,7 @@ module chimera_cluster parameter chimera_cfg_t Cfg = '0, parameter int unsigned NrCores = 9, + parameter int unsigned ClusterId = 0, parameter type narrow_in_req_t = logic, parameter type narrow_in_resp_t = logic, parameter type narrow_out_req_t = logic, @@ -51,6 +52,7 @@ module chimera_cluster ); `include "axi/typedef.svh" + `include "axi/assign.svh" localparam int WideDataWidth = $bits(wide_out_req_o.w.data); @@ -183,27 +185,43 @@ module chimera_cluster ) i_cluster_axi_adapter ( .soc_clk_i(soc_clk_i), + `ifndef TARGET_PULP_CLUSTER .clu_clk_i(clu_clk_i), + `endif .rst_ni, + // NARROW PORTS + // SoC to cluster (from SoC master port) .narrow_in_req_i (clu_axi_narrow_slv_req), .narrow_in_resp_o (clu_axi_narrow_slv_rsp), - .narrow_out_req_o (clu_axi_narrow_mst_req), - .narrow_out_resp_i(clu_axi_narrow_mst_rsp), - + // SoC to cluster (to cluster slave port) .clu_narrow_in_req_o (clu_axi_adapter_slv_req), .clu_narrow_in_resp_i (clu_axi_adapter_slv_resp), + + // cluster to SoC (to SoC slave port) + .narrow_out_req_o (clu_axi_narrow_mst_req), + .narrow_out_resp_i(clu_axi_narrow_mst_rsp), + // cluster to SoC (from cluster master port) .clu_narrow_out_req_i (clu_axi_adapter_mst_req), .clu_narrow_out_resp_o(clu_axi_adapter_mst_resp), + // WIDE PORTS + // cluster to SoC (to SoC slave port) .wide_out_req_o (wide_out_req_o), .wide_out_resp_i (wide_out_resp_i), + // cluster to SoC (from cluster master port) .clu_wide_out_req_i (clu_axi_wide_mst_req), .clu_wide_out_resp_o(clu_axi_wide_mst_resp), .wide_mem_bypass_mode_i(widemem_bypass_i) ); + //////////////////// + // Snitch cluster // + //////////////////// + + `ifdef TARGET_SNITCH_CLUSTER + typedef struct packed { logic [2:0] ema; logic [1:0] emaw; @@ -292,6 +310,186 @@ module chimera_cluster .wide_in_resp_o (), .wide_out_req_o (clu_axi_wide_mst_req), .wide_out_resp_i (clu_axi_wide_mst_resp) + ); + ////////////////// + // PULP cluster // + ////////////////// + + `elsif TARGET_PULP_CLUSTER + + // SoC to Cluster CDC source slice (narrow slave) + AXI_BUS #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataInWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ) + ) soc_to_cluster_axi_bus(); + AXI_BUS_ASYNC_GRAY #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataInWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) async_soc_to_cluster_axi_bus(); + + axi_cdc_src_intf #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataInWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdInWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) soc_to_cluster_src_cdc_fifo_i ( + .src_clk_i ( soc_clk_i ), + .src_rst_ni ( rst_ni ), + .src ( soc_to_cluster_axi_bus ), + .dst ( async_soc_to_cluster_axi_bus ) ); + + `AXI_ASSIGN_FROM_REQ(soc_to_cluster_axi_bus, clu_axi_adapter_slv_req) + `AXI_ASSIGN_TO_RESP(clu_axi_adapter_slv_resp, soc_to_cluster_axi_bus) + + // Cluster to SoC CDC destination slice (narrow master) + AXI_BUS #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ) + ) cluster_to_soc_axi_bus(); + AXI_BUS_ASYNC_GRAY #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) async_cluster_to_soc_axi_bus(); + + axi_cdc_dst_intf #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) cluster_to_soc_dst_cdc_fifo_i ( + .dst_clk_i ( soc_clk_i ), + .dst_rst_ni ( rst_ni ), + .src ( async_cluster_to_soc_axi_bus ), + .dst ( cluster_to_soc_axi_bus ) + ); + + `AXI_ASSIGN_TO_REQ(clu_axi_adapter_mst_req, cluster_to_soc_axi_bus) + `AXI_ASSIGN_FROM_RESP(cluster_to_soc_axi_bus, clu_axi_adapter_mst_resp) + + // DMA CDC destination slice (wide master) + AXI_BUS #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWideWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ) + ) dma_axi_bus(); + AXI_BUS_ASYNC_GRAY #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWideWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) async_dma_axi_bus(); + + axi_cdc_dst_intf #( + .AXI_ADDR_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiAddrWidth ), + .AXI_DATA_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiDataOutWideWidth ), + .AXI_ID_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiIdOutWideWidth ), + .AXI_USER_WIDTH ( Cfg.PulpCluCfgs[ClusterId].AxiUserWidth ), + .LOG_DEPTH ( Cfg.PulpCluCfgs[ClusterId].AxiCdcLogDepth ) + ) dma_dst_cdc_fifo_i ( + .dst_clk_i ( soc_clk_i ), + .dst_rst_ni ( rst_ni ), + .src ( async_dma_axi_bus ), + .dst ( dma_axi_bus ) + ); + + `AXI_ASSIGN_TO_REQ(clu_axi_wide_mst_req, dma_axi_bus) + `AXI_ASSIGN_FROM_RESP(dma_axi_bus, clu_axi_wide_mst_resp) + + pulp_cluster #( + .Cfg ( Cfg.PulpCluCfgs[ClusterId] ) + ) cluster_i ( + .clk_i ( clu_clk_i ), + .rst_ni ( rst_ni ), + .pwr_on_rst_ni ( rst_ni ), + .ref_clk_i ( clu_clk_i ), + .axi_isolate_i ( '0 ), + .axi_isolated_o ( /* Unconnected */ ), + .axi_isolated_wide_o ( /* Unconnected */ ), + .pmu_mem_pwdn_i ( 1'b0 ), + .base_addr_i ( Cfg.PulpCluCfgs[ClusterId].ClusterBaseAddr[31:28] ), + .dma_pe_evt_ack_i ( '1 ), + .dma_pe_evt_valid_o ( /* Unconnected */ ), + .dma_pe_irq_ack_i ( 1'b1 ), + .dma_pe_irq_valid_o ( /* Unconnected */ ), + .dbg_irq_valid_i ( '0 ), + .mbox_irq_i ( '0 ), + .pf_evt_ack_i ( 1'b1 ), + .pf_evt_valid_o ( /* Unconnected */ ), + .async_cluster_events_wptr_i ( '0 ), + .async_cluster_events_rptr_o ( /* Unconnected */ ), + .async_cluster_events_data_i ( '0 ), + .en_sa_boot_i ( 1'b0 ), + .test_mode_i ( 1'b0 ), + .fetch_en_i ( 1'b0 ), + .eoc_o ( /* Unconnected */ ), + .busy_o ( /* Unconnected */ ), + .cluster_id_i ( ClusterId[5:0] ), + .async_data_master_aw_wptr_o ( async_cluster_to_soc_axi_bus.aw_wptr ), + .async_data_master_aw_rptr_i ( async_cluster_to_soc_axi_bus.aw_rptr ), + .async_data_master_aw_data_o ( async_cluster_to_soc_axi_bus.aw_data ), + .async_data_master_ar_wptr_o ( async_cluster_to_soc_axi_bus.ar_wptr ), + .async_data_master_ar_rptr_i ( async_cluster_to_soc_axi_bus.ar_rptr ), + .async_data_master_ar_data_o ( async_cluster_to_soc_axi_bus.ar_data ), + .async_data_master_w_data_o ( async_cluster_to_soc_axi_bus.w_data ), + .async_data_master_w_wptr_o ( async_cluster_to_soc_axi_bus.w_wptr ), + .async_data_master_w_rptr_i ( async_cluster_to_soc_axi_bus.w_rptr ), + .async_data_master_r_wptr_i ( async_cluster_to_soc_axi_bus.r_wptr ), + .async_data_master_r_rptr_o ( async_cluster_to_soc_axi_bus.r_rptr ), + .async_data_master_r_data_i ( async_cluster_to_soc_axi_bus.r_data ), + .async_data_master_b_wptr_i ( async_cluster_to_soc_axi_bus.b_wptr ), + .async_data_master_b_rptr_o ( async_cluster_to_soc_axi_bus.b_rptr ), + .async_data_master_b_data_i ( async_cluster_to_soc_axi_bus.b_data ), + .async_wide_master_aw_wptr_o ( async_dma_axi_bus.aw_wptr ), + .async_wide_master_aw_rptr_i ( async_dma_axi_bus.aw_rptr ), + .async_wide_master_aw_data_o ( async_dma_axi_bus.aw_data ), + .async_wide_master_ar_wptr_o ( async_dma_axi_bus.ar_wptr ), + .async_wide_master_ar_rptr_i ( async_dma_axi_bus.ar_rptr ), + .async_wide_master_ar_data_o ( async_dma_axi_bus.ar_data ), + .async_wide_master_w_data_o ( async_dma_axi_bus.w_data ), + .async_wide_master_w_wptr_o ( async_dma_axi_bus.w_wptr ), + .async_wide_master_w_rptr_i ( async_dma_axi_bus.w_rptr ), + .async_wide_master_r_wptr_i ( async_dma_axi_bus.r_wptr ), + .async_wide_master_r_rptr_o ( async_dma_axi_bus.r_rptr ), + .async_wide_master_r_data_i ( async_dma_axi_bus.r_data ), + .async_wide_master_b_wptr_i ( async_dma_axi_bus.b_wptr ), + .async_wide_master_b_rptr_o ( async_dma_axi_bus.b_rptr ), + .async_wide_master_b_data_i ( async_dma_axi_bus.b_data ), + .async_data_slave_aw_wptr_i ( async_soc_to_cluster_axi_bus.aw_wptr ), + .async_data_slave_aw_rptr_o ( async_soc_to_cluster_axi_bus.aw_rptr ), + .async_data_slave_aw_data_i ( async_soc_to_cluster_axi_bus.aw_data ), + .async_data_slave_ar_wptr_i ( async_soc_to_cluster_axi_bus.ar_wptr ), + .async_data_slave_ar_rptr_o ( async_soc_to_cluster_axi_bus.ar_rptr ), + .async_data_slave_ar_data_i ( async_soc_to_cluster_axi_bus.ar_data ), + .async_data_slave_w_data_i ( async_soc_to_cluster_axi_bus.w_data ), + .async_data_slave_w_wptr_i ( async_soc_to_cluster_axi_bus.w_wptr ), + .async_data_slave_w_rptr_o ( async_soc_to_cluster_axi_bus.w_rptr ), + .async_data_slave_r_wptr_o ( async_soc_to_cluster_axi_bus.r_wptr ), + .async_data_slave_r_rptr_i ( async_soc_to_cluster_axi_bus.r_rptr ), + .async_data_slave_r_data_o ( async_soc_to_cluster_axi_bus.r_data ), + .async_data_slave_b_wptr_o ( async_soc_to_cluster_axi_bus.b_wptr ), + .async_data_slave_b_rptr_i ( async_soc_to_cluster_axi_bus.b_rptr ), + .async_data_slave_b_data_o ( async_soc_to_cluster_axi_bus.b_data ) + ); + + /* Error */ + `else + $error("No cluster selected"); + `endif + endmodule diff --git a/hw/chimera_cluster_adapter.sv b/hw/chimera_cluster_adapter.sv index 7e8c97c..04a96de 100644 --- a/hw/chimera_cluster_adapter.sv +++ b/hw/chimera_cluster_adapter.sv @@ -30,7 +30,9 @@ module chimera_cluster_adapter #( ) ( input logic soc_clk_i, + `ifndef TARGET_PULP_CLUSTER input logic clu_clk_i, + `endif input logic rst_ni, // From SOC input narrow_in_req_t narrow_in_req_i, @@ -265,7 +267,11 @@ module chimera_cluster_adapter #( .mst_req_t (clu_narrow_in_req_t), .mst_resp_t(clu_narrow_in_resp_t) ) i_narrow_slv_to_narrow_mst_iw_converter ( + `ifndef TARGET_PULP_CLUSTER .clk_i (clu_clk_i), + `else + .clk_i (soc_clk_i), + `endif .rst_ni (rst_ni), .slv_req_i (axi_to_cluster_narrow_req), .slv_resp_o(axi_to_cluster_narrow_resp), @@ -294,7 +300,11 @@ module chimera_cluster_adapter #( .mst_req_t (narrow_out_req_t), .mst_resp_t (narrow_out_resp_t) ) narrow_mst_iw_converter ( + `ifndef TARGET_PULP_CLUSTER .clk_i (clu_clk_i), + `else + .clk_i (soc_clk_i), + `endif .rst_ni (rst_ni), .slv_req_i (axi_from_cluster_narrow_iwc_req), .slv_resp_o(axi_from_cluster_narrow_iwc_resp), @@ -322,7 +332,11 @@ module chimera_cluster_adapter #( .mst_req_t (wide_out_req_t), .mst_resp_t (wide_out_resp_t) ) wide_mst_iw_converter ( + `ifndef TARGET_PULP_CLUSTER .clk_i (clu_clk_i), + `else + .clk_i (soc_clk_i), + `endif .rst_ni (rst_ni), .slv_req_i (axi_from_cluster_wide_iwc_req), .slv_resp_o(axi_from_cluster_wide_iwc_resp), @@ -332,6 +346,7 @@ module chimera_cluster_adapter #( // AXI Narrow CDC from SoC to Cluster + `ifndef TARGET_PULP_CLUSTER axi_cdc #( .aw_chan_t (axi_narrow_soc_in_aw_chan_t), .w_chan_t (axi_narrow_soc_in_w_chan_t), @@ -351,9 +366,14 @@ module chimera_cluster_adapter #( .dst_req_o (axi_to_cluster_narrow_req), .dst_resp_i(axi_to_cluster_narrow_resp) ); + `else + assign axi_to_cluster_narrow_req = narrow_in_req_i; + assign narrow_in_resp_o = axi_to_cluster_narrow_resp; + `endif // AXI Narrow CDC from Cluster to SoC + `ifndef TARGET_PULP_CLUSTER axi_cdc #( .aw_chan_t (axi_narrow_soc_out_aw_chan_t), .w_chan_t (axi_narrow_soc_out_w_chan_t), @@ -373,9 +393,14 @@ module chimera_cluster_adapter #( .dst_req_o (narrow_out_req_o[0]), .dst_resp_i(narrow_out_resp_i[0]) ); + `else + assign narrow_out_req_o[0] = axi_from_cluster_narrow_req; + assign axi_from_cluster_narrow_resp = narrow_out_resp_i[0]; + `endif // AXI Wide CDC from Cluster to SoC + `ifndef TARGET_PULP_CLUSTER axi_cdc #( .aw_chan_t (axi_wide_clu_out_aw_chan_t), .w_chan_t (axi_wide_clu_out_w_chan_t), @@ -395,6 +420,10 @@ module chimera_cluster_adapter #( .dst_req_o (axi_from_cluster_wide_premux_req), .dst_resp_i(axi_from_cluster_wide_premux_resp) ); + `else + assign axi_from_cluster_wide_premux_req = axi_from_cluster_wide_req; + assign axi_from_cluster_wide_resp = axi_from_cluster_wide_premux_resp; + `endif // Validate parameters `ifndef VERILATOR @@ -402,14 +431,16 @@ module chimera_cluster_adapter #( write_wide_bypass : assert property ( - @(posedge clu_clk_i) ((axi_from_cluster_wide_premux_req.aw_valid & wide_mem_bypass_mode_i) |-> + @(posedge `ifndef TARGET_PULP_CLUSTER clu_clk_i `else soc_clk_i `endif) + ((axi_from_cluster_wide_premux_req.aw_valid & wide_mem_bypass_mode_i) |-> (axi_from_cluster_wide_to_narrow_req.aw_valid & ~axi_from_cluster_wide_memisl_req.aw_valid))) else $fatal(1, "Bypass Mode ON, but write request routed toward the Wide interconnect"); read_wide_bypass : assert property ( - @(posedge clu_clk_i) ((axi_from_cluster_wide_premux_req.ar_valid & wide_mem_bypass_mode_i) |-> + @(posedge `ifndef TARGET_PULP_CLUSTER clu_clk_i `else soc_clk_i `endif) + ((axi_from_cluster_wide_premux_req.ar_valid & wide_mem_bypass_mode_i) |-> (axi_from_cluster_wide_to_narrow_req.ar_valid & ~axi_from_cluster_wide_memisl_req.ar_valid))) else $fatal(1, "Bypass Mode ON, but read request routed toward the Wide interocnnect"); diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index ae90115..4d2441c 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -8,8 +8,10 @@ package chimera_pkg; import cheshire_pkg::*; + import pulp_cluster_package::*; `include "apb/typedef.svh" + `include "pulp_soc_defines.sv" // Bit vector types for parameters. //We limit range to keep parameters sane. @@ -30,7 +32,7 @@ package chimera_pkg; localparam cluster_config_t ChimeraClusterCfg = '{ hasWideMasterPort: {1'b1, 1'b1, 1'b1, 1'b1, 1'b1}, - NrCores: {8'h9, 8'h9, 8'h9, 8'h9, 8'h9} + NrCores: {8'h8, 8'h8, 8'h8, 8'h8, 8'h8} }; function automatic int _sumVector(byte_bt [iomsb(ExtClusters):0] vector, int vectorLen); @@ -50,6 +52,7 @@ package chimera_pkg; // Configuration struct for Chimer: it includes the Cheshire Cfg typedef struct packed { cheshire_cfg_t ChsCfg; + pulp_cluster_cfg_t [iomsb(ExtClusters):0] PulpCluCfgs; doub_bt MemIslRegionStart; doub_bt MemIslRegionEnd; aw_bt MemIslAxiMstIdWidth; @@ -61,19 +64,16 @@ package chimera_pkg; int unsigned IsolateClusters; } chimera_cfg_t; - // SoC Config + // ------------------------------- + // | External Register Interface | + // ------------------------------- localparam bit SnitchBootROM = 1; localparam bit TopLevelCfgRegs = 1; localparam bit ExtCfgRegs = 1; localparam bit HyperCfgRegs = 1; - // ------------------------------- - // | External Register Interface | - // ------------------------------- - // SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, External regs (PADs, FLLs etc...) localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs + HyperCfgRegs; - localparam int ClusterDataWidth = 64; localparam byte_bt SnitchBootROMIdx = 8'h0; localparam doub_bt SnitchBootROMRegionStart = 64'h3000_0000; @@ -99,18 +99,15 @@ package chimera_pkg; // Cluster domain localparam byte_bt [iomsb(ExtClusters):0] ClusterIdx = {8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; - localparam doub_bt [iomsb( -ExtClusters -):0] ClusterRegionStart = { - 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000, 64'h4000_0000 + localparam doub_bt [iomsb(ExtClusters):0] ClusterRegionStart = { + 64'h4100_0000, 64'h40C0_0000, 64'h4080_0000, 64'h4040_0000, 64'h4000_0000 }; - localparam doub_bt [iomsb( -ExtClusters -):0] ClusterRegionEnd = { - 64'h40A0_0000, 64'h4080_0000, 64'h4060_0000, 64'h4040_0000, 64'h4020_0000 + localparam doub_bt [iomsb(ExtClusters):0] ClusterRegionEnd = { + 64'h4140_0000, 64'h4100_0000, 64'h40C0_0000, 64'h4080_0000, 64'h4040_0000 }; localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; + localparam int ClusterDataWidth = 64; // Memory Island localparam byte_bt MemIslandIdx = ClusterIdx[ExtClusters-1] + 1; @@ -147,6 +144,7 @@ ExtClusters chimera_cfg_t chimera_cfg; cheshire_cfg_t cfg = DefaultCfg; + pulp_cluster_cfg_t [iomsb(ExtClusters):0] pulp_clu_cfgs; // Global CFG @@ -196,8 +194,58 @@ ExtClusters cfg.NumExtDbgHarts = ExtCores; cfg.NumExtOutIntrTgts = ExtCores; + // Fill up PULP Cluster config + `ifdef TARGET_PULP_CLUSTER + // Assign default PULP Cluster config + for (int i = 0; i < ExtClusters; i++) begin + pulp_clu_cfgs[i] = PulpClusterDefaultCfg; + end + // PULP Cluster configuration (common to all clusters) + for (int i = 0; i < ExtClusters; i++) begin + pulp_clu_cfgs[i].CoreType = RI5CY; + pulp_clu_cfgs[i].NumCores = `NB_CORES; + pulp_clu_cfgs[i].DmaNumPlugs = `NB_DMAS; + pulp_clu_cfgs[i].DmaUseHwpePort = 1; + pulp_clu_cfgs[i].NumMstPeriphs = `NB_MPERIPHS; + pulp_clu_cfgs[i].NumSlvPeriphs = `NB_SPERIPHS; + pulp_clu_cfgs[i].UseHci = 1; + pulp_clu_cfgs[i].TcdmSize = 128*1024; + pulp_clu_cfgs[i].TcdmNumBank = 16; + pulp_clu_cfgs[i].HwpePresent = 1; + pulp_clu_cfgs[i].HwpeCfg = '{NumHwpes: 1, HwpeList: {NEUREKA}}; + pulp_clu_cfgs[i].HwpeNumPorts = 9; + pulp_clu_cfgs[i].EnableECC = 0; + pulp_clu_cfgs[i].ECCInterco = 0; + pulp_clu_cfgs[i].L2Size = MemIslRegionEnd - MemIslRegionStart; + pulp_clu_cfgs[i].DmBaseAddr = '0; //TODO: Fix + pulp_clu_cfgs[i].BootRomBaseAddr = '0; //TODO: Fix + pulp_clu_cfgs[i].BootAddr = '0; //TODO: Fix + pulp_clu_cfgs[i].EnablePrivateFpu = 1; + pulp_clu_cfgs[i].EnablePrivateFpDivSqrt = 0; + pulp_clu_cfgs[i].EnableSharedFpu = 0; + pulp_clu_cfgs[i].EnableSharedFpDivSqrt = 0; + pulp_clu_cfgs[i].NumSharedFpu = 0; + pulp_clu_cfgs[i].EnableTnnExtension = 1; + pulp_clu_cfgs[i].EnableTnnUnsigned = 1; + pulp_clu_cfgs[i].AxiIdOutWideWidth = MemIslAxiMstIdWidth; + pulp_clu_cfgs[i].AxiAddrWidth = cfg.AddrWidth; + pulp_clu_cfgs[i].AxiDataInWidth = ClusterDataWidth; + pulp_clu_cfgs[i].AxiDataOutWidth = ClusterDataWidth; + pulp_clu_cfgs[i].AxiDataOutWideWidth = cfg.AxiDataWidth * + MemIslNarrowToWideFactor; + pulp_clu_cfgs[i].AxiUserWidth = cfg.AxiUserWidth; + pulp_clu_cfgs[i].AxiCdcLogDepth = 3; + pulp_clu_cfgs[i].ClusterBaseAddr = ClusterRegionStart[0]; + end + `else + for (int i = 0; i < ExtClusters; i++) begin + pulp_clu_cfgs[i] = '0; + end + `endif + chimera_cfg = '{ ChsCfg : cfg, + PulpCluCfgs : pulp_clu_cfgs, MemIslRegionStart : MemIslRegionStart, MemIslRegionEnd : MemIslRegionEnd, MemIslAxiMstIdWidth : MemIslAxiMstIdWidth, From 70e6e698c3c054f213628c111fbdba0c95a63f00 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 21 Feb 2025 16:06:20 +0100 Subject: [PATCH 6/9] hw: Parametrize Snitch bootrom instance and config --- hw/chimera_clu_domain.sv | 9 ++++++++- hw/chimera_pkg.sv | 39 ++++++++++++++++++++++++--------------- hw/chimera_top_wrapper.sv | 3 ++- 3 files changed, 34 insertions(+), 17 deletions(-) diff --git a/hw/chimera_clu_domain.sv b/hw/chimera_clu_domain.sv index 22eff25..63641dc 100644 --- a/hw/chimera_clu_domain.sv +++ b/hw/chimera_clu_domain.sv @@ -173,6 +173,13 @@ module chimera_clu_domain end : gen_no_cluster_iso + logic [31:0] boot_addr_clu = + `ifdef TARGET_SNITCH_CLUSTER + SnitchBootROMRegionStart[31:0] + `else + 'b0 + `endif; + chimera_cluster #( .Cfg (Cfg), .NrCores (`NRCORES(extClusterIdx)), @@ -194,7 +201,7 @@ module chimera_clu_domain .msip_i (msip_i[`PREVNRCORES(extClusterIdx)+:`NRCORES(extClusterIdx)]), .hart_base_id_i (10'(`PREVNRCORES(extClusterIdx) + 1)), .cluster_base_addr_i(Cfg.ChsCfg.AxiExtRegionStart[extClusterIdx][Cfg.ChsCfg.AddrWidth-1:0]), - .boot_addr_i (SnitchBootROMRegionStart[31:0]), + .boot_addr_i (boot_addr_clu), .narrow_in_req_i (narrow_in_isolated_req[extClusterIdx]), .narrow_in_resp_o (narrow_in_isolated_resp[extClusterIdx]), diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 4d2441c..2312f1c 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -67,7 +67,7 @@ package chimera_pkg; // ------------------------------- // | External Register Interface | // ------------------------------- - localparam bit SnitchBootROM = 1; + localparam bit SnitchBootROM = `ifdef TARGET_SNITCH_CLUSTER 1 `else 0 `endif; localparam bit TopLevelCfgRegs = 1; localparam bit ExtCfgRegs = 1; localparam bit HyperCfgRegs = 1; @@ -79,23 +79,27 @@ package chimera_pkg; localparam doub_bt SnitchBootROMRegionStart = 64'h3000_0000; localparam doub_bt SnitchBootROMRegionEnd = 64'h3000_1000; - localparam byte_bt TopLevelCfgRegsIdx = 8'h1; + localparam byte_bt TopLevelCfgRegsIdx = SnitchBootROM; localparam doub_bt TopLevelCfgRegsRegionStart = 64'h3000_1000; localparam doub_bt TopLevelCfgRegsRegionEnd = 64'h3000_2000; // External configuration registers: PADs, FLLs, PMU Controller - localparam byte_bt ExtCfgRegsIdx = 8'h2; + localparam byte_bt ExtCfgRegsIdx = SnitchBootROM + TopLevelCfgRegs; localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000; localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000; // Hyperbus configuration registers: HyperBus - localparam byte_bt HyperCfgRegsIdx = 8'h3; + localparam byte_bt HyperCfgRegsIdx = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs; localparam doub_bt HyperCfgRegsRegionStart = 64'h3000_5000; localparam doub_bt HyperCfgRegsRegionEnd = 64'h3000_6000; // -------------------------- // | External AXI ports | // -------------------------- + localparam bit MemoryIsland = 1'b1; + localparam bit Hyperbus = 1'b1; + + localparam int AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus; // Cluster domain localparam byte_bt [iomsb(ExtClusters):0] ClusterIdx = {8'h4, 8'h3, 8'h2, 8'h1, 8'h0}; @@ -110,7 +114,7 @@ package chimera_pkg; localparam int ClusterDataWidth = 64; // Memory Island - localparam byte_bt MemIslandIdx = ClusterIdx[ExtClusters-1] + 1; + localparam byte_bt MemIslandIdx = ExtClusters; localparam doub_bt MemIslRegionStart = 64'h4800_0000; localparam doub_bt MemIslRegionEnd = 64'h4804_0000; @@ -122,7 +126,7 @@ package chimera_pkg; localparam shrt_bt MemIslWordsPerBank = 1024; // Hyperbus - localparam byte_bt HyperbusIdx = MemIslandIdx + 1; + localparam byte_bt HyperbusIdx = ExtClusters + MemoryIsland; localparam doub_bt HyperbusRegionStart = 64'h5000_0000; //TODO(smazzola): Correct size of HyperRAM? localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h1000_0000; @@ -139,8 +143,6 @@ package chimera_pkg; function automatic chimera_cfg_t gen_chimera_cfg(); localparam int AddrWidth = DefaultCfg.AddrWidth; - localparam int MemoryIsland = 1; - localparam int Hyperbus = 1; chimera_cfg_t chimera_cfg; cheshire_cfg_t cfg = DefaultCfg; @@ -168,8 +170,8 @@ package chimera_pkg; // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort); - cfg.AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus; - cfg.AxiExtNumRules = ExtClusters + MemoryIsland + Hyperbus; + cfg.AxiExtNumSlv = AxiExtNumSlv; + cfg.AxiExtNumRules = AxiExtNumSlv; cfg.AxiExtRegionIdx = {HyperbusIdx, MemIslandIdx, ClusterIdx}; cfg.AxiExtRegionStart = {HyperbusRegionStart, MemIslRegionStart, ClusterRegionStart}; @@ -178,15 +180,23 @@ package chimera_pkg; // REG CFG cfg.RegExtNumSlv = ExtRegNum; cfg.RegExtNumRules = ExtRegNum; - cfg.RegExtRegionIdx = {HyperCfgRegsIdx, ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx}; + cfg.RegExtRegionIdx = { + HyperCfgRegsIdx, + ExtCfgRegsIdx, + TopLevelCfgRegsIdx + `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMIdx `endif + }; cfg.RegExtRegionStart = { HyperCfgRegsRegionStart, ExtCfgRegsRegionStart, - TopLevelCfgRegsRegionStart, - SnitchBootROMRegionStart + TopLevelCfgRegsRegionStart + `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMRegionStart `endif }; cfg.RegExtRegionEnd = { - HyperCfgRegsRegionEnd, ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd + HyperCfgRegsRegionEnd, + ExtCfgRegsRegionEnd, + TopLevelCfgRegsRegionEnd + `ifdef TARGET_SNITCH_CLUSTER , SnitchBootROMRegionEnd `endif }; // ACCEL HART/IRQ CFG @@ -276,7 +286,6 @@ package chimera_pkg; gen_chimera_cfg() // 0: Default configuration }; - localparam int unsigned RegDataWidth = 32; localparam type addr_t = logic [ChimeraCfg[0].ChsCfg.AddrWidth-1:0]; localparam type data_t = logic [RegDataWidth-1:0]; diff --git a/hw/chimera_top_wrapper.sv b/hw/chimera_top_wrapper.sv index 3f7325e..0d37383 100644 --- a/hw/chimera_top_wrapper.sv +++ b/hw/chimera_top_wrapper.sv @@ -261,7 +261,7 @@ module chimera_top_wrapper // SNITCH BOOTROM - + `ifdef TARGET_SNITCH_CLUSTER logic [31:0] snitch_bootrom_addr; logic [31:0] snitch_bootrom_data, snitch_bootrom_data_q; logic snitch_bootrom_req, snitch_bootrom_req_q; @@ -304,6 +304,7 @@ module chimera_top_wrapper .addr_i(snitch_bootrom_addr), .data_o(snitch_bootrom_data) ); + `endif logic [ExtClusters-1:0] wide_mem_bypass_mode; assign wide_mem_bypass_mode = { From 4c7b2b80a58d06b46373d7621102e3db73de3d3c Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 21 Feb 2025 16:15:32 +0100 Subject: [PATCH 7/9] [WIP] sw: Test addressability and sw offload to PULP Cluster - temporarily substitute sw memory map with PULP Cluster's ranges - add software for addressability and test offload --- sw/include/soc_addr_map.h | 20 ++--- sw/tests/testClusterAddr_pulp.c | 35 +++++++++ sw/tests/testClusterOffload_pulp.c | 101 ++++++++++++++++++++++++++ target/sim/vsim/setup.chimera_soc.tcl | 2 +- 4 files changed, 147 insertions(+), 11 deletions(-) create mode 100644 sw/tests/testClusterAddr_pulp.c create mode 100644 sw/tests/testClusterOffload_pulp.c diff --git a/sw/include/soc_addr_map.h b/sw/include/soc_addr_map.h index 6445608..783a185 100644 --- a/sw/include/soc_addr_map.h +++ b/sw/include/soc_addr_map.h @@ -15,16 +15,16 @@ #define SOC_CTRL_BASE 0x30001000 #define CLUSTER_0_BASE 0x40000000 -#define CLUSTER_1_BASE 0x40200000 -#define CLUSTER_2_BASE 0x40400000 -#define CLUSTER_3_BASE 0x40600000 -#define CLUSTER_4_BASE 0x40800000 - -#define CLUSTER_0_NUMCORES 9 -#define CLUSTER_1_NUMCORES 9 -#define CLUSTER_2_NUMCORES 9 -#define CLUSTER_3_NUMCORES 9 -#define CLUSTER_4_NUMCORES 9 +#define CLUSTER_1_BASE 0x40400000 +#define CLUSTER_2_BASE 0x40800000 +#define CLUSTER_3_BASE 0x40C00000 +#define CLUSTER_4_BASE 0x41000000 + +#define CLUSTER_0_NUMCORES 8 +#define CLUSTER_1_NUMCORES 8 +#define CLUSTER_2_NUMCORES 8 +#define CLUSTER_3_NUMCORES 8 +#define CLUSTER_4_NUMCORES 8 static uint8_t _chimera_numCores[] = {CLUSTER_0_NUMCORES, CLUSTER_1_NUMCORES, CLUSTER_2_NUMCORES, CLUSTER_3_NUMCORES, CLUSTER_4_NUMCORES}; diff --git a/sw/tests/testClusterAddr_pulp.c b/sw/tests/testClusterAddr_pulp.c new file mode 100644 index 0000000..4301e01 --- /dev/null +++ b/sw/tests/testClusterAddr_pulp.c @@ -0,0 +1,35 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Sergio Mazzola + +// Simple addressability test which writes and subsequently reads a value +// in the first address mapped to the PULP Cluster 0 (i.e., the first +// TCDM address) + +#include "offload.h" +#include "soc_addr_map.h" +#include +#include + +#define TESTVAL_CLUSTER 0xdeadbeef + +int main() { + uint8_t *base_addr_tcdm_cluster_0 = CLUSTER_0_BASE; + + *((uint32_t*)base_addr_tcdm_cluster_0) = TESTVAL_CLUSTER; + + asm volatile ("nop"); + asm volatile ("nop"); + asm volatile ("nop"); + asm volatile ("nop"); + asm volatile ("nop"); + + uint32_t result = *((uint32_t*)base_addr_tcdm_cluster_0); + if (result == TESTVAL_CLUSTER) { + return 0; + } else { + return 1; + } +} \ No newline at end of file diff --git a/sw/tests/testClusterOffload_pulp.c b/sw/tests/testClusterOffload_pulp.c new file mode 100644 index 0000000..72d95bc --- /dev/null +++ b/sw/tests/testClusterOffload_pulp.c @@ -0,0 +1,101 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Sergio Mazzola + +// Simple offload test to PULP Cluster 0. First set the boot address of all 8 +// cluster cores to the desired one (the simple test function), then enables the +// fetch enable for all cores at the same time. All this is done through writes +// to the cluster's peripheral interconnect. Does not currently take care of the +// cluster return value. + +#include "offload.h" +#include "soc_addr_map.h" +#include +#include + +#define TESTVAL_CLUSTER 0xdeadbeef + +#define PERIPH_OFFSET 0x00200000 + +#define FETCH_EN_OFFSET (PERIPH_OFFSET + 0x008) + +#define BOOT_ADDR_CORE_0_OFFSET (PERIPH_OFFSET + 0x040) +#define BOOT_ADDR_CORE_1_OFFSET (PERIPH_OFFSET + 0x044) +#define BOOT_ADDR_CORE_2_OFFSET (PERIPH_OFFSET + 0x048) +#define BOOT_ADDR_CORE_3_OFFSET (PERIPH_OFFSET + 0x04C) +#define BOOT_ADDR_CORE_4_OFFSET (PERIPH_OFFSET + 0x050) +#define BOOT_ADDR_CORE_5_OFFSET (PERIPH_OFFSET + 0x054) +#define BOOT_ADDR_CORE_6_OFFSET (PERIPH_OFFSET + 0x058) +#define BOOT_ADDR_CORE_7_OFFSET (PERIPH_OFFSET + 0x05C) +#define BOOT_ADDR_CORE_8_OFFSET (PERIPH_OFFSET + 0x060) +#define BOOT_ADDR_CORE_9_OFFSET (PERIPH_OFFSET + 0x064) +#define BOOT_ADDR_CORE_10_OFFSET (PERIPH_OFFSET + 0x068) +#define BOOT_ADDR_CORE_11_OFFSET (PERIPH_OFFSET + 0x06C) +#define BOOT_ADDR_CORE_12_OFFSET (PERIPH_OFFSET + 0x070) +#define BOOT_ADDR_CORE_13_OFFSET (PERIPH_OFFSET + 0x074) +#define BOOT_ADDR_CORE_14_OFFSET (PERIPH_OFFSET + 0x078) +#define BOOT_ADDR_CORE_15_OFFSET (PERIPH_OFFSET + 0x07C) + +int32_t test_cluster() { + int32_t result; + int32_t hart_id; + + asm volatile ("csrr %0, mhartid" : "=r"(hart_id)::); + + asm volatile ( + "li t0, %1\n" // Load immediate value into t0 + "mv a0, t0\n" // Move t0 into a0 (x10) + "mv %0, a0\n" // Move a0 into the output variable + : "=r"(result) // Output operand + : "i"(TESTVAL_CLUSTER) // Input operand: immediate value + : "t0", "a0" // Clobbered registers + ); + + result = result + hart_id; + + return result; +} + +int main() { + int32_t hart_id; + asm volatile ("csrr %0, mhartid" : "=r"(hart_id)::); + + // set boot address of all cores in cluster 0 + uint8_t *boot_addr_core_0_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_0_OFFSET; + uint8_t *boot_addr_core_1_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_1_OFFSET; + uint8_t *boot_addr_core_2_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_2_OFFSET; + uint8_t *boot_addr_core_3_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_3_OFFSET; + uint8_t *boot_addr_core_4_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_4_OFFSET; + uint8_t *boot_addr_core_5_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_5_OFFSET; + uint8_t *boot_addr_core_6_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_6_OFFSET; + uint8_t *boot_addr_core_7_cluster_0 = CLUSTER_0_BASE + BOOT_ADDR_CORE_7_OFFSET; + + *((uint32_t*)boot_addr_core_0_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_1_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_2_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_3_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_4_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_5_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_6_cluster_0) = test_cluster; + *((uint32_t*)boot_addr_core_7_cluster_0) = test_cluster; + + // enable fetch for all cores in cluster 0 + uint8_t *fetch_en_cluster_0 = CLUSTER_0_BASE + FETCH_EN_OFFSET; + + *((uint32_t*)fetch_en_cluster_0) = 0x00FF; + + // only the host hart executes this + volatile int count = 100; + if (hart_id == 0) { + // delay loop + asm volatile ( + "1: nop\n" + "addi %0, %0, -1\n" + "bnez %0, 1b\n" + : "+r"(count) // Input and output operand + ); + } + return count; +} \ No newline at end of file diff --git a/target/sim/vsim/setup.chimera_soc.tcl b/target/sim/vsim/setup.chimera_soc.tcl index 0876587..f9dd142 100644 --- a/target/sim/vsim/setup.chimera_soc.tcl +++ b/target/sim/vsim/setup.chimera_soc.tcl @@ -4,5 +4,5 @@ # # Moritz Scherer -set BINARY ../../../sw/tests/testCluster.memisl.elf +set BINARY ../../../sw/tests/testClusterAddr_pulp.memisl.elf set SELCFG 0 From 08f6ab0b7ef2acbd69ac34b8b99ba4d396a21f9d Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Fri, 28 Feb 2025 15:15:09 +0100 Subject: [PATCH 8/9] hw,sw: Remove Snitch name from Cluster SoC regs and regenerate --- hw/bootrom/snitch/snitch_startup.c | 10 +-- hw/regs/chimera_reg_pkg.sv | 50 +++++------ hw/regs/chimera_reg_top.sv | 130 ++++++++++++++--------------- hw/regs/chimera_regs.hjson | 20 ++--- sw/include/regs/soc_ctrl.h | 28 +++---- sw/lib/offload.c | 10 +-- 6 files changed, 124 insertions(+), 124 deletions(-) diff --git a/hw/bootrom/snitch/snitch_startup.c b/hw/bootrom/snitch/snitch_startup.c index a484822..c84197d 100644 --- a/hw/bootrom/snitch/snitch_startup.c +++ b/hw/bootrom/snitch/snitch_startup.c @@ -40,23 +40,23 @@ void cluster_return(uint32_t ret) { switch (hartId) { case 1: - *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_0_RETURN_REG_OFFSET)) = + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_0_RETURN_REG_OFFSET)) = retVal; break; case 1 + CLUSTER_0_NUMCORES: - *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET)) = + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_1_RETURN_REG_OFFSET)) = retVal; break; case 1 + CLUSTER_0_NUMCORES + CLUSTER_1_NUMCORES: - *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET)) = + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_2_RETURN_REG_OFFSET)) = retVal; break; case 1 + CLUSTER_0_NUMCORES + CLUSTER_1_NUMCORES + CLUSTER_2_NUMCORES: - *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET)) = + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_3_RETURN_REG_OFFSET)) = retVal; break; case 1 + CLUSTER_0_NUMCORES + CLUSTER_1_NUMCORES + CLUSTER_2_NUMCORES + CLUSTER_3_NUMCORES: - *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET)) = + *((volatile uint32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_4_RETURN_REG_OFFSET)) = retVal; break; } diff --git a/hw/regs/chimera_reg_pkg.sv b/hw/regs/chimera_reg_pkg.sv index e5dd6a1..d786301 100644 --- a/hw/regs/chimera_reg_pkg.sv +++ b/hw/regs/chimera_reg_pkg.sv @@ -23,23 +23,23 @@ package chimera_reg_pkg; typedef struct packed { logic [31:0] q; - } chimera_reg2hw_snitch_cluster_0_return_reg_t; + } chimera_reg2hw_cluster_0_return_reg_t; typedef struct packed { logic [31:0] q; - } chimera_reg2hw_snitch_cluster_1_return_reg_t; + } chimera_reg2hw_cluster_1_return_reg_t; typedef struct packed { logic [31:0] q; - } chimera_reg2hw_snitch_cluster_2_return_reg_t; + } chimera_reg2hw_cluster_2_return_reg_t; typedef struct packed { logic [31:0] q; - } chimera_reg2hw_snitch_cluster_3_return_reg_t; + } chimera_reg2hw_cluster_3_return_reg_t; typedef struct packed { logic [31:0] q; - } chimera_reg2hw_snitch_cluster_4_return_reg_t; + } chimera_reg2hw_cluster_4_return_reg_t; typedef struct packed { logic q; @@ -105,11 +105,11 @@ package chimera_reg_pkg; typedef struct packed { chimera_reg2hw_snitch_boot_addr_reg_t snitch_boot_addr; // [238:207] chimera_reg2hw_snitch_intr_handler_addr_reg_t snitch_intr_handler_addr; // [206:175] - chimera_reg2hw_snitch_cluster_0_return_reg_t snitch_cluster_0_return; // [174:143] - chimera_reg2hw_snitch_cluster_1_return_reg_t snitch_cluster_1_return; // [142:111] - chimera_reg2hw_snitch_cluster_2_return_reg_t snitch_cluster_2_return; // [110:79] - chimera_reg2hw_snitch_cluster_3_return_reg_t snitch_cluster_3_return; // [78:47] - chimera_reg2hw_snitch_cluster_4_return_reg_t snitch_cluster_4_return; // [46:15] + chimera_reg2hw_cluster_0_return_reg_t cluster_0_return; // [174:143] + chimera_reg2hw_cluster_1_return_reg_t cluster_1_return; // [142:111] + chimera_reg2hw_cluster_2_return_reg_t cluster_2_return; // [110:79] + chimera_reg2hw_cluster_3_return_reg_t cluster_3_return; // [78:47] + chimera_reg2hw_cluster_4_return_reg_t cluster_4_return; // [46:15] chimera_reg2hw_cluster_0_clk_gate_en_reg_t cluster_0_clk_gate_en; // [14:14] chimera_reg2hw_cluster_1_clk_gate_en_reg_t cluster_1_clk_gate_en; // [13:13] chimera_reg2hw_cluster_2_clk_gate_en_reg_t cluster_2_clk_gate_en; // [12:12] @@ -130,11 +130,11 @@ package chimera_reg_pkg; // Register offsets parameter logic [BlockAw-1:0] CHIMERA_SNITCH_BOOT_ADDR_OFFSET = 7'h 0; parameter logic [BlockAw-1:0] CHIMERA_SNITCH_INTR_HANDLER_ADDR_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_0_RETURN_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_1_RETURN_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_2_RETURN_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_3_RETURN_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] CHIMERA_SNITCH_CLUSTER_4_RETURN_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_0_RETURN_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_1_RETURN_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_2_RETURN_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_3_RETURN_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_4_RETURN_OFFSET = 7'h 18; parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_0_CLK_GATE_EN_OFFSET = 7'h 1c; parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_1_CLK_GATE_EN_OFFSET = 7'h 20; parameter logic [BlockAw-1:0] CHIMERA_CLUSTER_2_CLK_GATE_EN_OFFSET = 7'h 24; @@ -155,11 +155,11 @@ package chimera_reg_pkg; typedef enum int { CHIMERA_SNITCH_BOOT_ADDR, CHIMERA_SNITCH_INTR_HANDLER_ADDR, - CHIMERA_SNITCH_CLUSTER_0_RETURN, - CHIMERA_SNITCH_CLUSTER_1_RETURN, - CHIMERA_SNITCH_CLUSTER_2_RETURN, - CHIMERA_SNITCH_CLUSTER_3_RETURN, - CHIMERA_SNITCH_CLUSTER_4_RETURN, + CHIMERA_CLUSTER_0_RETURN, + CHIMERA_CLUSTER_1_RETURN, + CHIMERA_CLUSTER_2_RETURN, + CHIMERA_CLUSTER_3_RETURN, + CHIMERA_CLUSTER_4_RETURN, CHIMERA_CLUSTER_0_CLK_GATE_EN, CHIMERA_CLUSTER_1_CLK_GATE_EN, CHIMERA_CLUSTER_2_CLK_GATE_EN, @@ -181,11 +181,11 @@ package chimera_reg_pkg; parameter logic [3:0] CHIMERA_PERMIT [22] = '{ 4'b 1111, // index[ 0] CHIMERA_SNITCH_BOOT_ADDR 4'b 1111, // index[ 1] CHIMERA_SNITCH_INTR_HANDLER_ADDR - 4'b 1111, // index[ 2] CHIMERA_SNITCH_CLUSTER_0_RETURN - 4'b 1111, // index[ 3] CHIMERA_SNITCH_CLUSTER_1_RETURN - 4'b 1111, // index[ 4] CHIMERA_SNITCH_CLUSTER_2_RETURN - 4'b 1111, // index[ 5] CHIMERA_SNITCH_CLUSTER_3_RETURN - 4'b 1111, // index[ 6] CHIMERA_SNITCH_CLUSTER_4_RETURN + 4'b 1111, // index[ 2] CHIMERA_CLUSTER_0_RETURN + 4'b 1111, // index[ 3] CHIMERA_CLUSTER_1_RETURN + 4'b 1111, // index[ 4] CHIMERA_CLUSTER_2_RETURN + 4'b 1111, // index[ 5] CHIMERA_CLUSTER_3_RETURN + 4'b 1111, // index[ 6] CHIMERA_CLUSTER_4_RETURN 4'b 0001, // index[ 7] CHIMERA_CLUSTER_0_CLK_GATE_EN 4'b 0001, // index[ 8] CHIMERA_CLUSTER_1_CLK_GATE_EN 4'b 0001, // index[ 9] CHIMERA_CLUSTER_2_CLK_GATE_EN diff --git a/hw/regs/chimera_reg_top.sv b/hw/regs/chimera_reg_top.sv index 65f21d8..22443c5 100644 --- a/hw/regs/chimera_reg_top.sv +++ b/hw/regs/chimera_reg_top.sv @@ -73,21 +73,21 @@ module chimera_reg_top #( logic [31:0] snitch_intr_handler_addr_qs; logic [31:0] snitch_intr_handler_addr_wd; logic snitch_intr_handler_addr_we; - logic [31:0] snitch_cluster_0_return_qs; - logic [31:0] snitch_cluster_0_return_wd; - logic snitch_cluster_0_return_we; - logic [31:0] snitch_cluster_1_return_qs; - logic [31:0] snitch_cluster_1_return_wd; - logic snitch_cluster_1_return_we; - logic [31:0] snitch_cluster_2_return_qs; - logic [31:0] snitch_cluster_2_return_wd; - logic snitch_cluster_2_return_we; - logic [31:0] snitch_cluster_3_return_qs; - logic [31:0] snitch_cluster_3_return_wd; - logic snitch_cluster_3_return_we; - logic [31:0] snitch_cluster_4_return_qs; - logic [31:0] snitch_cluster_4_return_wd; - logic snitch_cluster_4_return_we; + logic [31:0] cluster_0_return_qs; + logic [31:0] cluster_0_return_wd; + logic cluster_0_return_we; + logic [31:0] cluster_1_return_qs; + logic [31:0] cluster_1_return_wd; + logic cluster_1_return_we; + logic [31:0] cluster_2_return_qs; + logic [31:0] cluster_2_return_wd; + logic cluster_2_return_we; + logic [31:0] cluster_3_return_qs; + logic [31:0] cluster_3_return_wd; + logic cluster_3_return_we; + logic [31:0] cluster_4_return_qs; + logic [31:0] cluster_4_return_wd; + logic cluster_4_return_we; logic cluster_0_clk_gate_en_qs; logic cluster_0_clk_gate_en_wd; logic cluster_0_clk_gate_en_we; @@ -189,19 +189,19 @@ module chimera_reg_top #( ); - // R[snitch_cluster_0_return]: V(False) + // R[cluster_0_return]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_snitch_cluster_0_return ( + ) u_cluster_0_return ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (snitch_cluster_0_return_we), - .wd (snitch_cluster_0_return_wd), + .we (cluster_0_return_we), + .wd (cluster_0_return_wd), // from internal hardware .de (1'b0), @@ -209,26 +209,26 @@ module chimera_reg_top #( // to internal hardware .qe (), - .q (reg2hw.snitch_cluster_0_return.q ), + .q (reg2hw.cluster_0_return.q ), // to register interface (read) - .qs (snitch_cluster_0_return_qs) + .qs (cluster_0_return_qs) ); - // R[snitch_cluster_1_return]: V(False) + // R[cluster_1_return]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_snitch_cluster_1_return ( + ) u_cluster_1_return ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (snitch_cluster_1_return_we), - .wd (snitch_cluster_1_return_wd), + .we (cluster_1_return_we), + .wd (cluster_1_return_wd), // from internal hardware .de (1'b0), @@ -236,26 +236,26 @@ module chimera_reg_top #( // to internal hardware .qe (), - .q (reg2hw.snitch_cluster_1_return.q ), + .q (reg2hw.cluster_1_return.q ), // to register interface (read) - .qs (snitch_cluster_1_return_qs) + .qs (cluster_1_return_qs) ); - // R[snitch_cluster_2_return]: V(False) + // R[cluster_2_return]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_snitch_cluster_2_return ( + ) u_cluster_2_return ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (snitch_cluster_2_return_we), - .wd (snitch_cluster_2_return_wd), + .we (cluster_2_return_we), + .wd (cluster_2_return_wd), // from internal hardware .de (1'b0), @@ -263,26 +263,26 @@ module chimera_reg_top #( // to internal hardware .qe (), - .q (reg2hw.snitch_cluster_2_return.q ), + .q (reg2hw.cluster_2_return.q ), // to register interface (read) - .qs (snitch_cluster_2_return_qs) + .qs (cluster_2_return_qs) ); - // R[snitch_cluster_3_return]: V(False) + // R[cluster_3_return]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_snitch_cluster_3_return ( + ) u_cluster_3_return ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (snitch_cluster_3_return_we), - .wd (snitch_cluster_3_return_wd), + .we (cluster_3_return_we), + .wd (cluster_3_return_wd), // from internal hardware .de (1'b0), @@ -290,26 +290,26 @@ module chimera_reg_top #( // to internal hardware .qe (), - .q (reg2hw.snitch_cluster_3_return.q ), + .q (reg2hw.cluster_3_return.q ), // to register interface (read) - .qs (snitch_cluster_3_return_qs) + .qs (cluster_3_return_qs) ); - // R[snitch_cluster_4_return]: V(False) + // R[cluster_4_return]: V(False) prim_subreg #( .DW (32), .SWACCESS("RW"), .RESVAL (32'h0) - ) u_snitch_cluster_4_return ( + ) u_cluster_4_return ( .clk_i (clk_i ), .rst_ni (rst_ni ), // from register interface - .we (snitch_cluster_4_return_we), - .wd (snitch_cluster_4_return_wd), + .we (cluster_4_return_we), + .wd (cluster_4_return_wd), // from internal hardware .de (1'b0), @@ -317,10 +317,10 @@ module chimera_reg_top #( // to internal hardware .qe (), - .q (reg2hw.snitch_cluster_4_return.q ), + .q (reg2hw.cluster_4_return.q ), // to register interface (read) - .qs (snitch_cluster_4_return_qs) + .qs (cluster_4_return_qs) ); @@ -736,11 +736,11 @@ module chimera_reg_top #( addr_hit = '0; addr_hit[ 0] = (reg_addr == CHIMERA_SNITCH_BOOT_ADDR_OFFSET); addr_hit[ 1] = (reg_addr == CHIMERA_SNITCH_INTR_HANDLER_ADDR_OFFSET); - addr_hit[ 2] = (reg_addr == CHIMERA_SNITCH_CLUSTER_0_RETURN_OFFSET); - addr_hit[ 3] = (reg_addr == CHIMERA_SNITCH_CLUSTER_1_RETURN_OFFSET); - addr_hit[ 4] = (reg_addr == CHIMERA_SNITCH_CLUSTER_2_RETURN_OFFSET); - addr_hit[ 5] = (reg_addr == CHIMERA_SNITCH_CLUSTER_3_RETURN_OFFSET); - addr_hit[ 6] = (reg_addr == CHIMERA_SNITCH_CLUSTER_4_RETURN_OFFSET); + addr_hit[ 2] = (reg_addr == CHIMERA_CLUSTER_0_RETURN_OFFSET); + addr_hit[ 3] = (reg_addr == CHIMERA_CLUSTER_1_RETURN_OFFSET); + addr_hit[ 4] = (reg_addr == CHIMERA_CLUSTER_2_RETURN_OFFSET); + addr_hit[ 5] = (reg_addr == CHIMERA_CLUSTER_3_RETURN_OFFSET); + addr_hit[ 6] = (reg_addr == CHIMERA_CLUSTER_4_RETURN_OFFSET); addr_hit[ 7] = (reg_addr == CHIMERA_CLUSTER_0_CLK_GATE_EN_OFFSET); addr_hit[ 8] = (reg_addr == CHIMERA_CLUSTER_1_CLK_GATE_EN_OFFSET); addr_hit[ 9] = (reg_addr == CHIMERA_CLUSTER_2_CLK_GATE_EN_OFFSET); @@ -793,20 +793,20 @@ module chimera_reg_top #( assign snitch_intr_handler_addr_we = addr_hit[1] & reg_we & !reg_error; assign snitch_intr_handler_addr_wd = reg_wdata[31:0]; - assign snitch_cluster_0_return_we = addr_hit[2] & reg_we & !reg_error; - assign snitch_cluster_0_return_wd = reg_wdata[31:0]; + assign cluster_0_return_we = addr_hit[2] & reg_we & !reg_error; + assign cluster_0_return_wd = reg_wdata[31:0]; - assign snitch_cluster_1_return_we = addr_hit[3] & reg_we & !reg_error; - assign snitch_cluster_1_return_wd = reg_wdata[31:0]; + assign cluster_1_return_we = addr_hit[3] & reg_we & !reg_error; + assign cluster_1_return_wd = reg_wdata[31:0]; - assign snitch_cluster_2_return_we = addr_hit[4] & reg_we & !reg_error; - assign snitch_cluster_2_return_wd = reg_wdata[31:0]; + assign cluster_2_return_we = addr_hit[4] & reg_we & !reg_error; + assign cluster_2_return_wd = reg_wdata[31:0]; - assign snitch_cluster_3_return_we = addr_hit[5] & reg_we & !reg_error; - assign snitch_cluster_3_return_wd = reg_wdata[31:0]; + assign cluster_3_return_we = addr_hit[5] & reg_we & !reg_error; + assign cluster_3_return_wd = reg_wdata[31:0]; - assign snitch_cluster_4_return_we = addr_hit[6] & reg_we & !reg_error; - assign snitch_cluster_4_return_wd = reg_wdata[31:0]; + assign cluster_4_return_we = addr_hit[6] & reg_we & !reg_error; + assign cluster_4_return_wd = reg_wdata[31:0]; assign cluster_0_clk_gate_en_we = addr_hit[7] & reg_we & !reg_error; assign cluster_0_clk_gate_en_wd = reg_wdata[0]; @@ -866,23 +866,23 @@ module chimera_reg_top #( end addr_hit[2]: begin - reg_rdata_next[31:0] = snitch_cluster_0_return_qs; + reg_rdata_next[31:0] = cluster_0_return_qs; end addr_hit[3]: begin - reg_rdata_next[31:0] = snitch_cluster_1_return_qs; + reg_rdata_next[31:0] = cluster_1_return_qs; end addr_hit[4]: begin - reg_rdata_next[31:0] = snitch_cluster_2_return_qs; + reg_rdata_next[31:0] = cluster_2_return_qs; end addr_hit[5]: begin - reg_rdata_next[31:0] = snitch_cluster_3_return_qs; + reg_rdata_next[31:0] = cluster_3_return_qs; end addr_hit[6]: begin - reg_rdata_next[31:0] = snitch_cluster_4_return_qs; + reg_rdata_next[31:0] = cluster_4_return_qs; end addr_hit[7]: begin diff --git a/hw/regs/chimera_regs.hjson b/hw/regs/chimera_regs.hjson index 53911f3..0a8c137 100644 --- a/hw/regs/chimera_regs.hjson +++ b/hw/regs/chimera_regs.hjson @@ -34,8 +34,8 @@ ], } { - name: "SNITCH_CLUSTER_0_RETURN", - desc: "Register to store return value of Snitch cluster 0", + name: "CLUSTER_0_RETURN", + desc: "Register to store return value of cluster 0", swaccess: "rw", hwaccess: "hro", resval: "0", @@ -46,8 +46,8 @@ } { - name: "SNITCH_CLUSTER_1_RETURN", - desc: "Register to store return value of Snitch cluster 1", + name: "CLUSTER_1_RETURN", + desc: "Register to store return value of cluster 1", swaccess: "rw", hwaccess: "hro", resval: "0", @@ -58,8 +58,8 @@ } { - name: "SNITCH_CLUSTER_2_RETURN", - desc: "Register to store return value of Snitch cluster 2", + name: "CLUSTER_2_RETURN", + desc: "Register to store return value of cluster 2", swaccess: "rw", hwaccess: "hro", resval: "0", @@ -70,8 +70,8 @@ } { - name: "SNITCH_CLUSTER_3_RETURN", - desc: "Register to store return value of Snitch cluster 3", + name: "CLUSTER_3_RETURN", + desc: "Register to store return value of cluster 3", swaccess: "rw", hwaccess: "hro", resval: "0", @@ -82,8 +82,8 @@ } { - name: "SNITCH_CLUSTER_4_RETURN", - desc: "Register to store return value of Snitch cluster 4", + name: "CLUSTER_4_RETURN", + desc: "Register to store return value of cluster 4", swaccess: "rw", hwaccess: "hro", resval: "0", diff --git a/sw/include/regs/soc_ctrl.h b/sw/include/regs/soc_ctrl.h index ca0d3b0..2d6e289 100644 --- a/sw/include/regs/soc_ctrl.h +++ b/sw/include/regs/soc_ctrl.h @@ -4,7 +4,7 @@ // Copyright 2024 ETH Zurich and University of Bologna. // Licensing information found in source file: -// +// // SPDX-License-Identifier: SHL-0.51 #ifndef _CHIMERA_REG_DEFS_ @@ -22,20 +22,20 @@ extern "C" { // Set interrupt handler address for all snitch cores #define CHIMERA_SNITCH_INTR_HANDLER_ADDR_REG_OFFSET 0x4 -// Register to store return value of Snitch cluster 0 -#define CHIMERA_SNITCH_CLUSTER_0_RETURN_REG_OFFSET 0x8 +// Register to store return value of cluster 0 +#define CHIMERA_CLUSTER_0_RETURN_REG_OFFSET 0x8 -// Register to store return value of Snitch cluster 1 -#define CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET 0xc +// Register to store return value of cluster 1 +#define CHIMERA_CLUSTER_1_RETURN_REG_OFFSET 0xc -// Register to store return value of Snitch cluster 2 -#define CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET 0x10 +// Register to store return value of cluster 2 +#define CHIMERA_CLUSTER_2_RETURN_REG_OFFSET 0x10 -// Register to store return value of Snitch cluster 3 -#define CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET 0x14 +// Register to store return value of cluster 3 +#define CHIMERA_CLUSTER_3_RETURN_REG_OFFSET 0x14 -// Register to store return value of Snitch cluster 4 -#define CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET 0x18 +// Register to store return value of cluster 4 +#define CHIMERA_CLUSTER_4_RETURN_REG_OFFSET 0x18 // Enable clock gate for cluster 0 #define CHIMERA_CLUSTER_0_CLK_GATE_EN_REG_OFFSET 0x1c @@ -98,7 +98,7 @@ extern "C" { #define CHIMERA_CLUSTER_4_BUSY_CLUSTER_4_BUSY_BIT 0 #ifdef __cplusplus -} // extern "C" +} // extern "C" #endif -#endif // _CHIMERA_REG_DEFS_ - // End generated register defines for chimera \ No newline at end of file +#endif // _CHIMERA_REG_DEFS_ +// End generated register defines for chimera \ No newline at end of file diff --git a/sw/lib/offload.c b/sw/lib/offload.c index c7a6040..ae8f533 100644 --- a/sw/lib/offload.c +++ b/sw/lib/offload.c @@ -65,19 +65,19 @@ uint32_t waitForCluster(uint8_t clusterId) { volatile int32_t *snitchReturnAddr; if (clusterId == 0) { snitchReturnAddr = - (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_0_RETURN_REG_OFFSET); + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_0_RETURN_REG_OFFSET); } else if (clusterId == 1) { snitchReturnAddr = - (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET); + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_1_RETURN_REG_OFFSET); } else if (clusterId == 2) { snitchReturnAddr = - (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET); + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_2_RETURN_REG_OFFSET); } else if (clusterId == 3) { snitchReturnAddr = - (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET); + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_3_RETURN_REG_OFFSET); } else if (clusterId == 4) { snitchReturnAddr = - (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET); + (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_4_RETURN_REG_OFFSET); } while (*snitchReturnAddr == 0) { From 648875d8cda925c5c829a797f173fcd8acb88bb6 Mon Sep 17 00:00:00 2001 From: Sergio Mazzola Date: Wed, 12 Mar 2025 17:32:11 +0100 Subject: [PATCH 9/9] hw: :bug: Fix cluster-side AXI ID widths --- hw/chimera_cluster.sv | 2 +- hw/chimera_pkg.sv | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/chimera_cluster.sv b/hw/chimera_cluster.sv index 0bb1a27..ce1cf4d 100644 --- a/hw/chimera_cluster.sv +++ b/hw/chimera_cluster.sv @@ -75,7 +75,7 @@ module chimera_cluster typedef logic [WideDataWidth/8-1:0] axi_cluster_strb_wide_t; typedef logic [ClusterNarrowAxiMstIdWidth-1:0] axi_cluster_mst_id_width_narrow_t; - typedef logic [ClusterNarrowAxiMstIdWidth-1+2:0] axi_cluster_slv_id_width_narrow_t; + typedef logic [ClusterNarrowAxiSlvIdWidth-1:0] axi_cluster_slv_id_width_narrow_t; typedef logic [NarrowMasterIdWidth-1:0] axi_soc_mst_id_width_narrow_t; typedef logic [NarrowSlaveIdWidth-1:0] axi_soc_slv_id_width_narrow_t; diff --git a/hw/chimera_pkg.sv b/hw/chimera_pkg.sv index 2312f1c..e625f4d 100644 --- a/hw/chimera_pkg.sv +++ b/hw/chimera_pkg.sv @@ -110,7 +110,8 @@ package chimera_pkg; 64'h4140_0000, 64'h4100_0000, 64'h40C0_0000, 64'h4080_0000, 64'h4040_0000 }; - localparam aw_bt ClusterNarrowAxiMstIdWidth = 1; + localparam aw_bt ClusterNarrowAxiMstIdWidth = `ifdef TARGET_PULP_CLUSTER pulp_cluster_package::AxiSubordinateIdwidth `else 1 `endif; + localparam aw_bt ClusterNarrowAxiSlvIdWidth = `ifdef TARGET_PULP_CLUSTER pulp_cluster_package::AxiManagerIdwidth `else ClusterNarrowAxiMstIdWidth + 2 `endif; localparam int ClusterDataWidth = 64; // Memory Island @@ -237,6 +238,8 @@ package chimera_pkg; pulp_clu_cfgs[i].NumSharedFpu = 0; pulp_clu_cfgs[i].EnableTnnExtension = 1; pulp_clu_cfgs[i].EnableTnnUnsigned = 1; + pulp_clu_cfgs[i].AxiIdInWidth = pulp_cluster_package::AxiSubordinateIdwidth; + pulp_clu_cfgs[i].AxiIdOutWidth = pulp_cluster_package::AxiManagerIdwidth; pulp_clu_cfgs[i].AxiIdOutWideWidth = MemIslAxiMstIdWidth; pulp_clu_cfgs[i].AxiAddrWidth = cfg.AddrWidth; pulp_clu_cfgs[i].AxiDataInWidth = ClusterDataWidth;