diff --git a/rtl/basic/hwpe_stream_fence.sv b/rtl/basic/hwpe_stream_fence.sv
index ba8bc29..89556b3 100644
--- a/rtl/basic/hwpe_stream_fence.sv
+++ b/rtl/basic/hwpe_stream_fence.sv
@@ -29,20 +29,23 @@
  * .. _hwpe_stream_fence_params:
  * .. table:: **hwpe_stream_fence** design-time parameters.
  *
- *   +------------------+-------------+---------------------------------------------+
- *   | **Name**         | **Default** | **Description**                             |
- *   +------------------+-------------+---------------------------------------------+
- *   | *NB_STREAMS*     | 2           | Number of input/output HWPE-Stream streams. |
- *   +------------------+-------------+---------------------------------------------+
- *   | *DATA_WIDTH*     | 32          | Width of the HWPE-Stream streams.           |
- *   +------------------+-------------+---------------------------------------------+
+ *   +------------------+----------------+---------------------------------------------+
+ *   | **Name**         | **Default**    | **Description**                             |
+ *   +------------------+----------------+---------------------------------------------+
+ *   | *NB_STREAMS*     | 2              | Number of input/output HWPE-Stream streams. |
+ *   +------------------+----------------+---------------------------------------------+
+ *   | *DATA_WIDTH*     | 32             | Width of the HWPE-Stream streams.           |
+ *   +------------------+----------------+---------------------------------------------+
+ *   | *STRB_WIDTH*     | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal.     |
+ *   +------------------+----------------+---------------------------------------------+
  */
 
 import hwpe_stream_package::*;
 
 module hwpe_stream_fence #(
   parameter int unsigned NB_STREAMS = 2,
-  parameter int unsigned DATA_WIDTH = 32
+  parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8
 )
 (
   input  logic clk_i,
@@ -59,7 +62,7 @@ module hwpe_stream_fence #(
   logic                  out_valid;
   logic [NB_STREAMS-1:0] fence_state_q, fence_state_d;
   logic [NB_STREAMS-1:0][DATA_WIDTH-1:0]   data_q;
-  logic [NB_STREAMS-1:0][DATA_WIDTH/8-1:0] strb_q;
+  logic [NB_STREAMS-1:0][STRB_WIDTH-1:0] strb_q;
 
   generate
     for(genvar ii=0; ii<NB_STREAMS; ii++) begin : binding
diff --git a/rtl/basic/hwpe_stream_merge.sv b/rtl/basic/hwpe_stream_merge.sv
index 7e78ef4..e496199 100644
--- a/rtl/basic/hwpe_stream_merge.sv
+++ b/rtl/basic/hwpe_stream_merge.sv
@@ -35,20 +35,23 @@
  * .. _hwpe_stream_merge_params:
  * .. table:: **hwpe_stream_merge** design-time parameters.
  *
- *   +------------------+-------------+---------------------------------------------+
- *   | **Name**         | **Default** | **Description**                             |
- *   +------------------+-------------+---------------------------------------------+
- *   | *NB_IN_STREAMS*  | 2           | Number of input HWPE-Stream streams.        |
- *   +------------------+-------------+---------------------------------------------+
- *   | *DATA_WIDTH_IN*  | 32          | Width of the input HWPE-Stream streams.     |
- *   +------------------+-------------+---------------------------------------------+
+ *   +------------------+------------------+-----------------------------------------------+
+ *   | **Name**         | **Default**      | **Description**                               |
+ *   +------------------+------------------+-----------------------------------------------+
+ *   | *NB_IN_STREAMS*  | 2                | Number of input HWPE-Stream streams.          |
+ *   +------------------+------------------+-----------------------------------------------+
+ *   | *DATA_WIDTH_IN*  | 32               | Width of the input HWPE-Stream streams.       |
+ *   +------------------+------------------+-----------------------------------------------+
+ *   | *STRB_WIDTH_IN*  |DATA_WIDTH_IN / 8 | Width of the input HWPE-Stream strobe signal. |
+ *   +------------------+------------------+-----------------------------------------------+
  */
 
 import hwpe_stream_package::*;
 
 module hwpe_stream_merge #(
   parameter int unsigned NB_IN_STREAMS = 2,
-  parameter int unsigned DATA_WIDTH_IN = 32
+  parameter int unsigned DATA_WIDTH_IN = 32,
+  parameter int unsigned STRB_WIDTH_IN = DATA_WIDTH_IN/8
 )
 (
   input  logic                   clk_i,
@@ -59,8 +62,6 @@ module hwpe_stream_merge #(
   hwpe_stream_intf_stream.source pop_o
 );
 
-  parameter STRB_WIDTH_IN = DATA_WIDTH_IN / 8;
-
   logic [NB_IN_STREAMS-1:0] stream_valid;
 
   generate
diff --git a/rtl/basic/hwpe_stream_serialize.sv b/rtl/basic/hwpe_stream_serialize.sv
index ed8c388..7289db2 100644
--- a/rtl/basic/hwpe_stream_serialize.sv
+++ b/rtl/basic/hwpe_stream_serialize.sv
@@ -22,24 +22,26 @@
  * .. _hwpe_stream_serialize_params:
  * .. table:: **hwpe_stream_serialize** design-time parameters.
  *
- *   +------------------+-------------+-------------------------------------------------------+
- *   | **Name**         | **Default** | **Description**                                       |
- *   +------------------+-------------+-------------------------------------------------------+
- *   | *NB_IN_STREAMS*  | 2           | Number of input HWPE-Stream streams.                  |
- *   +------------------+-------------+-------------------------------------------------------+
- *   | *DATA_WIDTH*     | 32          | Width of the HWPE-Stream streams.                     |
- *   +------------------+-------------+-------------------------------------------------------+
- *   | *CONTIG_LIMIT*   | 1024        | Maximum number of contiguous packets per stream.      |
- *   +------------------+-------------+-------------------------------------------------------+
- *   | *SYNC_READY*     | 0           | If 0, each incoming stream is handshaken separately,  |
- *   |                  |             | which means that their producers must be independent. |
- *   |                  |             | If 1, the ready signal is "fenced", which means that  |
- *   |                  |             | all streams wait for the last stream to be ready to   |
- *   |                  |             | progress. This is useful, for example, when there is  |
- *   |                  |             | a single producer (e.g., `hwpe_stream_split`). Care   |
- *   |                  |             | must be taken to deadlocks, typically by inserting a  |
- *   |                  |             | decoupling FIFO.                                      |
- *   +------------------+-------------+-------------------------------------------------------+
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | **Name**         | **Default**    | **Description**                                       |
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | *NB_IN_STREAMS*  | 2              | Number of input HWPE-Stream streams.                  |
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | *DATA_WIDTH*     | 32             | Width of the HWPE-Stream streams.                     |
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | *STRB_WIDTH*     | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal.               |
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | *CONTIG_LIMIT*   | 1024           | Maximum number of contiguous packets per stream.      |
+ *   +------------------+----------------+-------------------------------------------------------+
+ *   | *SYNC_READY*     | 0              | If 0, each incoming stream is handshaken separately,  |
+ *   |                  |                | which means that their producers must be independent. |
+ *   |                  |                | If 1, the ready signal is "fenced", which means that  |
+ *   |                  |                | all streams wait for the last stream to be ready to   |
+ *   |                  |                | progress. This is useful, for example, when there is  |
+ *   |                  |                | a single producer (e.g., `hwpe_stream_split`). Care   |
+ *   |                  |                | must be taken to deadlocks, typically by inserting a  |
+ *   |                  |                | decoupling FIFO.                                      |
+ *   +------------------+----------------+-------------------------------------------------------+
  *
   * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_serialize_ctrl:
@@ -61,6 +63,7 @@ module hwpe_stream_serialize #(
   parameter int unsigned NB_IN_STREAMS = 2,
   parameter int unsigned CONTIG_LIMIT = 1024,
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter logic        SYNC_READY = 1'b0
 )
 (
@@ -80,7 +83,7 @@ module hwpe_stream_serialize #(
   // boilerplate for SystemVerilog compliance
   logic [NB_IN_STREAMS-1:0][DATA_WIDTH-1:0]   push_data;
   logic [NB_IN_STREAMS-1:0]                   push_valid;
-  logic [NB_IN_STREAMS-1:0][DATA_WIDTH/8-1:0] push_strb;
+  logic [NB_IN_STREAMS-1:0][STRB_WIDTH-1:0] push_strb;
   logic [NB_IN_STREAMS-1:0]                   push_ready;
 
   generate
diff --git a/rtl/basic/hwpe_stream_split.sv b/rtl/basic/hwpe_stream_split.sv
index 64f994d..6593e1b 100644
--- a/rtl/basic/hwpe_stream_split.sv
+++ b/rtl/basic/hwpe_stream_split.sv
@@ -35,20 +35,23 @@
  * .. _hwpe_stream_split_params:
  * .. table:: **hwpe_stream_split** design-time parameters.
  *
- *   +------------------+-------------+---------------------------------------------+
- *   | **Name**         | **Default** | **Description**                             |
- *   +------------------+-------------+---------------------------------------------+
- *   | *NB_OUT_STREAMS* | 2           | Number of output HWPE-Stream streams.       |
- *   +------------------+-------------+---------------------------------------------+
- *   | *DATA_WIDTH_IN*  | 128         | Width of the input HWPE-Stream stream.      |
- *   +------------------+-------------+---------------------------------------------+
+ *   +------------------+-------------------+------------------------------------------------+
+ *   | **Name**         | **Default**       | **Description**                                |
+ *   +------------------+-------------------+------------------------------------------------+
+ *   | *NB_OUT_STREAMS* | 2                 | Number of output HWPE-Stream streams.          |
+ *   +------------------+-------------------+------------------------------------------------+
+ *   | *DATA_WIDTH_IN*  | 128               | Width of the input HWPE-Stream stream.         |
+ *   +------------------+-------------------+------------------------------------------------+
+ *   | *STRB_WIDTH_IN*  | DATA_WIDTH_IN / 8 | Width of the input HWPE-Stream strobe signal.  |
+ *   +------------------+-------------------+------------------------------------------------+
  */
 
 import hwpe_stream_package::*;
 
 module hwpe_stream_split #(
   parameter int unsigned NB_OUT_STREAMS = 2,
-  parameter int unsigned DATA_WIDTH_IN = 128
+  parameter int unsigned DATA_WIDTH_IN  = 128,
+  parameter int unsigned STRB_WIDTH_IN  = DATA_WIDTH_IN/8
 )
 (
   input  logic                   clk_i,
@@ -60,7 +63,7 @@ module hwpe_stream_split #(
 );
 
   parameter int unsigned DATA_WIDTH_OUT = DATA_WIDTH_IN/NB_OUT_STREAMS;
-  parameter int unsigned STRB_WIDTH_OUT = DATA_WIDTH_OUT/8;
+  parameter int unsigned STRB_WIDTH_OUT = STRB_WIDTH_IN/NB_OUT_STREAMS;
 
   logic [NB_OUT_STREAMS-1:0] stream_ready;
 
diff --git a/rtl/fifo/hwpe_stream_fifo.sv b/rtl/fifo/hwpe_stream_fifo.sv
index da79d14..46e2781 100644
--- a/rtl/fifo/hwpe_stream_fifo.sv
+++ b/rtl/fifo/hwpe_stream_fifo.sv
@@ -33,17 +33,19 @@
  * .. _hwpe_stream_fifo_params:
  * .. table:: **hwpe_stream_fifo** design-time parameters.
  *
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | **Name**               | **Default**  | **Description**                                                                      |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*           | 32           | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *FIFO_DEPTH*           | 8            | Depth of the FIFO queue (multiple of 2).                                             |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO*           | 0            | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO_TEST_WRAP* | 0            | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers.                         |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | **Name**               | **Default**    | **Description**                                                                      |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*           | 32             | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*           | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal.                                              |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *FIFO_DEPTH*           | 8              | Depth of the FIFO queue (multiple of 2).                                             |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO*           | 0              | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO_TEST_WRAP* | 0              | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers.                         |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_fifo_flags:
@@ -67,6 +69,7 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_fifo #(
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned FIFO_DEPTH = 8,
   parameter int unsigned LATCH_FIFO = 0,
   parameter int unsigned LATCH_FIFO_TEST_WRAP = 0
@@ -90,7 +93,7 @@ module hwpe_stream_fifo #(
 
   logic [ADDR_DEPTH-1:0] pop_pointer_q,  pop_pointer_d;
   logic [ADDR_DEPTH-1:0] push_pointer_q, push_pointer_d;
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] fifo_registers[FIFO_DEPTH-1:0];
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
   integer       i;
 
   assign flags_o.empty = (cs == EMPTY) ? 1'b1 : 1'b0;
@@ -229,8 +232,8 @@ module hwpe_stream_fifo #(
     endcase
   end
 
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_out_int;
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_in_int;
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] data_out_int;
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] data_in_int;
 
   generate
     if(LATCH_FIFO == 0) begin : fifo_ff_gen
@@ -260,7 +263,7 @@ module hwpe_stream_fifo #(
 
       hwpe_stream_fifo_scm #(
         .ADDR_WIDTH ( ADDR_DEPTH                ),
-        .DATA_WIDTH ( DATA_WIDTH + DATA_WIDTH/8 )
+        .DATA_WIDTH ( DATA_WIDTH + STRB_WIDTH   )
       ) i_fifo_latch (
         .clk         ( clk_i                       ),
         .rst_n       ( rst_ni                      ),
@@ -279,7 +282,7 @@ module hwpe_stream_fifo #(
 
       hwpe_stream_fifo_scm_test_wrap #(
         .ADDR_WIDTH ( ADDR_DEPTH                ),
-        .DATA_WIDTH ( DATA_WIDTH + DATA_WIDTH/8 )
+        .DATA_WIDTH ( DATA_WIDTH + STRB_WIDTH   )
       ) i_fifo_latch (
         .clk ( clk_i ),
         .rst_n       ( rst_ni                      ),
@@ -300,7 +303,7 @@ module hwpe_stream_fifo #(
     end
   endgenerate
 
-  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8-1:DATA_WIDTH/8] : '0;
-  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH/8-1:0] : '0;
+  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH-1:STRB_WIDTH] : '0;
+  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[STRB_WIDTH-1:0] : '0;
 
 endmodule // hwpe_stream_fifo
diff --git a/rtl/fifo/hwpe_stream_fifo_earlystall.sv b/rtl/fifo/hwpe_stream_fifo_earlystall.sv
index ceadac4..57514f1 100644
--- a/rtl/fifo/hwpe_stream_fifo_earlystall.sv
+++ b/rtl/fifo/hwpe_stream_fifo_earlystall.sv
@@ -30,15 +30,17 @@
  * .. _hwpe_stream_fifo_earlystall_params:
  * .. table:: **hwpe_stream_fifo_earlystall** design-time parameters.
  *
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | **Name**               | **Default**  | **Description**                                                                      |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*           | 32           | Width of the HWPE-Streams (multiple of 32).                                          |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *FIFO_DEPTH*           | 8            | Depth of the FIFO queue (multiple of 2).                                             |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO*           | 0            | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
+ *   | **Name**               | **Default**     | **Description**                                                                      |
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*           | 32              | Width of the HWPE-Streams (multiple of 32).                                          |
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*           | DATA_WIDTH / 8  | Width of the HWPE-Stream strobe signal.                                              |
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
+ *   | *FIFO_DEPTH*           | 8               | Depth of the FIFO queue (multiple of 2).                                             |
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO*           | 0               | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
+ *   +------------------------+-----------------+--------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_fifo_earlystall_flags:
@@ -62,6 +64,7 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_fifo_earlystall #(
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned FIFO_DEPTH = 8,
   parameter int unsigned LATCH_FIFO = 0
 )
@@ -84,7 +87,7 @@ module hwpe_stream_fifo_earlystall #(
   // internal signals
   logic [ADDR_DEPTH-1:0] pop_pointer_q,  pop_pointer_d;
   logic [ADDR_DEPTH-1:0] push_pointer_q, push_pointer_d;
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] fifo_registers[FIFO_DEPTH-1:0];
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
   integer       i;
 
   assign flags_o.empty = (cs == EMPTY) ? 1'b1 : 1'b0;
@@ -213,9 +216,9 @@ module hwpe_stream_fifo_earlystall #(
     endcase
   end
 
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_out_int;
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_out_reg;
-  logic [DATA_WIDTH+DATA_WIDTH/8-1:0] data_in_int;
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] data_out_int;
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] data_out_reg;
+  logic [DATA_WIDTH+STRB_WIDTH-1:0] data_in_int;
 
   generate
     if(LATCH_FIFO == 0) begin : fifo_ff_gen
@@ -224,11 +227,11 @@ module hwpe_stream_fifo_earlystall #(
       begin
         if(rst_ni == 1'b0) begin
           for (i=0; i< FIFO_DEPTH; i++)
-            fifo_registers[i] <= {(DATA_WIDTH+DATA_WIDTH/8) {1'b0}};
+            fifo_registers[i] <= {(DATA_WIDTH+STRB_WIDTH) {1'b0}};
         end
         else if(clear_i == 1'b1) begin
           for (i=0; i< FIFO_DEPTH; i++)
-            fifo_registers[i] <= {(DATA_WIDTH+DATA_WIDTH/8) {1'b0}};
+            fifo_registers[i] <= {(DATA_WIDTH+STRB_WIDTH) {1'b0}};
         end
         else begin
           if(push_i.valid == 1'b1)
@@ -245,7 +248,7 @@ module hwpe_stream_fifo_earlystall #(
 
       hwpe_stream_fifo_scm #(
         .ADDR_WIDTH(ADDR_DEPTH             ),
-        .DATA_WIDTH(DATA_WIDTH+DATA_WIDTH/8)
+        .DATA_WIDTH(DATA_WIDTH+STRB_WIDTH)
       ) i_fifo_latch (
         .clk ( clk_i ),
         .rst_n       ( rst_ni         ),
@@ -260,7 +263,7 @@ module hwpe_stream_fifo_earlystall #(
     end
   endgenerate
 
-  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8-1:DATA_WIDTH/8] : '0;
-  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH/8-1:0] : '0;
+  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH-1:STRB_WIDTH] : '0;
+  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[STRB_WIDTH-1:0] : '0;
 
 endmodule // hwpe_stream_fifo_earlystall
diff --git a/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv b/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv
index c4ae673..6bd496d 100644
--- a/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv
+++ b/rtl/fifo/hwpe_stream_fifo_earlystall_sidech.sv
@@ -18,6 +18,7 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_fifo_earlystall_sidech #(
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned FIFO_DEPTH = 8,
   parameter int unsigned LATCH_FIFO = 0,
   parameter int unsigned SIDECH_WIDTH = 1
@@ -44,7 +45,7 @@ module hwpe_stream_fifo_earlystall_sidech #(
   // internal signals
   logic [ADDR_DEPTH-1:0] pop_pointer_q,  pop_pointer_d;
   logic [ADDR_DEPTH-1:0] push_pointer_q, push_pointer_d;
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
   integer       i;
 
   assign flags_o.empty = (cs == EMPTY) ? 1'b1 : 1'b0;
@@ -173,8 +174,8 @@ module hwpe_stream_fifo_earlystall_sidech #(
     endcase
   end
 
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] data_out_int;
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] data_in_int;
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] data_out_int;
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] data_in_int;
 
   generate
     if(LATCH_FIFO == 0) begin : fifo_ff_gen
@@ -183,11 +184,11 @@ module hwpe_stream_fifo_earlystall_sidech #(
       begin
         if(rst_ni == 1'b0) begin
           for (i=0; i< FIFO_DEPTH; i++)
-            fifo_registers[i] <= {(DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH) {1'b0}};
+            fifo_registers[i] <= {(DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH) {1'b0}};
         end
         else if(clear_i == 1'b1) begin
           for (i=0; i< FIFO_DEPTH; i++)
-            fifo_registers[i] <= {(DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH) {1'b0}};
+            fifo_registers[i] <= {(DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH) {1'b0}};
         end
         else begin
           if(push_i.valid == 1'b1)
@@ -204,7 +205,7 @@ module hwpe_stream_fifo_earlystall_sidech #(
 
       hwpe_stream_fifo_scm #(
         .ADDR_WIDTH( ADDR_DEPTH                           ),
-        .DATA_WIDTH( DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH )
+        .DATA_WIDTH( DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH )
       ) i_fifo_latch (
         .clk ( clk_i ),
         .rst_n       ( rst_ni         ),
@@ -219,8 +220,8 @@ module hwpe_stream_fifo_earlystall_sidech #(
     end
   endgenerate
 
-  assign sidech_o   = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:DATA_WIDTH+DATA_WIDTH/8] : '0;
-  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8-1:DATA_WIDTH/8] : '0;
-  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH/8-1:0] : '0;
+  assign sidech_o   = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:DATA_WIDTH+STRB_WIDTH] : '0;
+  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH-1:STRB_WIDTH] : '0;
+  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[STRB_WIDTH-1:0] : '0;
 
 endmodule // hwpe_stream_fifo_earlystall_sidech
diff --git a/rtl/fifo/hwpe_stream_fifo_passthrough.sv b/rtl/fifo/hwpe_stream_fifo_passthrough.sv
index 53c58e1..26c71a2 100644
--- a/rtl/fifo/hwpe_stream_fifo_passthrough.sv
+++ b/rtl/fifo/hwpe_stream_fifo_passthrough.sv
@@ -32,17 +32,19 @@
  * .. _hwpe_stream_fifo_params:
  * .. table:: **hwpe_stream_fifo** design-time parameters.
  *
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | **Name**               | **Default**  | **Description**                                                                      |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*           | 32           | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *FIFO_DEPTH*           | 8            | Depth of the FIFO queue (multiple of 2).                                             |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO*           | 0            | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO_TEST_WRAP* | 0            | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers.                         |
- *   +------------------------+--------------+--------------------------------------------------------------------------------------+
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | **Name**               | **Default**    | **Description**                                                                      |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*           | 32             | Width of the HWPE-Streams (typically multiple of 32, but this module does not care). |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*           | DATA_WIDTH / 8 | Width of the HWPE-Stream strobe signal.                                              |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *FIFO_DEPTH*           | 8              | Depth of the FIFO queue (multiple of 2).                                             |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO*           | 0              | If 1, use latches instead of flip-flops (requires special constraints in synthesis). |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO_TEST_WRAP* | 0              | If 1 and *LATCH_FIFO* is 1, wrap latches with BIST wrappers.                         |
+ *   +------------------------+----------------+--------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_fifo_flags:
@@ -66,6 +68,7 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_fifo_passthrough #(
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned FIFO_DEPTH = 8,
   parameter int unsigned LATCH_FIFO = 0,
   parameter int unsigned LATCH_FIFO_TEST_WRAP = 0
@@ -118,6 +121,7 @@ module hwpe_stream_fifo_passthrough #(
 
   hwpe_stream_fifo #(
     .DATA_WIDTH           ( DATA_WIDTH           ),
+    .STRB_WIDTH           ( STRB_WIDTH           ),
     .FIFO_DEPTH           ( FIFO_DEPTH           ),
     .LATCH_FIFO           ( LATCH_FIFO           ),
     .LATCH_FIFO_TEST_WRAP ( LATCH_FIFO_TEST_WRAP )
diff --git a/rtl/fifo/hwpe_stream_fifo_sidech.sv b/rtl/fifo/hwpe_stream_fifo_sidech.sv
index d9510c7..aec6e9e 100644
--- a/rtl/fifo/hwpe_stream_fifo_sidech.sv
+++ b/rtl/fifo/hwpe_stream_fifo_sidech.sv
@@ -18,6 +18,7 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_fifo_sidech #(
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned FIFO_DEPTH = 8,
   parameter int unsigned LATCH_FIFO = 0,
   parameter int unsigned SIDECH_WIDTH = 1
@@ -44,7 +45,7 @@ module hwpe_stream_fifo_sidech #(
 
   logic [ADDR_DEPTH-1:0] pop_pointer_q,  pop_pointer_d;
   logic [ADDR_DEPTH-1:0] push_pointer_q, push_pointer_d;
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] fifo_registers[FIFO_DEPTH-1:0];
   integer       i;
 
   assign flags_o.empty = (cs == EMPTY) ? 1'b1 : 1'b0;
@@ -163,8 +164,8 @@ module hwpe_stream_fifo_sidech #(
     endcase
   end
 
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] data_out_int;
-  logic [DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:0] data_in_int;
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] data_out_int;
+  logic [DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:0] data_in_int;
 
   generate
     if(LATCH_FIFO == 0) begin : fifo_ff_gen
@@ -193,8 +194,8 @@ module hwpe_stream_fifo_sidech #(
       assign data_in_int = { sidech_i, push_i.data, push_i.strb };
 
       hwpe_stream_fifo_scm #(
-        .ADDR_WIDTH( ADDR_DEPTH                              ),
-        .DATA_WIDTH( DATA_WIDTH + DATA_WIDTH/8 +SIDECH_WIDTH )
+        .ADDR_WIDTH( ADDR_DEPTH                            ),
+        .DATA_WIDTH( DATA_WIDTH + STRB_WIDTH +SIDECH_WIDTH )
       ) i_fifo_latch (
         .clk ( clk_i ),
         .rst_n       ( rst_ni                      ),
@@ -209,8 +210,8 @@ module hwpe_stream_fifo_sidech #(
     end
   endgenerate
 
-  assign sidech_o   = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8+SIDECH_WIDTH-1:DATA_WIDTH+DATA_WIDTH/8] : '0;
-  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+DATA_WIDTH/8-1:DATA_WIDTH/8] : '0;
-  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH/8-1:0] : '0;
+  assign sidech_o   = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH+SIDECH_WIDTH-1:DATA_WIDTH+STRB_WIDTH] : '0;
+  assign pop_o.data = (pop_o.valid == 1'b1) ? data_out_int[DATA_WIDTH+STRB_WIDTH-1:STRB_WIDTH] : '0;
+  assign pop_o.strb = (pop_o.valid == 1'b1) ? data_out_int[STRB_WIDTH-1:0] : '0;
 
 endmodule // hwpe_stream_fifo_sidech
diff --git a/rtl/streamer/hwpe_stream_sink.sv b/rtl/streamer/hwpe_stream_sink.sv
index 847eef3..5ed2eaa 100644
--- a/rtl/streamer/hwpe_stream_sink.sv
+++ b/rtl/streamer/hwpe_stream_sink.sv
@@ -42,19 +42,21 @@
  * .. _hwpe_stream_sink_params:
  * .. table:: **hwpe_stream_sink** design-time parameters.
  *
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | **Name**          | **Default** | **Description**                                                                                                        |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *TCDM_FIFO_DEPTH* | 2           | If >0, the module produces a HWPE-MemDecoupled interface and includes a TCDM FIFO of this depth.                       |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*      | 32          | Width of input/output streams.                                                                                         |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO*      | 0           | If 1, use latches instead of flip-flops (requires special constraints in synthesis).                                   |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *TRANS_CNT*       | 16          | Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ `TRANS_CNT`.   |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *REALIGNABLE*     | 1           | If set to 0, the sink will not support non-word-aligned HWPE-Mem accesses.                                             |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | **Name**          | **Default**    | **Description**                                                                                                        |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *TCDM_FIFO_DEPTH* | 2              | If >0, the module produces a HWPE-MemDecoupled interface and includes a TCDM FIFO of this depth.                       |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*      | 32             | Width of input/output streams.                                                                                         |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*      | DATA_WIDTH / 8 | Width of input/output stream strobe signal.                                                                            |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO*      | 0              | If 1, use latches instead of flip-flops (requires special constraints in synthesis).                                   |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *TRANS_CNT*       | 16             | Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ `TRANS_CNT`.   |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *REALIGNABLE*     | 1              | If set to 0, the sink will not support non-word-aligned HWPE-Mem accesses.                                             |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_sink_ctrl:
@@ -92,6 +94,7 @@ module hwpe_stream_sink
 #(
   // Stream interface params
   parameter int unsigned DATA_WIDTH      = 32,
+  parameter int unsigned STRB_WIDTH      = DATA_WIDTH/8,
   parameter int unsigned NB_TCDM_PORTS   = DATA_WIDTH/32,
   parameter int unsigned REALIGNABLE     = 1,
   parameter int unsigned LATCH_FIFO      = 0,
@@ -132,7 +135,8 @@ module hwpe_stream_sink
   );
 
   hwpe_stream_intf_stream #(
-    .DATA_WIDTH ( DATA_WIDTH )
+    .DATA_WIDTH ( DATA_WIDTH ),
+    .STRB_WIDTH ( STRB_WIDTH )
   ) realigned_stream (
     .clk ( clk_realign_gated )
   );
@@ -142,6 +146,7 @@ module hwpe_stream_sink
 
   hwpe_stream_split #(
     .DATA_WIDTH_IN ( DATA_WIDTH    ),
+    .STRB_WIDTH_IN ( STRB_WIDTH    ),
     .NB_OUT_STREAMS( NB_TCDM_PORTS )
   ) i_stream_split (
     .clk_i   ( clk_i            ),
@@ -179,7 +184,8 @@ module hwpe_stream_sink
   generate
     if (REALIGNABLE) begin : realign_gen
       hwpe_stream_sink_realign #(
-        .DATA_WIDTH ( DATA_WIDTH )
+        .DATA_WIDTH ( DATA_WIDTH ),
+        .STRB_WIDTH ( STRB_WIDTH )
       ) i_realign (
         .clk_i       ( clk_realign_gated                      ),
         .rst_ni      ( rst_ni                                 ),
diff --git a/rtl/streamer/hwpe_stream_sink_realign.sv b/rtl/streamer/hwpe_stream_sink_realign.sv
index e696b93..ffe4024 100644
--- a/rtl/streamer/hwpe_stream_sink_realign.sv
+++ b/rtl/streamer/hwpe_stream_sink_realign.sv
@@ -23,11 +23,13 @@
  * .. _hwpe_stream_sink_realign_params:
  * .. table:: **hwpe_stream_sink_realign** design-time parameters.
  *
- *   +-------------------+-------------+--------------------------------------------------------------------------------------------------------------------------+
- *   | **Name**          | **Default** | **Description**                                                                                                          |
- *   +-------------------+-------------+--------------------------------------------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*      | 32          | Width of input/output streams.                                                                                           |
- *   +-------------------+-------------+--------------------------------------------------------------------------------------------------------------------------+
+ *   +-------------------+----------------+--------------------------------------------------------------------------------------------------------------------------+
+ *   | **Name**          | **Default**    | **Description**                                                                                                          |
+ *   +-------------------+----------------+--------------------------------------------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*      | 32             | Width of input/output streams.                                                                                           |
+ *   +-------------------+----------------+--------------------------------------------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*      | DATA_WIDTH / 8 | Width of input/output stream strobe signals.                                                                             |
+ *   +-------------------+----------------+--------------------------------------------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_sink_realign_ctrl:
@@ -56,7 +58,8 @@
 import hwpe_stream_package::*;
 
 module hwpe_stream_sink_realign #(
-  parameter int unsigned DATA_WIDTH = 32
+  parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8
 )
 (
   input  logic                    clk_i,
@@ -66,27 +69,27 @@ module hwpe_stream_sink_realign #(
 
   input  ctrl_realign_t           ctrl_i,
 
-  input  logic [DATA_WIDTH/8-1:0] strb_i,
+  input  logic [STRB_WIDTH-1:0] strb_i,
   hwpe_stream_intf_stream.sink    push_i,
   hwpe_stream_intf_stream.source  pop_o
 );
 
-  logic [DATA_WIDTH/8-1:0] strb_q;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_inv_d;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_inv_q;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_d;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_q;
-  logic unsigned [$clog2(DATA_WIDTH/8)+3:0] strb_rotate_d_shifted;
-  logic unsigned [$clog2(DATA_WIDTH/8)+3:0] strb_rotate_q_shifted;
-  logic unsigned [$clog2(DATA_WIDTH/8)+3:0] strb_rotate_inv_shifted;
+  logic [STRB_WIDTH-1:0] strb_q;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_inv_d;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_inv_q;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_d;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_q;
+  logic unsigned [$clog2(STRB_WIDTH)+3:0] strb_rotate_d_shifted;
+  logic unsigned [$clog2(STRB_WIDTH)+3:0] strb_rotate_q_shifted;
+  logic unsigned [$clog2(STRB_WIDTH)+3:0] strb_rotate_inv_shifted;
   logic [DATA_WIDTH-1:0]   stream_data_q;
-  logic [DATA_WIDTH/8-1:0] stream_strb_q;
-  logic [DATA_WIDTH/8-1:0] stream_strb_latest_q;
+  logic [STRB_WIDTH-1:0] stream_strb_q;
+  logic [STRB_WIDTH-1:0] stream_strb_latest_q;
 
   logic [DATA_WIDTH-1:0] int_data;
   logic [DATA_WIDTH-1:0] int_data_q;
-  logic [DATA_WIDTH/8-1:0] int_strb;
-  logic [DATA_WIDTH/8-1:0] int_strb_q;
+  logic [STRB_WIDTH-1:0] int_strb;
+  logic [STRB_WIDTH-1:0] int_strb_q;
   logic int_valid;
   logic int_valid_q;
   logic int_ready;
@@ -121,15 +124,15 @@ module hwpe_stream_sink_realign #(
   begin
     strb_rotate_inv_d = '0;
     if(ctrl_i.first) begin
-      for (int i=0; i<DATA_WIDTH/8; i++)
-        strb_rotate_inv_d += ($clog2(DATA_WIDTH/8))'(strb_i[i]);
+      for (int i=0; i<STRB_WIDTH; i++)
+        strb_rotate_inv_d += ($clog2(STRB_WIDTH))'(strb_i[i]);
     end
     else begin
-      for (int i=0; i<DATA_WIDTH/8; i++)
-        strb_rotate_inv_d += ($clog2(DATA_WIDTH/8))'(strb_q[i]);
+      for (int i=0; i<STRB_WIDTH; i++)
+        strb_rotate_inv_d += ($clog2(STRB_WIDTH))'(strb_q[i]);
     end
   end
-  assign strb_rotate_d = {($clog2(DATA_WIDTH/8)){1'b1}} - strb_rotate_inv_d + 1;
+  assign strb_rotate_d = {($clog2(STRB_WIDTH)){1'b1}} - strb_rotate_inv_d + 1;
   assign strb_rotate_d_shifted   = strb_rotate_d << 3;
   assign strb_rotate_q_shifted   = strb_rotate_q << 3;
   assign strb_rotate_inv_shifted = strb_rotate_inv_q << 3;
diff --git a/rtl/streamer/hwpe_stream_source.sv b/rtl/streamer/hwpe_stream_source.sv
index b3629af..f3a9f69 100644
--- a/rtl/streamer/hwpe_stream_source.sv
+++ b/rtl/streamer/hwpe_stream_source.sv
@@ -46,19 +46,21 @@
  * .. _hwpe_stream_source_params:
  * .. table:: **hwpe_stream_source** design-time parameters.
  *
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | **Name**          | **Default** | **Description**                                                                                                        |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *DECOUPLED*       | 0           | If 1, the module expects a HWPE-MemDecoupled interface instead of HWPE-Mem.                                            |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*      | 32          | Width of input/output streams (multiple of 32).                                                                        |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *LATCH_FIFO*      | 0           | If 1, use latches instead of flip-flops (requires special constraints in synthesis).                                   |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *TRANS_CNT*       | 16          | Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ `TRANS_CNT`.   |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *REALIGNABLE*     | 1           | If set to 0, the source will not support non-word-aligned HWPE-Mem accesses.                                           |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | **Name**          | **Default**    | **Description**                                                                                                        |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *DECOUPLED*       | 0              | If 1, the module expects a HWPE-MemDecoupled interface instead of HWPE-Mem.                                            |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*      | 32             | Width of input/output streams (multiple of 32).                                                                        |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*      | DATA_WIDTH / 8 | Width of input/output stream strobe signal.                                                                            |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *LATCH_FIFO*      | 0              | If 1, use latches instead of flip-flops (requires special constraints in synthesis).                                   |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *TRANS_CNT*       | 16             | Number of bits supported in the transaction counter of the address generator, which will overflow at 2^ `TRANS_CNT`.   |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *REALIGNABLE*     | 1              | If set to 0, the source will not support non-word-aligned HWPE-Mem accesses.                                           |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_source_ctrl:
@@ -96,6 +98,7 @@ module hwpe_stream_source
 #(
   // Stream interface params
   parameter int unsigned DATA_WIDTH    = 32,
+  parameter int unsigned STRB_WIDTH    = DATA_WIDTH/8,
   parameter int unsigned NB_TCDM_PORTS = DATA_WIDTH/32,
   parameter int unsigned DECOUPLED     = 0,
   parameter int unsigned LATCH_FIFO    = 0,
@@ -149,13 +152,15 @@ module hwpe_stream_source
   );
 
   hwpe_stream_intf_stream #(
-    .DATA_WIDTH ( DATA_WIDTH )
+    .DATA_WIDTH ( DATA_WIDTH ),
+    .STRB_WIDTH ( STRB_WIDTH )
   ) misaligned_stream (
     .clk ( clk_i )
   );
 
   hwpe_stream_intf_stream #(
-    .DATA_WIDTH ( DATA_WIDTH )
+    .DATA_WIDTH ( DATA_WIDTH ),
+    .STRB_WIDTH ( STRB_WIDTH )
   ) misaligned_fifo_stream (
     .clk ( clk_i )
   );
@@ -194,7 +199,8 @@ module hwpe_stream_source
     if (REALIGNABLE) begin : realign_gen
       hwpe_stream_source_realign #(
         .DECOUPLED  ( DECOUPLED  ),
-        .DATA_WIDTH ( DATA_WIDTH )
+        .DATA_WIDTH ( DATA_WIDTH ),
+        .STRB_WIDTH ( STRB_WIDTH )
       ) i_realign (
         .clk_i      ( clk_i                                  ),
         .rst_ni     ( rst_ni                                 ),
@@ -222,6 +228,7 @@ module hwpe_stream_source
 
       hwpe_stream_fifo #(
         .DATA_WIDTH ( DATA_WIDTH ),
+        .STRB_WIDTH ( STRB_WIDTH ),
         .FIFO_DEPTH ( 2          ),
         .LATCH_FIFO ( LATCH_FIFO )
       ) i_misaligned_fifo (
diff --git a/rtl/streamer/hwpe_stream_source_realign.sv b/rtl/streamer/hwpe_stream_source_realign.sv
index f90b23d..ee29571 100644
--- a/rtl/streamer/hwpe_stream_source_realign.sv
+++ b/rtl/streamer/hwpe_stream_source_realign.sv
@@ -23,15 +23,17 @@
  * .. _hwpe_stream_source_realign_params:
  * .. table:: **hwpe_stream_source_realign** design-time parameters.
  *
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | **Name**          | **Default** | **Description**                                                                                                        |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *DECOUPLED*       | 0           | If 1, the module expects a HWPE-MemDecoupled interface instead of HWPE-Mem.                                            |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *DATA_WIDTH*      | 32          | Width of input/output streams.                                                                                         |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
- *   | *STRB_FIFO_DEPTH* | 4           | Depth of the FIFO queue used for strobes; when full, the realigner will lower its ready signal at the input interface. |
- *   +-------------------+-------------+------------------------------------------------------------------------------------------------------------------------+
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | **Name**          | **Default**    | **Description**                                                                                                        |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *DECOUPLED*       | 0              | If 1, the module expects a HWPE-MemDecoupled interface instead of HWPE-Mem.                                            |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *DATA_WIDTH*      | 32             | Width of input/output streams.                                                                                         |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *STRB_WIDTH*      | DATA_WIDTH / 8 | Width of input/output stream strobe signal.                                                                            |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
+ *   | *STRB_FIFO_DEPTH* | 4              | Depth of the FIFO queue used for strobes; when full, the realigner will lower its ready signal at the input interface. |
+ *   +-------------------+----------------+------------------------------------------------------------------------------------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_source_realign_ctrl:
@@ -73,6 +75,7 @@ module hwpe_stream_source_realign #(
   parameter int unsigned DECOUPLED  = 0, // set to 1 if used with a TCDM stream that does not respect the zero-latency assumption,
                                          // e.g. it passes through a TCDM load FIFO.
   parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8,
   parameter int unsigned STRB_FIFO_DEPTH = 4
 )
 (
@@ -84,26 +87,26 @@ module hwpe_stream_source_realign #(
   input  ctrl_realign_t           ctrl_i,
   output flags_realign_t          flags_o,
 
-  input  logic [DATA_WIDTH/8-1:0] strb_i,
+  input  logic [STRB_WIDTH-1:0] strb_i,
   hwpe_stream_intf_stream.sink    push_i,
   hwpe_stream_intf_stream.source  pop_o
 );
 
-  logic [STRB_FIFO_DEPTH-1:0][DATA_WIDTH/8-1:0] strb_last_fifo, strb_first_fifo;
+  logic [STRB_FIFO_DEPTH-1:0][STRB_WIDTH-1:0] strb_last_fifo, strb_first_fifo;
   logic [STRB_FIFO_DEPTH-1:0] last_packet_fifo;
-  logic [DATA_WIDTH/8-1:0] int_strb;
+  logic [STRB_WIDTH-1:0] int_strb;
 
   logic [$clog2(STRB_FIFO_DEPTH):0] strb_first_cnt;
   logic [$clog2(STRB_FIFO_DEPTH):0] strb_last_cnt;
 
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_d;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_inv_d;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_d;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_inv_d;
   logic [DATA_WIDTH-1:0]   stream_data_q;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_q;
-  logic unsigned [$clog2(DATA_WIDTH/8):0] strb_rotate_inv_q;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_q;
+  logic unsigned [$clog2(STRB_WIDTH):0] strb_rotate_inv_q;
 
-  logic unsigned [$clog2(DATA_WIDTH/8)+3:0] strb_rotate_q_shifted;
-  logic unsigned [$clog2(DATA_WIDTH/8)+3:0] strb_rotate_inv_q_shifted;
+  logic unsigned [$clog2(STRB_WIDTH)+3:0] strb_rotate_q_shifted;
+  logic unsigned [$clog2(STRB_WIDTH)+3:0] strb_rotate_inv_q_shifted;
 
   logic clk_gated;
 
@@ -283,10 +286,10 @@ module hwpe_stream_source_realign #(
   always_comb
   begin
     strb_rotate_d = '0;
-    for (int i=0; i<DATA_WIDTH/8; i++)
-      strb_rotate_d += ($clog2(DATA_WIDTH/8))'(int_strb[i]);
+    for (int i=0; i<STRB_WIDTH; i++)
+      strb_rotate_d += ($clog2(STRB_WIDTH))'(int_strb[i]);
   end
-  assign strb_rotate_inv_d = {($clog2(DATA_WIDTH/8)){1'b1}} - strb_rotate_d + 1;
+  assign strb_rotate_inv_d = {($clog2(STRB_WIDTH)){1'b1}} - strb_rotate_d + 1;
 
   always_ff @(posedge clk_gated or negedge rst_ni)
   begin
diff --git a/rtl/streamer/hwpe_stream_strbgen.sv b/rtl/streamer/hwpe_stream_strbgen.sv
index 38b1d28..d97e0ef 100644
--- a/rtl/streamer/hwpe_stream_strbgen.sv
+++ b/rtl/streamer/hwpe_stream_strbgen.sv
@@ -23,11 +23,13 @@
  * .. _hwpe_stream_strbgen_params:
  * .. table:: **hwpe_stream_strbgen** design-time parameters.
  *
- *   +--------------+-------------+--------------------------------+
- *   | **Name**     | **Default** | **Description**                |
- *   +--------------+-------------+--------------------------------+
- *   | *DATA_WIDTH* | 32          | Width of input/output streams. |
- *   +--------------+-------------+--------------------------------+
+ *   +--------------+----------------+---------------------------------------------+
+ *   | **Name**     | **Default**    | **Description**                             |
+ *   +--------------+----------------+---------------------------------------------+
+ *   | *DATA_WIDTH* | 32             | Width of input/output streams.              |
+ *   +--------------+----------------+---------------------------------------------+
+ *   | *STRB_WIDTH* | DATA_WIDTH / 8 | Width of input/output stream strobe signal. |
+ *   +--------------+----------------+---------------------------------------------+
  *
  * .. tabularcolumns:: |l|l|J|
  * .. _hwpe_stream_strbgen_ctrl:
@@ -63,7 +65,8 @@ import hwpe_stream_package::*;
 
 module hwpe_stream_strbgen
 #(
-  parameter int unsigned DATA_WIDTH = 32
+  parameter int unsigned DATA_WIDTH = 32,
+  parameter int unsigned STRB_WIDTH = DATA_WIDTH/8
 )
 (
   // global signals
@@ -90,8 +93,8 @@ module hwpe_stream_strbgen
       cnt <= '0;
     end
     else if(push_i.valid & push_i.ready) begin
-      if(cnt < ctrl_i.line_length-8'h1) begin
-        cnt <= cnt + 8'h1;
+      if(cnt < ctrl_i.line_length-'h1) begin
+        cnt <= cnt + 'h1;
       end
       else begin
         cnt <= '0;
@@ -99,11 +102,11 @@ module hwpe_stream_strbgen
     end
   end
 
-  logic [DATA_WIDTH/8-1:0] decoded_remainder;
+  logic [STRB_WIDTH-1:0] decoded_remainder;
   always_comb
   begin
     decoded_remainder = '0;
-    for(int i=0; i<DATA_WIDTH/8; i++) begin
+    for(int i=0; i<STRB_WIDTH; i++) begin
       if(i<ctrl_i.line_length_remainder)
         decoded_remainder[i] = 1'b1;
     end
@@ -111,7 +114,7 @@ module hwpe_stream_strbgen
 
   assign pop_o.valid = push_i.valid;
   assign pop_o.data  = push_i.data;
-  assign pop_o.strb  = ((cnt == ctrl_i.line_length-8'h1) && (ctrl_i.line_length_remainder != '0)) ? push_i.strb & decoded_remainder : push_i.strb;
+  assign pop_o.strb  = ((cnt == ctrl_i.line_length-'h1) && (ctrl_i.line_length_remainder != '0)) ? push_i.strb & decoded_remainder : push_i.strb;
 
   assign push_i.ready = pop_o.ready;