diff --git a/.gitignore b/.gitignore index a20ac26aa2f51d..7da4218b796c20 100644 --- a/.gitignore +++ b/.gitignore @@ -133,3 +133,4 @@ all.config # Kdevelop4 *.kdev4 +initramfs.cpio diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index eb56c82d8aa14c..4345ce5f723770 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -211,6 +211,12 @@ config RISCV_BASE_PMU feature of perf. It can run on any RISC-V machines so serves as the fallback, but this option can also be disable to reduce kernel size. +config ARIANE_PMU + bool "Ariane's PMU" + default n + help + Enable Ariane's PMU test code + endmenu config FPU diff --git a/arch/riscv/configs/ariane_defconfig b/arch/riscv/configs/ariane_defconfig new file mode 100644 index 00000000000000..718ed72f6a64bc --- /dev/null +++ b/arch/riscv/configs/ariane_defconfig @@ -0,0 +1,188 @@ +CONFIG_DEFAULT_HOSTNAME="ariane-fpga" +# CONFIG_CROSS_MEMORY_ATTACH is not set +CONFIG_NAMESPACES=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="${BR_BINARIES_DIR}/rootfs.cpio" +CONFIG_EMBEDDED=y +CONFIG_SMP=y +CONFIG_CMDLINE="earlyprintk" +CONFIG_MODULES=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_COMPACTION is not set +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_TLS=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_VIRTIO_BLK=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +CONFIG_VXLAN=y +CONFIG_LOWRISC_DIGILENT_100MHZ=y +CONFIG_XILINX_EMACLITE=y +CONFIG_MDIO_BCM_UNIMAC=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS_MUX_GPIO=y +CONFIG_MDIO_BUS_MUX_MMIOREG=y +CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y +CONFIG_MDIO_GPIO=y +CONFIG_REALTEK_PHY=y +# CONFIG_WLAN is not set +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_VT is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_UARTLITE=y +CONFIG_HVC_RISCV_SBI=y +CONFIG_VIRTIO_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C=y +CONFIG_I2C_OCORES=y +CONFIG_SPI=y +CONFIG_SPI_XILINX=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_XILINX=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MMC=y +CONFIG_MMC_SPI=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_VIRTIO_MMIO=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_SIFIVE_PLIC=y +CONFIG_EXT3_FS=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_TMPFS=y +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V4=y +CONFIG_NFS_SWAP=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_CRYPTO_ECHAINIV=y +# CONFIG_CRYPTO_HW is not set +CONFIG_PRINTK_TIME=y + + +CONFIG_ARIANE_PMU=y +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + + +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_COUNTERS=y +CONFIG_VM_EVENT_COUNTERS=y + +CONFIG_FRAME_POINTER=y +CONFIG_KALLSYMS=y +CONFIG_TRACEPOINTS=y +CONFIG_HAVE_KPROBES=y +CONFIG_KPROBES=y +#CONFIG_KPROBE_EVENTS=y +#CONFIG_UPROBES=y +#CONFIG_UPROBE_EVENTS=y +#CONFIG_DEBUG_INFO=y + + +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y +# +# Generic Kernel Debugging Instruments +# +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_FS=y +# CONFIG_UBSAN is not set +#CONFIG_UBSAN_ALIGNMENT=y +# end of Generic Kernel Debugging Instruments + +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y + + +#CONFIG_TRACE_IRQFLAGS_SUPPORT=y +#CONFIG_STACKTRACE_SUPPORT=y +#CONFIG_LATENCYTOP=y +#CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +#CONFIG_TRACE_CLOCK=y +#CONFIG_RING_BUFFER=y +#CONFIG_EVENT_TRACING=y +#CONFIG_CONTEXT_SWITCH_TRACER=y +#CONFIG_TRACING=y +#CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set +#CONFIG_FUNCTION_TRACER=y + +#CONFIG_FUNCTION_GRAPH_TRACER=y +#CONFIG_DYNAMIC_FTRACE=y +#CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +# CONFIG_FUNCTION_PROFILER is not set +#CONFIG_STACK_TRACER=y +#CONFIG_PREEMPTIRQ_EVENTS=y +#CONFIG_IRQSOFF_TRACER=y +#CONFIG_PREEMPT_TRACER=y +#CONFIG_SCHED_TRACER=y +# CONFIG_HWLAT_TRACER is not set +#CONFIG_FTRACE_SYSCALLS=y +# CONFIG_TRACER_SNAPSHOT is not set +#CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +#CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_SAMPLES is not set + diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 2fd3461e50abc9..9487aa9d703d2f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -1,83 +1,1628 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/riscv 5.1.0-rc7 Kernel Configuration +# + +# +# Compiler: riscv64-unknown-elf-gcc (GCC) 7.2.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70200 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BUILD_SALT="" +CONFIG_DEFAULT_HOSTNAME="ariane-fpga" +CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +# CONFIG_AUDIT is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_IRQ_DOMAIN=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_CLOCKEVENTS=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_HZ_PERIODIC=y +# CONFIG_NO_HZ_IDLE is not set +# CONFIG_NO_HZ is not set +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_PSI is not set + +# +# RCU Subsystem +# +CONFIG_TINY_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TINY_SRCU=y +CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_SWAP_ENABLED is not set +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_DEBUG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y CONFIG_CGROUP_SCHED=y -CONFIG_CFS_BANDWIDTH=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_BPF=y -CONFIG_NAMESPACES=y -CONFIG_USER_NS=y -CONFIG_CHECKPOINT_RESTORE=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +# CONFIG_NAMESPACES is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_SCHED_AUTOGROUP is not set +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="initramfs.cpio" +CONFIG_INITRAMFS_FORCE=y +CONFIG_INITRAMFS_ROOT_UID=0 +CONFIG_INITRAMFS_ROOT_GID=0 +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_INITRAMFS_COMPRESSION=".gz" +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_BPF=y CONFIG_EXPERT=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_HAVE_FUTEX_CMPXCHG=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y -CONFIG_SMP=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y +# CONFIG_USERFAULTFD is not set +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +# CONFIG_PERF_EVENTS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +CONFIG_SLUB_MEMCG_SYSFS_ON=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_PROFILING is not set +CONFIG_64BIT=y +CONFIG_RISCV=y +CONFIG_MMU=y +CONFIG_ZONE_DMA32=y +CONFIG_PAGE_OFFSET=0xffffffe000000000 +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=3 + +# +# Platform type +# +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_MAXPHYSMEM_2GB is not set +CONFIG_MAXPHYSMEM_128GB=y +# CONFIG_SMP is not set +CONFIG_TUNE_GENERIC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_A=y +CONFIG_FPU=y + +# +# Kernel features +# +CONFIG_HZ_100=y +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y + +# +# Boot options +# +CONFIG_CMDLINE="swiotlb=noforce" +# CONFIG_CMDLINE_FALLBACK is not set +# CONFIG_CMDLINE_EXTEND is not set +CONFIG_CMDLINE_FORCE=y + +# +# Power management options +# +# CONFIG_PM is not set + +# +# General architecture-dependent options +# +CONFIG_HAVE_64BIT_ALIGNED_ACCESS=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_HAVE_CLK=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_REFCOUNT_FULL is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_PLUGIN_HOSTCC="" +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_ZONED is not set +# CONFIG_BLK_DEV_THROTTLING is not set +# CONFIG_BLK_CMDLINE_PARSER is not set +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_DEBUG_FS is not set +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set + +# +# IO Schedulers +# +# CONFIG_MQ_IOSCHED_DEADLINE is not set +# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_IOSCHED_BFQ is not set +CONFIG_ASN1=y +CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +CONFIG_INLINE_READ_UNLOCK=y +CONFIG_INLINE_READ_UNLOCK_IRQ=y +CONFIG_INLINE_WRITE_UNLOCK=y +CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_BINFMT_MISC is not set +CONFIG_COREDUMP=y + +# +# Memory Management options +# +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +# CONFIG_CMA is not set +# CONFIG_ZPOOL is not set +# CONFIG_ZBUD is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y CONFIG_NET=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# CONFIG_PACKET=y +# CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +# CONFIG_UNIX_DIAG is not set +# CONFIG_TLS is not set +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_NETLINK_DIAG=y -CONFIG_PCI=y -CONFIG_PCIEPORTBUS=y -CONFIG_PCI_HOST_GENERIC=y -CONFIG_PCIE_XILINX=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +# CONFIG_SYN_COOKIES is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +# CONFIG_NETFILTER is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set +# CONFIG_DNS_RESOLVER is not set +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +# CONFIG_NETLINK_DIAG is not set +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +# CONFIG_CGROUP_NET_PRIO is not set +# CONFIG_CGROUP_NET_CLASSID is not set +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_STREAM_PARSER is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_NET_DEVLINK is not set +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_PCI=y +# CONFIG_PCI is not set +# CONFIG_PCCARD is not set + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="" CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +CONFIG_GENERIC_CPU_DEVICES=y + +# +# Bus devices +# +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y +# CONFIG_OF_UNITTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_KOBJ=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_OVERLAY is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set CONFIG_BLK_DEV_LOOP=y -CONFIG_VIRTIO_BLK=y -CONFIG_BLK_DEV_SD=y -CONFIG_BLK_DEV_SR=y -CONFIG_ATA=y -CONFIG_SATA_AHCI=y -CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=y +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set + +# +# NVME Support +# +# CONFIG_NVME_FC is not set + +# +# Misc devices +# +# CONFIG_DUMMY_IRQ is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_SRAM is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set + +# +# Texas Instruments shared transport line discipline +# + +# +# Altera FPGA firmware download module (requires I2C) +# + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# + +# +# SCIF Bus Driver +# + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# CONFIG_ECHO is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set CONFIG_NETDEVICES=y -CONFIG_VIRTIO_NET=y -CONFIG_MACB=y -CONFIG_E1000E=y -CONFIG_R8169=y -CONFIG_MICROSEMI_PHY=y -CONFIG_INPUT_MOUSEDEV=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_VETH is not set +# CONFIG_NLMON is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +CONFIG_ETHERNET=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_ALTERA_TSE is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_AURORA is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_CAVIUM=y +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_DNET is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +CONFIG_NET_VENDOR_LOWRISC=y +CONFIG_LOWRISC_DIGILENT_100MHZ=y +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +CONFIG_MDIO_BITBANG=y +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +# CONFIG_MDIO_HISI_FEMAC is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_OCTEON is not set +CONFIG_PHYLIB=y +CONFIG_SWPHY=y + +# +# MII PHY device drivers +# +# CONFIG_AMD_PHY is not set +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_ASIX_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +CONFIG_FIXED_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set + +# +# Host-side USB support is needed for USB Network Adapter support +# +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +# CONFIG_VT is not set +CONFIG_UNIX98_PTYS=y +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +# CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +# CONFIG_SERIAL_8250_ASPEED_VUART is not set +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_OF_PLATFORM=y + +# +# Non-8250 serial port support +# CONFIG_SERIAL_EARLYCON_RISCV_SBI=y +CONFIG_SERIAL_UARTLITE=y +# CONFIG_SERIAL_UARTLITE_CONSOLE is not set +CONFIG_SERIAL_UARTLITE_NR_UARTS=1 +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_HVC_DRIVER=y CONFIG_HVC_RISCV_SBI=y +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_XILLYBUS is not set + +# +# I2C support +# +# CONFIG_I2C is not set +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +# CONFIG_PPS is not set + +# +# PTP clock support +# # CONFIG_PTP_1588_CLOCK is not set -CONFIG_DRM=y -CONFIG_DRM_RADEON=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PLATFORM=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_UAS=y -CONFIG_VIRTIO_MMIO=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# CONFIG_PINCTRL is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_REGULATOR is not set +# CONFIG_RC_CORE is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_DRM_DP_CEC is not set + +# +# ARM devices +# + +# +# ACP (Audio CoProcessor) Configuration +# + +# +# AMD Library routines +# + +# +# Frame buffer Devices +# +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_SOUND is not set + +# +# HID support +# +# CONFIG_HID is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SUPPORT is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_PWRSEQ_EMMC is not set +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_USDHI6ROL0 is not set +# CONFIG_MMC_CQHCI is not set +CONFIG_MMC_LOWRISC=y +# CONFIG_MMC_MTK is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set + +# +# DMABUF options +# +# CONFIG_SYNC_FILE is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_STAGING is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_CLK_HSDK is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +# CONFIG_ARM_TIMER_SP804 is not set +CONFIG_RISCV_TIMER=y +# CONFIG_MAILBOX is not set +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# CONFIG_IOMMU_DEBUGFS is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_VIRTIO is not set +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# + +# +# Broadcom SoC drivers +# + +# +# NXP/Freescale QorIQ SoC drivers +# + +# +# i.MX SoC drivers +# + +# +# Qualcomm SoC drivers +# +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC_MAX_NR=1 CONFIG_SIFIVE_PLIC=y +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set +# CONFIG_FMC is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set +CONFIG_RAS=y + +# +# Android +# +# CONFIG_ANDROID is not set +# CONFIG_LIBNVDIMM is not set +# CONFIG_DAX is not set +# CONFIG_NVMEM is not set + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# CONFIG_FPGA is not set +# CONFIG_FSI is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set + +# +# File systems +# +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_FS_POSIX_ACL is not set +# CONFIG_EXT3_FS_SECURITY is not set CONFIG_EXT4_FS=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_AUTOFS4_FS=y +# CONFIG_EXT4_FS_POSIX_ACL is not set +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_FUSE_FS is not set +# CONFIG_OVERLAY_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +CONFIG_FAT_DEFAULT_UTF8=y +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set +# CONFIG_PROC_CHILDREN is not set +CONFIG_KERNFS=y +CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_TMPFS_XATTR is not set +CONFIG_MEMFD_CREATE=y +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set CONFIG_NFS_V4_1=y CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y -CONFIG_CRYPTO_USER_API_HASH=y -CONFIG_CRYPTO_DEV_VIRTIO=y +CONFIG_PNFS_FILE_LAYOUT=y +CONFIG_PNFS_FLEXFILE_LAYOUT=y +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +CONFIG_NFS_V4_1_MIGRATION=y +CONFIG_NFS_USE_LEGACY_DNS=y +CONFIG_NFSD=y +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_FLEXFILELAYOUT is not set +# CONFIG_NFSD_FAULT_INJECTION is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_SUNRPC_BACKCHANNEL=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_LSM="yama,loadpin,safesetid,integrity" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +# CONFIG_CRYPTO_SEQIV is not set +# CONFIG_CRYPTO_ECHAINIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CFB is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRCT10DIF is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_DRBG_MENU is not set +# CONFIG_CRYPTO_JITTERENTROPY is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +# CONFIG_CRYPTO_HW is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y + +# +# Certificates for signature checking +# +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_PCI_IOMAP=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +CONFIG_CRC7=y +# CONFIG_LIBCRC32C is not set +# CONFIG_CRC8 is not set +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_DMA_DECLARE_COHERENT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_LIBFDT=y +CONFIG_OID_REGISTRY=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set + +# +# Kernel hacking +# + +# +# printk and dmesg options +# CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7 +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_DYNAMIC_DEBUG is not set + +# +# Compile-time checks and compiler options +# +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_INFO_REDUCED=y +# CONFIG_DEBUG_INFO_SPLIT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_FRAME_POINTER=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_DEBUG_KERNEL=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_KASAN_STACK=1 +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_DEBUG_SHIRQ is not set + +# +# Debug Lockups and Hangs +# +# CONFIG_SOFTLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHEDSTATS is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_STACKTRACE is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PI_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_PREEMPTIRQ_EVENTS is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_HWLAT_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_FTRACE_SYSCALLS is not set +# CONFIG_TRACER_SNAPSHOT is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_LKDTM is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_SORT is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_TEST_HEXDUMP is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITFIELD is not set +# CONFIG_TEST_UUID is not set +# CONFIG_TEST_XARRAY is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_IDA is not set +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_SYSCTL is not set +CONFIG_TEST_UDELAY=y +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_MEMTEST is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y diff --git a/arch/riscv/include/asm/perf_event.h b/arch/riscv/include/asm/perf_event.h index aefbfaa6a78156..c6eadd500ec901 100644 --- a/arch/riscv/include/asm/perf_event.h +++ b/arch/riscv/include/asm/perf_event.h @@ -22,6 +22,11 @@ #define RISCV_MAX_COUNTERS 2 #endif +#ifdef CONFIG_ARIANE_PMU +#undef RISCV_MAX_COUNTERS +#define RISCV_MAX_COUNTERS 16 +#endif + #ifndef RISCV_MAX_COUNTERS #error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." #endif @@ -47,6 +52,26 @@ #define RISCV_OP_UNSUPP (-EOPNOTSUPP) +#ifdef CONFIG_ARIANE_PMU + +#define RISCV_OP_L1_ICACHE_MISS 2 // L1 Instr Cache Miss +#define RISCV_OP_L1_DCACHE_MISS 3 // L1 Data Cache Miss +#define RISCV_OP_ITLB_MISS 4 // ITLB Miss +#define RISCV_OP_DTLB_MISS 5 // DTLB Miss +#define RISCV_OP_LOAD 6 // Loads +#define RISCV_OP_STORE 7 // Stores +#define RISCV_OP_EXCEPTION 8 // Taken exceptions +#define RISCV_OP_EXCEPTION_RET 9 // Exception return +#define RISCV_OP_BRANCH_JUMP 10 // Software change of PC +#define RISCV_OP_CALL 11 // Procedure call +#define RISCV_OP_RET 12 // Procedure Return +#define RISCV_OP_MIS_PREDICT 13 // Branch mis-predicted +#define RISCV_OP_SB_FULL 14 // Scoreboard full +#define RISCV_OP_IF_EMPTY 15 // instruction fetch queue empty +// #define RISCV_OP_DCACHE_RW 16 + +#endif + struct cpu_hw_events { /* # currently enabled events*/ int n_events; diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index b6bb10b92fe24e..e7a96378e85e96 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -26,6 +26,10 @@ #define SBI_REMOTE_SFENCE_VMA_ASID 7 #define SBI_SHUTDOWN 8 +#ifdef CONFIG_ARIANE_PMU +#define SBI_READ_PMU_CSR_COUNTER 9 +#endif + #define SBI_CALL(which, arg0, arg1, arg2) ({ \ register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0); \ register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1); \ @@ -43,6 +47,13 @@ #define SBI_CALL_1(which, arg0) SBI_CALL(which, arg0, 0, 0) #define SBI_CALL_2(which, arg0, arg1) SBI_CALL(which, arg0, arg1, 0) +#ifdef CONFIG_ARIANE_PMU +static inline unsigned long sbi_pmu_csr_read(int csr_idx) +{ + return SBI_CALL_1(SBI_READ_PMU_CSR_COUNTER, csr_idx); +} +#endif + static inline void sbi_console_putchar(int ch) { SBI_CALL_1(SBI_CONSOLE_PUTCHAR, ch); diff --git a/arch/riscv/kernel/perf_event.c b/arch/riscv/kernel/perf_event.c index 667ee70defea16..7e16847d26ef3d 100644 --- a/arch/riscv/kernel/perf_event.c +++ b/arch/riscv/kernel/perf_event.c @@ -31,14 +31,95 @@ #include #include #include +#include + +#ifdef CONFIG_ARIANE_PMU +#define USE_M_MODE 1 + +#if USE_M_MODE + +#define CSR_CYCLE 0xB00 +#define CSR_INSTRET 0xB02 +// Performance counters (Machine Mode) +#define CSR_L1_ICACHE_MISS 0xB03 // L1 Instr Cache Miss +#define CSR_L1_DCACHE_MISS 0xB04 // L1 Data Cache Miss +#define CSR_ITLB_MISS 0xB05 // ITLB Miss +#define CSR_DTLB_MISS 0xB06 // DTLB Miss +#define CSR_LOAD 0xB07 // Loads +#define CSR_STORE 0xB08 // Stores +#define CSR_EXCEPTION 0xB09 // Taken exceptions +#define CSR_EXCEPTION_RET 0xB0A // Exception return +#define CSR_BRANCH_JUMP 0xB0B // Software change of PC +#define CSR_CALL 0xB0C // Procedure call +#define CSR_RET 0xB0D // Procedure Return +#define CSR_MIS_PREDICT 0xB0E // Branch mis-predicted +#define CSR_SB_FULL 0xB0F // Scoreboard full +#define CSR_IF_EMPTY 0xB10 // instruction fetch queue empty + +#else + +// Counters and Timers (User Mode - R/O Shadows) +#define CSR_CYCLE 0xC00 +#define CSR_TIME 0xC01 +#define CSR_INSTRET 0xC02 + // Performance counters (User Mode - R/O Shadows) +#define CSR_L1_ICACHE_MISS 0xC03 // L1 Instr Cache Miss +#define CSR_L1_DCACHE_MISS 0xC04 // L1 Data Cache Miss +#define CSR_ITLB_MISS 0xC05 // ITLB Miss +#define CSR_DTLB_MISS 0xC06 // DTLB Miss +#define CSR_LOAD 0xC07 // Loads +#define CSR_STORE 0xC08 // Stores +#define CSR_EXCEPTION 0xC09 // Taken exceptions +#define CSR_EXCEPTION_RET 0xC0A // Exception return +#define CSR_BRANCH_JUMP 0xC0B // Software change of PC +#define CSR_CALL 0xC0C // Procedure call +#define CSR_RET 0xC0D // Procedure Return +#define CSR_MIS_PREDICT 0xC0E // Branch mis-predicted +#define CSR_SB_FULL 0xC0F // Scoreboard full +#define CSR_IF_EMPTY 0xC10 // instruction fetch queue empty + +#endif +#endif static const struct riscv_pmu *riscv_pmu __read_mostly; static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); +#ifdef CONFIG_ARIANE_PMU +static const int riscv_event_idx_csr_map[] = { + [RISCV_PMU_CYCLE] = CSR_CYCLE, + [RISCV_PMU_INSTRET] = CSR_INSTRET, + [RISCV_OP_L1_ICACHE_MISS] = CSR_L1_ICACHE_MISS, + [RISCV_OP_L1_DCACHE_MISS] = CSR_L1_DCACHE_MISS, + [RISCV_OP_ITLB_MISS] = CSR_ITLB_MISS, + [RISCV_OP_DTLB_MISS] = CSR_DTLB_MISS, + [RISCV_OP_LOAD] = CSR_LOAD, + [RISCV_OP_STORE] = CSR_STORE, + [RISCV_OP_EXCEPTION] = CSR_EXCEPTION, + [RISCV_OP_EXCEPTION_RET] = CSR_EXCEPTION_RET, + [RISCV_OP_BRANCH_JUMP] = CSR_BRANCH_JUMP, + [RISCV_OP_CALL] = CSR_CALL, + [RISCV_OP_RET] = CSR_RET, + [RISCV_OP_MIS_PREDICT] = CSR_MIS_PREDICT, + [RISCV_OP_SB_FULL] = CSR_SB_FULL, + [RISCV_OP_IF_EMPTY] = CSR_IF_EMPTY, + //[RISCV_OP_DCACHE_RW] = 0xC11, +}; +#endif + /* * Hardware & cache maps and their methods */ - +#ifdef CONFIG_ARIANE_PMU +static const int riscv_hw_event_map[] = { + [PERF_COUNT_HW_CPU_CYCLES] = RISCV_PMU_CYCLE, + [PERF_COUNT_HW_INSTRUCTIONS] = RISCV_PMU_INSTRET, + [PERF_COUNT_HW_CACHE_REFERENCES] = RISCV_OP_UNSUPP, + [PERF_COUNT_HW_CACHE_MISSES] = RISCV_OP_UNSUPP, + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = RISCV_OP_BRANCH_JUMP, + [PERF_COUNT_HW_BRANCH_MISSES] = RISCV_OP_MIS_PREDICT, + [PERF_COUNT_HW_BUS_CYCLES] = RISCV_OP_UNSUPP, + }; +#else static const int riscv_hw_event_map[] = { [PERF_COUNT_HW_CPU_CYCLES] = RISCV_PMU_CYCLE, [PERF_COUNT_HW_INSTRUCTIONS] = RISCV_PMU_INSTRET, @@ -48,8 +129,99 @@ static const int riscv_hw_event_map[] = { [PERF_COUNT_HW_BRANCH_MISSES] = RISCV_OP_UNSUPP, [PERF_COUNT_HW_BUS_CYCLES] = RISCV_OP_UNSUPP, }; +#endif #define C(x) PERF_COUNT_HW_CACHE_##x +#ifdef CONFIG_ARIANE_PMU +static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX] +[PERF_COUNT_HW_CACHE_OP_MAX] +[PERF_COUNT_HW_CACHE_RESULT_MAX] = { + [C(L1D)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_LOAD, + [C(RESULT_MISS)] = RISCV_OP_L1_DCACHE_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_STORE, + [C(RESULT_MISS)] = RISCV_OP_L1_DCACHE_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_LOAD, + [C(RESULT_MISS)] = RISCV_OP_L1_DCACHE_MISS, + }, + }, + [C(L1I)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_IF_EMPTY, + [C(RESULT_MISS)] = RISCV_OP_L1_ICACHE_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_IF_EMPTY, + [C(RESULT_MISS)] = RISCV_OP_L1_ICACHE_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_IF_EMPTY, + [C(RESULT_MISS)] = RISCV_OP_L1_ICACHE_MISS, + }, + }, + [C(LL)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + }, + [C(DTLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_DTLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_DTLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_DTLB_MISS, + }, + }, + [C(ITLB)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_ITLB_MISS, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_ITLB_MISS, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_ITLB_MISS, + }, + }, + [C(BPU)] = { + [C(OP_READ)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + [C(OP_WRITE)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + [C(OP_PREFETCH)] = { + [C(RESULT_ACCESS)] = RISCV_OP_UNSUPP, + [C(RESULT_MISS)] = RISCV_OP_UNSUPP, + }, + }, +}; +#else static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX] [PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_RESULT_MAX] = { @@ -138,6 +310,7 @@ static const int riscv_cache_event_map[PERF_COUNT_HW_CACHE_MAX] }, }, }; +#endif static int riscv_map_hw_event(u64 config) { @@ -150,7 +323,14 @@ static int riscv_map_hw_event(u64 config) int riscv_map_cache_decode(u64 config, unsigned int *type, unsigned int *op, unsigned int *result) { +#ifdef CONFIG_ARIANE_PMU + *type = config & 0xFF; + *op = (config >> 8) & 0xFF; + *result = (config >> 16) & 0xFF; + return 0; +#else return -ENOENT; +#endif } static int riscv_map_cache_event(u64 config) @@ -183,6 +363,88 @@ static inline u64 read_counter(int idx) { u64 val = 0; +#ifdef CONFIG_ARIANE_PMU + if (idx >= RISCV_PMU_CYCLE && idx <= RISCV_OP_IF_EMPTY) { +#if USE_M_MODE + if (RISCV_OP_BRANCH_JUMP == idx) { + //val = sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_EXCEPTION_RET]); + //val += sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_RET]); + //val += sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_CALL]); + val = sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_BRANCH_JUMP]); + // } else if (RISCV_OP_DCACHE_RW == idx) { + // val = sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_LOAD]); + // val += sbi_pmu_csr_read(riscv_event_idx_csr_map[RISCV_OP_STORE]); + } else + val = sbi_pmu_csr_read(riscv_event_idx_csr_map[idx]); +#else + switch(riscv_event_idx_csr_map[idx]) { + case CSR_CYCLE: + val = csr_read(CSR_CYCLE); + break; + case CSR_TIME: + val = csr_read(CSR_TIME); + break; + case CSR_INSTRET: + val = csr_read(CSR_INSTRET); + break; + case CSR_L1_ICACHE_MISS: + val = csr_read(CSR_L1_ICACHE_MISS); + break; + case CSR_L1_DCACHE_MISS: + val = csr_read(CSR_L1_DCACHE_MISS); + break; + case CSR_ITLB_MISS: + val = csr_read(CSR_ITLB_MISS); + break; + case CSR_DTLB_MISS: + val = csr_read(CSR_DTLB_MISS); + break; + case CSR_LOAD: + val = csr_read(CSR_LOAD); + break; + case CSR_STORE: + val = csr_read(CSR_STORE); + break; + // case 0xC11: + // val = csr_read(CSR_LOAD); + // val += csr_read(CSR_STORE); + // break; + case CSR_EXCEPTION: + val = csr_read(CSR_EXCEPTION); + break; + case CSR_EXCEPTION_RET: + val = csr_read(CSR_EXCEPTION_RET); + break; + case CSR_BRANCH_JUMP: + //val = csr_read(CSR_EXCEPTION_RET); + //val += csr_read(CSR_RET); + //val += csr_read(CSR_CALL); + val = csr_read(CSR_BRANCH_JUMP); + break; + case CSR_CALL: + val = csr_read(CSR_CALL); + break; + case CSR_RET: + val = csr_read(CSR_RET); + break; + case CSR_MIS_PREDICT: + val = csr_read(CSR_MIS_PREDICT); + break; + case CSR_SB_FULL: + val = csr_read(CSR_SB_FULL); + break; + case CSR_IF_EMPTY: + val = csr_read(CSR_IF_EMPTY); + break; + default: + break; + } +#endif + } else { + WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); + return -EINVAL; + } +#else switch (idx) { case RISCV_PMU_CYCLE: val = csr_read(cycle); @@ -194,6 +456,7 @@ static inline u64 read_counter(int idx) WARN_ON_ONCE(idx < 0 || idx > RISCV_MAX_COUNTERS); return -EINVAL; } +#endif return val; } @@ -452,7 +715,11 @@ static const struct riscv_pmu riscv_base_pmu = { .map_cache_event = riscv_map_cache_event, .cache_events = &riscv_cache_event_map, .counter_width = 63, +#ifdef CONFIG_ARIANE_PMU + .num_counters = RISCV_MAX_COUNTERS + 0, +#else .num_counters = RISCV_BASE_COUNTERS + 0, +#endif .handle_irq = &riscv_base_pmu_handle_irq, /* This means this PMU has no IRQ. */ diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 28fcd8f580a1d7..fbff935afba94f 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -938,6 +938,12 @@ config MMC_BCM2835 If unsure, say N. +config MMC_LOWRISC + tristate "LowRISC SD/MMC Card Interface Driver" + depends on RISCV + help + This selects the LowRISC SD-card driver based on Nexys4-DDR from Digilent + config MMC_MTK tristate "MediaTek SD/MMC Card Interface support" depends on HAS_DMA diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile index 73578718f11990..2656d1a40d4956 100644 --- a/drivers/mmc/host/Makefile +++ b/drivers/mmc/host/Makefile @@ -73,6 +73,7 @@ obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o obj-$(CONFIG_MMC_USDHI6ROL0) += usdhi6rol0.o obj-$(CONFIG_MMC_TOSHIBA_PCI) += toshsd.o obj-$(CONFIG_MMC_BCM2835) += bcm2835.o +obj-$(CONFIG_MMC_LOWRISC) += lowrisc_sd.o obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o obj-$(CONFIG_MMC_REALTEK_USB) += rtsx_usb_sdmmc.o diff --git a/drivers/mmc/host/lowrisc_sd.c b/drivers/mmc/host/lowrisc_sd.c new file mode 100644 index 00000000000000..d2570eb8ad5c8b --- /dev/null +++ b/drivers/mmc/host/lowrisc_sd.c @@ -0,0 +1,803 @@ +/* + * LowRISC Secure Digital Host Controller Interface driver + * + * Copyright (C) 2018 LowRISC CIC + * + * Based on toshsd.c + * Copyright (C) 2014 Ondrej Zary + * Copyright (C) 2007 Richard Betts, All Rights Reserved. + * + * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and, + * sdhci.c, copyright (C) 2005-2006 Pierre Ossman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "lowrisc_sd.h" + +#define DRIVER_NAME "lowrisc-mmc" +#define LOG(l) printk l +#define LOGV(l) pr_debug l + +static volatile uint64_t *led_sd_base; +static uint32_t led_last; + +#ifdef CONFIG_LOWRISC_GPIO +#include +#include +#define GPIO_MAJOR 200 +#define GPIO_MINOR 0 +#define GPIO_DEV_COUNT 2 + +static int gpio_open( struct inode *, struct file * ); +static ssize_t gpio_read( struct file * , char * , size_t, loff_t *); +static ssize_t gpio_write(struct file * , const char * , size_t, loff_t *); +static int gpio_close(struct inode *, struct file * ); +struct file_operations gpio_fops = { + read : gpio_read, + write : gpio_write, + open : gpio_open, + release : gpio_close, + owner : THIS_MODULE +}; + +struct cdev gpio_cdev; + +int gpio_init_module(void) +{ + + dev_t devno; + unsigned int count = GPIO_DEV_COUNT; // apply for two minor for two LED + int err; + + devno = MKDEV(GPIO_MAJOR, GPIO_MINOR); + register_chrdev_region(devno, count , "myLED"); + + // -- initial the char device + cdev_init(&gpio_cdev, &gpio_fops); + gpio_cdev.owner = THIS_MODULE; + err = cdev_add(&gpio_cdev, devno, count); + + if (err < 0) + { + printk("Device Add Error\n"); + return -1; + } + + printk("This is lowrisc-gpio driver.\n"); + + return 0; +} + +void gpio_cleanup_module(void) +{ + dev_t devno; + + devno = MKDEV(GPIO_MAJOR, GPIO_MINOR); + + unregister_chrdev_region(devno, GPIO_DEV_COUNT); + cdev_del(&gpio_cdev); +} + +/* + * file operation: OPEN + * */ +static int gpio_open(struct inode *inod, struct file *fil) +{ + return 0; +} + +/* + * file operation: READ + * */ +static ssize_t gpio_read(struct file *filp, char *buff, size_t len, loff_t *off) +{ + static const char hex[] = "0123456789ABCDEF"; + + int led_value = 0; + short count; + char msg[5]; + + if (*off) + return 0; + + if (led_sd_base) + led_value = led_sd_base[from_dip]; + + msg[0] = hex[(led_value >> 12)&0xF]; + msg[1] = hex[(led_value >> 8)&0xF]; + msg[2] = hex[(led_value >> 4)&0xF]; + msg[3] = hex[(led_value >> 0)&0xF]; + + if (len > 4) + len = 4; + + count = raw_copy_to_user(buff, msg, len); + + return len; +} + +/* + * file operation: WRITE + * */ +static ssize_t gpio_write(struct file *filp, const char *buff, size_t len, loff_t *off) +{ + short count; + char *endp, msg[7]; + + if (*off) + return 0; + + if (len > 6) + len = 6; + count = raw_copy_from_user( msg, buff, len ); + msg[len] = 0; + + if (led_sd_base) + { + led_last = (led_last&red_led) | (simple_strtol(msg, &endp, 16) & ~red_led); + printk("User msg %s, led=%X", msg, led_last); + led_sd_base[led_reg] = led_last; + } + return len; +} + +/* + * file operation : CLOSE + * */ +static int gpio_close(struct inode *inod, struct file *fil) +{ + return 0; +} +#endif + +static void lowrisc_sd_set_led(struct lowrisc_sd_host *host, unsigned char state) +{ + volatile uint64_t *sd_base = host->ioaddr; + if (!led_sd_base) + led_sd_base = sd_base; + if (state) + led_last |= red_led; + else + led_last &= ~red_led; + led_sd_base[led_reg] = led_last; +} + +void sd_align(struct lowrisc_sd_host *host, int d_align) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[align_reg] = d_align; +} + +void sd_clk_div(struct lowrisc_sd_host *host, int clk_div) +{ + volatile uint64_t *sd_base = host->ioaddr; + /* This section is incomplete */ + sd_base[clk_din_reg] = clk_div; +} + +void sd_arg(struct lowrisc_sd_host *host, uint32_t arg) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[arg_reg] = arg; +} + +void sd_cmd(struct lowrisc_sd_host *host, uint32_t cmd) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[cmd_reg] = cmd; +} + +void sd_setting(struct lowrisc_sd_host *host, int setting) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[setting_reg] = setting; +} + +void sd_cmd_start(struct lowrisc_sd_host *host, int sd_cmd) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[start_reg] = sd_cmd; +} + +void sd_reset(struct lowrisc_sd_host *host, int sd_rst, int clk_rst, int data_rst, int cmd_rst) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[reset_reg] = ((sd_rst&1) << 3)|((clk_rst&1) << 2)|((data_rst&1) << 1)|((cmd_rst&1) << 0); +} + +void sd_blkcnt(struct lowrisc_sd_host *host, int d_blkcnt) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[blkcnt_reg] = d_blkcnt&0xFFFF; +} + +void sd_blksize(struct lowrisc_sd_host *host, int d_blksize) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[blksiz_reg] = d_blksize&0xFFF; +} + +void sd_timeout(struct lowrisc_sd_host *host, int d_timeout) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[timeout_reg] = d_timeout; +} + +void sd_irq_en(struct lowrisc_sd_host *host, int mask) +{ + volatile uint64_t *sd_base = host->ioaddr; + sd_base[irq_en_reg] = mask; + host->int_en = mask; + pr_debug("sd_irq_en(%X)\n", mask); +} + +static void lowrisc_sd_init(struct lowrisc_sd_host *host) +{ + +} + +/* Set MMC clock / power */ +static void __lowrisc_sd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + switch (ios->power_mode) { + case MMC_POWER_OFF: + mdelay(1); + break; + case MMC_POWER_UP: + break; + case MMC_POWER_ON: +#if 0 + mdelay(20); +#endif + break; + } + + switch (ios->bus_width) { + case MMC_BUS_WIDTH_1: + host->width_setting = 0; + break; + case MMC_BUS_WIDTH_4: + host->width_setting = 0x20; + break; + } +} + +static void lowrisc_sd_finish_request(struct lowrisc_sd_host *host) +{ + struct mmc_request *mrq = host->mrq; + + /* Write something to end the command */ + host->mrq = NULL; + host->cmd = NULL; + host->data = NULL; + + sd_reset(host, 0,1,0,1); + sd_cmd_start(host, 0); + sd_reset(host, 0,1,1,1); + lowrisc_sd_set_led(host, 0); + mmc_request_done(host->mmc, mrq); +} + +static void lowrisc_sd_cmd_irq(struct lowrisc_sd_host *host) +{ + struct mmc_command *cmd = host->cmd; + volatile uint64_t *sd_base = host->ioaddr; + + LOGV (("lowrisc_sd_cmd_irq\n")); + + if (!host->cmd) { + dev_warn(&host->pdev->dev, "Spurious CMD irq\n"); + return; + } + host->cmd = NULL; + + LOGV (("lowrisc_sd_cmd_irq IRQ line %d\n", __LINE__)); + if (cmd->flags & MMC_RSP_PRESENT && cmd->flags & MMC_RSP_136) { + int i; + LOGV (("lowrisc_sd_cmd_irq IRQ line %d\n", __LINE__)); + /* R2 */ + for (i = 0;i < 4;i++) + { + cmd->resp[i] = sd_base[resp0 + (3-i)] << 8; + if (i != 3) + cmd->resp[i] |= sd_base[resp0 + (2-i)] >> 24; + } + } else if (cmd->flags & MMC_RSP_PRESENT) { + LOGV (("lowrisc_sd_cmd_irq IRQ line %d\n", __LINE__)); + /* R1, R1B, R3, R6, R7 */ + cmd->resp[0] = sd_base[resp0]; + } + +LOGV (("Command IRQ complete %d %d %x\n", cmd->opcode, cmd->error, cmd->flags)); + + /* If there is data to handle we will + * finish the request in the mmc_data_end_irq handler.*/ + if (host->data) + { + host->int_en |= SD_CARD_RW_END; + } + else + lowrisc_sd_finish_request(host); +} + +static void lowrisc_sd_data_end_irq(struct lowrisc_sd_host *host) +{ + struct mmc_data *data = host->data; + unsigned long flags; + + LOGV (("lowrisc_sd_data_end_irq\n")); + + host->data = NULL; + + if (!data) { + dev_warn(&host->pdev->dev, "Spurious data end IRQ\n"); + return; + } + + if (data->flags & MMC_DATA_READ) + { + volatile uint64_t *sd_base = 0x1000 + (volatile uint64_t *)(host->ioaddr); + int len; + size_t blksize = data->blksz; + + local_irq_save(flags); + + BUG_ON(!sg_miter_next(&host->sg_miter)); + BUG_ON(host->sg_miter.length < blksize); + + if (!((sizeof(u64)-1) & (size_t)(host->sg_miter.addr))) // optimise case for aligned buffer + { + u64 *buf = (u64 *)(host->sg_miter.addr); + for (len = blksize; len > 0; len -= sizeof(u64)) + { + *buf++ = *sd_base++; + } + } + else + { + u8 *buf = host->sg_miter.addr; + for (len = blksize; len > 0; len -= sizeof(u64)) + { + u64 scratch = *sd_base++; + memcpy(buf, &scratch, sizeof(u64)); + buf += sizeof(u64); + } + } + host->sg_miter.consumed = blksize; + sg_miter_stop(&host->sg_miter); + + local_irq_restore(flags); + } + + if (data->error == 0) + data->bytes_xfered = data->blocks * data->blksz; + else + data->bytes_xfered = 0; + + LOGV (("Completed data request xfr=%d\n", + data->bytes_xfered)); + + // iowrite16(0, host->ioaddr + SD_STOPINTERNAL); + + lowrisc_sd_finish_request(host); +} + +static irqreturn_t lowrisc_sd_irq(int irq, void *dev_id) +{ + struct lowrisc_sd_host *host = dev_id; + volatile uint64_t *sd_base = host->ioaddr; + u32 int_reg, int_status; + int error = 0, ret = IRQ_HANDLED; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + int_status = sd_base[irq_stat_resp]; + int_reg = int_status & host->int_en; + + /* nothing to do: it's not our IRQ */ + if (!int_reg) { + ret = IRQ_NONE; + goto irq_end; + } + + LOGV (("lowrisc_sd IRQ status:%x enabled:%x\n", int_status, host->int_en)); + + if (sd_base[wait_resp] >= sd_base[timeout_resp]) { + error = -ETIMEDOUT; + LOGV (("lowrisc_sd timeout %lld clocks\n", sd_base[timeout_resp])); + } else if (int_reg & 0) { + error = -EILSEQ; + dev_err(&host->pdev->dev, "BadCRC\n"); + } + + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + + if (error) { + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + if (host->cmd) + host->cmd->error = error; + + if (error == -ETIMEDOUT) { + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + sd_cmd_start(host, 0); + sd_setting(host, 0); + } else { + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + lowrisc_sd_init(host); + __lowrisc_sd_set_ios(host->mmc, &host->mmc->ios); + goto irq_end; + } + } + + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + + /* Card insert/remove. The mmc controlling code is stateless. */ + if (int_reg & SD_CARD_CARD_REMOVED_0) + { + int mask = (host->int_en & ~SD_CARD_CARD_REMOVED_0) | SD_CARD_CARD_INSERTED_0; + sd_irq_en(host, mask); + printk("Card removed, mask changed to %d\n", mask); + mmc_detect_change(host->mmc, 1); + } + + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + if (int_reg & SD_CARD_CARD_INSERTED_0) + { + int mask = (host->int_en & ~SD_CARD_CARD_INSERTED_0) | SD_CARD_CARD_REMOVED_0 ; + sd_irq_en(host, mask); + printk("Card inserted, mask changed to %d\n", mask); + lowrisc_sd_init(host); + mmc_detect_change(host->mmc, 1); + } + + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + /* Command completion */ + if (int_reg & SD_CARD_RESP_END) { + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + + lowrisc_sd_cmd_irq(host); + host->int_en &= ~SD_CARD_RESP_END; + } + + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + /* Data transfer completion */ + if (int_reg & SD_CARD_RW_END) { + LOGV (("lowrisc_sd IRQ line %d\n", __LINE__)); + + lowrisc_sd_data_end_irq(host); + host->int_en &= ~SD_CARD_RW_END; + } +irq_end: + sd_irq_en(host, host->int_en); + spin_unlock_irqrestore(&host->lock, flags); + return ret; +} + +static void lowrisc_sd_start_cmd(struct lowrisc_sd_host *host, struct mmc_command *cmd) +{ + int setting = 0; + int timeout = 1000000; + struct mmc_data *data = host->data; + volatile uint64_t *sd_base = host->ioaddr; + unsigned long flags; + spin_lock_irqsave(&host->lock, flags); + + LOGV (("Command opcode: %d\n", cmd->opcode)); +/* + if (cmd->opcode == MMC_STOP_TRANSMISSION) { + sd_cmd(host, SD_STOPINT_ISSUE_CMD12); + + cmd->resp[0] = cmd->opcode; + cmd->resp[1] = 0; + cmd->resp[2] = 0; + cmd->resp[3] = 0; + + lowrisc_sd_finish_request(host); + return; + } +*/ + if (!(cmd->flags & MMC_RSP_PRESENT)) + setting = 0; + else if (cmd->flags & MMC_RSP_136) + setting = 3; + else if (cmd->flags & MMC_RSP_BUSY) + setting = 1; + else + setting = 1; + setting |= host->width_setting; + + host->cmd = cmd; + + if (cmd->opcode == MMC_APP_CMD) + { + /* placeholder */ + } + + if (cmd->opcode == MMC_GO_IDLE_STATE) + { + /* placeholder */ + } + + LOGV (("testing data flags\n")); + if (data) { + setting |= 0x4; + if (data->flags & MMC_DATA_READ) + setting |= 0x10; + else + { + setting |= 0x8; + } + } + + LOGV (("writing registers\n")); + /* Send the command */ + sd_reset(host, 0,1,0,1); + sd_align(host, 0); + sd_arg(host, cmd->arg); + sd_cmd(host, cmd->opcode); + sd_setting(host, setting); + sd_cmd_start(host, 0); + sd_reset(host, 0,1,1,1); + sd_timeout(host, timeout); + /* start the transaction */ + sd_cmd_start(host, 1); + LOGV (("enabling interrupt\n")); + sd_irq_en(host, sd_base[irq_en_resp] | SD_CARD_RESP_END); + spin_unlock_irqrestore(&host->lock, flags); + LOGV (("leaving lowrisc_sd_start_cmd\n")); +} + +static void lowrisc_sd_start_data(struct lowrisc_sd_host *host, struct mmc_data *data) +{ + unsigned int flags = SG_MITER_ATOMIC; + + LOGV (("setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n", + data->blksz, data->blocks, data->sg->offset)); + + host->data = data; + + if (data->flags & MMC_DATA_READ) + flags |= SG_MITER_TO_SG; + else + flags |= SG_MITER_FROM_SG; + + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); + + /* Set transfer length and blocksize */ + sd_blkcnt(host, data->blocks); + sd_blksize(host, data->blksz); + + if (!(data->flags & MMC_DATA_READ)) + { + volatile uint64_t *sd_base = 0x1000 + (volatile uint64_t *)(host->ioaddr); + struct mmc_data *data = host->data; + if (sg_miter_next(&host->sg_miter)) + { + int len; + size_t blksize = data->blksz; + BUG_ON(host->sg_miter.length < blksize); + if (!((sizeof(u64)-1) & (size_t)(host->sg_miter.addr))) // optimise case for aligned buffer + { + u64 *buf = (u64 *)(host->sg_miter.addr); + for (len = blksize; len > 0; len -= sizeof(u64)) + { + *sd_base++ = *buf++; + } + } + else + { + u8 *buf = host->sg_miter.addr; + for (len = blksize; len > 0; len -= sizeof(u64)) + { + u64 scratch; + memcpy(&scratch, buf, sizeof(u64)); + buf += sizeof(u64); + *sd_base++ = scratch; + } + } + host->sg_miter.consumed = blksize; + sg_miter_stop(&host->sg_miter); + } + } +} + +/* Process requests from the MMC layer */ +static void lowrisc_sd_request(struct mmc_host *mmc, struct mmc_request *mrq) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + volatile uint64_t *sd_base = host->ioaddr; + unsigned long flags; + + /* abort if card not present */ + if (sd_base[detect_resp]) { + mrq->cmd->error = -ENOMEDIUM; + mmc_request_done(mmc, mrq); + return; + } + + spin_lock_irqsave(&host->lock, flags); + + WARN_ON(host->mrq != NULL); + + host->mrq = mrq; + + if (mrq->data) + lowrisc_sd_start_data(host, mrq->data); + + lowrisc_sd_set_led(host, 1); + + lowrisc_sd_start_cmd(host, mrq->cmd); + + spin_unlock_irqrestore(&host->lock, flags); +} + +static void lowrisc_sd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + __lowrisc_sd_set_ios(mmc, ios); + spin_unlock_irqrestore(&host->lock, flags); +} + +static int lowrisc_sd_get_ro(struct mmc_host *mmc) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + volatile uint64_t *sd_base = host->ioaddr; + return sd_base[detect_resp]; +} + +static int lowrisc_sd_get_cd(struct mmc_host *mmc) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + volatile uint64_t *sd_base = host->ioaddr; + + return !sd_base[detect_resp]; +} + +static int lowrisc_sd_card_busy(struct mmc_host *mmc) +{ + struct lowrisc_sd_host *host = mmc_priv(mmc); + volatile uint64_t *sd_base = host->ioaddr; + return sd_base[start_resp]; +} + +static struct mmc_host_ops lowrisc_sd_ops = { + .request = lowrisc_sd_request, + .set_ios = lowrisc_sd_set_ios, + .get_ro = lowrisc_sd_get_ro, + .get_cd = lowrisc_sd_get_cd, + .card_busy = lowrisc_sd_card_busy, +}; + + +static void lowrisc_sd_powerdown(struct lowrisc_sd_host *host) +{ + volatile uint64_t *sd_base = host->ioaddr; + /* mask all interrupts */ + sd_base[irq_en_reg] = 0; + /* disable card clock */ +} + +static int lowrisc_sd_probe(struct platform_device *pdev) +{ + int ret; + struct lowrisc_sd_host *host; + struct mmc_host *mmc; + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + mmc = mmc_alloc_host(sizeof(struct lowrisc_sd_host), &pdev->dev); + if (!mmc) { + ret = -ENOMEM; + goto release; + } + + host = mmc_priv(mmc); + host->mmc = mmc; + + host->pdev = pdev; + + if (!request_mem_region(iomem->start, resource_size(iomem), + mmc_hostname(host->mmc))) { + dev_err(&pdev->dev, "cannot request region\n"); + ret = -EBUSY; + goto release; + } + + led_sd_base = host->ioaddr; +#ifdef CONFIG_LOWRISC_GPIO + gpio_init_module(); +#endif + host->ioaddr = ioremap(iomem->start, resource_size(iomem)); + if (!host->ioaddr) { + ret = -ENOMEM; + goto release; + } + printk("lowrisc-digilent-sd: Lowrisc sd platform driver (%llX-%llX) mapped to %lx\n", + iomem[0].start, + iomem[0].end, + (size_t)(host->ioaddr)); + + host->irq = platform_get_irq(pdev, 0); + + /* Set MMC host parameters */ + mmc->ops = &lowrisc_sd_ops; + mmc->caps = MMC_CAP_4_BIT_DATA; + mmc->ocr_avail = MMC_VDD_32_33; + + mmc->f_min = 5000000; + mmc->f_max = 5000000; + mmc->max_blk_count = 1; + + spin_lock_init(&host->lock); + + lowrisc_sd_init(host); + + ret = request_irq(host->irq, lowrisc_sd_irq, 0, DRIVER_NAME, host); + + if (ret) + { + printk("request_irq failed\n"); + goto unmap; + } + + mmc_add_host(mmc); + + printk("lowrisc-sd driver loaded, IRQ %d\n", host->irq); + sd_irq_en(host, SD_CARD_CARD_INSERTED_0 | SD_CARD_CARD_REMOVED_0); /* get an interrupt either way */ + return 0; + +unmap: +release: + mmc_free_host(mmc); + return ret; +} + +static int lowrisc_sd_remove(struct platform_device *pdev) +{ + struct lowrisc_sd_host *host = platform_get_drvdata(pdev); + + mmc_remove_host(host->mmc); + lowrisc_sd_powerdown(host); + free_irq(host->irq, host); + mmc_free_host(host->mmc); + return 0; +} + +static const struct of_device_id lowrisc_sd_of_match[] = { + { .compatible = DRIVER_NAME }, + { } +}; + +MODULE_DEVICE_TABLE(of, lowrisc_sd_of_match); + +static struct platform_driver lowrisc_sd_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = lowrisc_sd_of_match, + }, + .probe = lowrisc_sd_probe, + .remove = lowrisc_sd_remove, +}; + +module_platform_driver(lowrisc_sd_driver); + +MODULE_AUTHOR("Jonathan Kimmitt"); +MODULE_DESCRIPTION("LowRISC Secure Digital Host Controller Interface driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/mmc/host/lowrisc_sd.h b/drivers/mmc/host/lowrisc_sd.h new file mode 100644 index 00000000000000..8aa18fa0e68b24 --- /dev/null +++ b/drivers/mmc/host/lowrisc_sd.h @@ -0,0 +1,52 @@ +/* + * LowRISC PCI Secure Digital Host Controller Interface driver + * + * Based on toshsd.h + * + * Copyright (C) 2014 Ondrej Zary + * Copyright (C) 2007 Richard Betts, All Rights Reserved. + * + * Based on asic3_mmc.c Copyright (c) 2005 SDG Systems, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +enum {align_reg,clk_din_reg,arg_reg,cmd_reg, + setting_reg,start_reg,reset_reg,blkcnt_reg, + blksiz_reg,timeout_reg,clk_pll_reg,irq_en_reg, + unused1,unused2,unused3,led_reg}; + +enum {resp0,resp1,resp2,resp3, + wait_resp,status_resp,packet_resp0,packet_resp1, + data_wait_resp,trans_cnt_resp,obsolete1,obsolet2, + detect_resp,xfr_addr_resp,irq_stat_resp,pll_resp, + align_resp,clk_din_resp,arg_resp,cmd_i_resp, + setting_resp,start_resp,reset_resp,blkcnt_resp, + blksize_resp,timeout_resp,clk_pll_resp,irq_en_resp, + dead1,dead2,dead3,from_dip}; + +enum {SD_APP_OP_COND=41, data_buffer_offset=0x2000}; + +enum {SD_CARD_RESP_END=1,SD_CARD_RW_END=2, SD_CARD_CARD_REMOVED_0=4, SD_CARD_CARD_INSERTED_0=8}; + +enum {red_led = 1 << 21}; + +struct lowrisc_sd_host { + struct platform_device *pdev; + struct mmc_host *mmc; + + spinlock_t lock; + + struct mmc_request *mrq;/* Current request */ + struct mmc_command *cmd;/* Current command */ + struct mmc_data *data; /* Current data request */ + + struct sg_mapping_iter sg_miter; /* for PIO */ + + void __iomem *ioaddr; /* mapped address */ + int irq; + int int_en, width_setting; +}; diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index 885e00d17807ad..5d18ddf22bbd2c 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -115,6 +115,7 @@ config LANTIQ_XRX200 Support for the PMAC of the Gigabit switch (GSWIP) inside the Lantiq / Intel VRX200 VDSL SoC +source "drivers/net/ethernet/lowrisc/Kconfig" source "drivers/net/ethernet/marvell/Kconfig" source "drivers/net/ethernet/mediatek/Kconfig" source "drivers/net/ethernet/mellanox/Kconfig" diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 7b5bf96820666c..06beeb5776fab2 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_JME) += jme.o obj-$(CONFIG_KORINA) += korina.o obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o +obj-$(CONFIG_NET_VENDOR_LOWRISC) += lowrisc/ obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/ obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ diff --git a/drivers/net/ethernet/lowrisc/Kconfig b/drivers/net/ethernet/lowrisc/Kconfig new file mode 100644 index 00000000000000..cccdadc1637e32 --- /dev/null +++ b/drivers/net/ethernet/lowrisc/Kconfig @@ -0,0 +1,26 @@ +# +# Xilink device configuration +# + +config NET_VENDOR_LOWRISC + bool "Lowrisc devices" + default y + depends on RISCV + ---help--- + If you have a network (Ethernet) card belonging to this class, say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Lowrisc devices. If you say Y, you will be asked + for your specific card in the following questions. + +if NET_VENDOR_LOWRISC + +config LOWRISC_DIGILENT_100MHZ + tristate "Lowrisc 100MHz Ethernet Nexys4_DDR support" + depends on RISCV + select PHYLIB + ---help--- + This driver supports the 100MHz Ethernet for Nexys4_DDR Digilent boards from Lowrisc. + +endif # NET_VENDOR_LOWRISC diff --git a/drivers/net/ethernet/lowrisc/Makefile b/drivers/net/ethernet/lowrisc/Makefile new file mode 100644 index 00000000000000..4eb3adee161d5f --- /dev/null +++ b/drivers/net/ethernet/lowrisc/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for the Lowrisc network device driver. +# + +obj-$(CONFIG_LOWRISC_DIGILENT_100MHZ) += lowrisc_100MHz.o +CFLAGS_lowrisc_100MHz.o := -DDEBUG diff --git a/drivers/net/ethernet/lowrisc/lowrisc_100MHz.c b/drivers/net/ethernet/lowrisc/lowrisc_100MHz.c new file mode 100644 index 00000000000000..4984e7bd11cbf7 --- /dev/null +++ b/drivers/net/ethernet/lowrisc/lowrisc_100MHz.c @@ -0,0 +1,830 @@ +/* + * Lowrisc Ether100MHz Linux driver for the Lowrisc Ethernet 100MHz device. + * + * This is an experimental driver which is based on the original emac_lite + * driver from John Williams . + * + * 2007 - 2013 (c) Xilinx, Inc. + * PHY control portions copyright (C) 2015 Microchip Technology + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lowrisc_100MHz.h" + +#define DRIVER_AUTHOR "WOOJUNG HUH " +#define DRIVER_DESC "Microchip LAN8720 PHY driver" +#define DRIVER_NAME "lowrisc-eth" + +/* General Ethernet Definitions */ +#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */ +#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ + +#define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */ + +/** + * struct net_local - Our private per device data + * @ndev: instance of the network device + * @reset_lock: lock used for synchronization + * @phy_dev: pointer to the PHY device + * @phy_node: pointer to the PHY device node + * @mii_bus: pointer to the MII bus + * @last_link: last link status + */ +struct net_local { + struct mdiobb_ctrl ctrl; /* must be first for bitbang driver to work */ + void __iomem *ioaddr; + struct net_device *ndev; + u32 msg_enable; + + struct phy_device *phy_dev; + struct mii_bus *mii_bus; + int last_duplex; + int last_carrier; + + /* Spinlock */ + struct mutex lock; + uint32_t last_mdio_gpio; + int irq, num_tests, phy_addr; + + struct napi_struct napi; +}; + +static void inline eth_write(struct net_local *priv, size_t addr, int data) +{ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + eth_base[addr >> 3] = data; +} + +static void inline eth_copyout(struct net_local *priv, uint8_t *data, int len) +{ + int i, rnd = ((len-1)|7)+1; + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + if (!(((size_t)data) & 7)) + { + uint64_t *ptr = (uint64_t *)data; + for (i = 0; i < rnd/8; i++) + eth_base[TXBUFF_OFFSET/8 + i] = ptr[i]; + } + else // We can't unfortunately rely on the skb being word aligned + { + uint64_t notptr; + for (i = 0; i < rnd/8; i++) + { + memcpy(¬ptr, data+(i<<3), sizeof(uint64_t)); + eth_base[TXBUFF_OFFSET/8 + i] = notptr; + } + } +} + +static volatile inline int eth_read(struct net_local *priv, size_t addr) +{ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + return eth_base[addr >> 3]; +} + +static inline void eth_copyin(struct net_local *priv, uint8_t *data, int len, int start) +{ + int i, rnd = ((len-1)|7)+1; + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + if (!(((size_t)data) & 7)) + { + uint64_t *ptr = (uint64_t *)data; + for (i = 0; i < rnd/8; i++) + ptr[i] = eth_base[start + i]; + } + else // We can't unfortunately rely on the skb being word aligned + { + for (i = 0; i < rnd/8; i++) + { + uint64_t notptr = eth_base[start + i]; + memcpy(data+(i<<3), ¬ptr, sizeof(uint64_t)); + } + } +} + +static void inline eth_enable_irq(struct net_local *priv) +{ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + eth_base[MACHI_OFFSET >> 3] |= MACHI_IRQ_EN; + mmiowb(); +} + +static void inline eth_disable_irq(struct net_local *priv) +{ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + eth_base[MACHI_OFFSET >> 3] &= ~MACHI_IRQ_EN; + mmiowb(); +} + +/** + * lowrisc_update_address - Update the MAC address in the device + * @drvdata: Pointer to the Ether100MHz device private data + * @address_ptr:Pointer to the MAC address (MAC address is a 48-bit value) + * + * Tx must be idle and Rx should be idle for deterministic results. + * It is recommended that this function should be called after the + * initialization and before transmission of any packets from the device. + * The MAC address can be programmed using any of the two transmit + * buffers (if configured). + */ + +static void lowrisc_update_address(struct net_local *priv, u8 *address_ptr) +{ + uint32_t macaddr_lo, macaddr_hi; + memcpy (&macaddr_lo, address_ptr+2, sizeof(uint32_t)); + memcpy (&macaddr_hi, address_ptr+0, sizeof(uint16_t)); + mutex_lock(&priv->lock); + eth_write(priv, MACLO_OFFSET, htonl(macaddr_lo)); + eth_write(priv, MACHI_OFFSET, htons(macaddr_hi)); + eth_write(priv, RFCS_OFFSET, 8); /* use 8 buffers */ + mutex_unlock(&priv->lock); +} + +/** + * lowrisc_read_mac_address - Read the MAC address in the device + * @drvdata: Pointer to the Ether100MHz device private data + * @address_ptr:Pointer to the 6-byte buffer to receive the MAC address (MAC address is a 48-bit value) + * + * In lowrisc the starting value is programmed by the boot loader according to DIP switch [15:12] + */ + +static void lowrisc_read_mac_address(struct net_local *priv, u8 *address_ptr) +{ + uint32_t macaddr_hi, macaddr_lo; + mutex_lock(&priv->lock); + macaddr_hi = ntohs(eth_read(priv, MACHI_OFFSET)&MACHI_MACADDR_MASK); + macaddr_lo = ntohl(eth_read(priv, MACLO_OFFSET)); + mutex_unlock(&priv->lock); + memcpy (address_ptr+2, &macaddr_lo, sizeof(uint32_t)); + memcpy (address_ptr+0, &macaddr_hi, sizeof(uint16_t)); +} + +/** + * lowrisc_set_mac_address - Set the MAC address for this device + * @dev: Pointer to the network device instance + * @addr: Void pointer to the sockaddr structure + * + * This function copies the HW address from the sockaddr strucutre to the + * net_device structure and updates the address in HW. + * + * Return: Error if the net device is busy or 0 if the addr is set + * successfully + */ +static int lowrisc_set_mac_address(struct net_device *ndev, void *address) +{ + struct net_local *priv = netdev_priv(ndev); + struct sockaddr *addr = address; + memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); + lowrisc_update_address(priv, ndev->dev_addr); + return 0; +} + +/** + * lowrisc_tx_timeout - Callback for Tx Timeout + * @dev: Pointer to the network device + * + * This function is called when Tx time out occurs for Ether100MHz device. + */ +static void lowrisc_tx_timeout(struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + + dev_err(&priv->ndev->dev, "Exceeded transmit timeout of %lu ms\n", + TX_TIMEOUT * 1000UL / HZ); + + ndev->stats.tx_errors++; + + /* Reset the device */ + mutex_lock(&priv->lock); + + /* Shouldn't really be necessary, but shouldn't hurt */ + netif_stop_queue(ndev); + + /* To exclude tx timeout */ + netif_trans_update(ndev); /* prevent tx timeout */ + + /* We're all ready to go. Start the queue */ + netif_wake_queue(ndev); + mutex_unlock(&priv->lock); +} + +/** + * lowrisc_close - Close the network device + * @dev: Pointer to the network device + * + * This function stops the Tx queue, disables interrupts and frees the IRQ for + * the Ether100MHz device. + * It also disconnects the phy device associated with the Ether100MHz device. + */ +static int lowrisc_close(struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + + netif_stop_queue(ndev); + napi_disable(&priv->napi); + mutex_lock(&priv->lock); + eth_disable_irq(priv); + mutex_unlock(&priv->lock); + if (priv->irq) + free_irq(priv->irq, priv); + priv->irq = 0; + printk("Close device, free interrupt\n"); + + if (priv->phy_dev) + phy_disconnect(priv->phy_dev); + priv->phy_dev = NULL; + + return 0; +} + +/** + * lowrisc_remove_ndev - Free the network device + * @ndev: Pointer to the network device to be freed + * + * This function un maps the IO region of the Ether100MHz device and frees the net + * device. + */ +static void lowrisc_remove_ndev(struct net_device *ndev) +{ + if (ndev) { + free_netdev(ndev); + } +} + +static void lowrisc_phy_adjust_link(struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + struct phy_device *phy_dev = priv->phy_dev; + int carrier; + + if (phy_dev->duplex != priv->last_duplex) { + if (phy_dev->duplex) { + netif_dbg(priv, link, priv->ndev, "full duplex mode\n"); + } else { + netif_dbg(priv, link, priv->ndev, "half duplex mode\n"); + } + + priv->last_duplex = phy_dev->duplex; + } + + carrier = netif_carrier_ok(ndev); + if (carrier != priv->last_carrier) { + if (carrier) + netif_dbg(priv, link, priv->ndev, "carrier OK\n"); + else + netif_dbg(priv, link, priv->ndev, "no carrier\n"); + priv->last_carrier = carrier; + } +} + +static int lowrisc_mii_probe(struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + struct phy_device *phydev = NULL; + const char *phyname; + + BUG_ON(priv->phy_dev); + + /* find the first (lowest address) PHY + * on the current MAC's MII bus + */ + for (priv->phy_addr = 1; priv->phy_addr < PHY_MAX_ADDR; priv->phy_addr++) + { + phydev = mdiobus_get_phy(priv->mii_bus, priv->phy_addr); + if (phydev) { + /* break out with first one found */ + break; + } + } + if (!phydev) { + netdev_err(ndev, "no PHY found in range address 0..%d\n", PHY_MAX_ADDR-1); + return -ENODEV; + } + + phyname = phydev_name(phydev); + printk("Probing %s (address %d)\n", phyname, priv->phy_addr); + + phydev = phy_connect(ndev, phyname, + lowrisc_phy_adjust_link, PHY_INTERFACE_MODE_MII); + + if (IS_ERR(phydev)) { + netdev_err(ndev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + /* mask with MAC supported features */ + linkmode_copy(phydev->advertising, phydev->supported); + + phy_attached_info(phydev); + + priv->phy_dev = phydev; + priv->last_duplex = -1; + priv->last_carrier = -1; + + return 0; +} + +static void mdio_dir(struct mdiobb_ctrl *ctrl, int dir) +{ + struct net_local *priv = (struct net_local *)ctrl; /* struct mdiobb_ctrl must be first in net_local for bitbang driver to work */ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + if (dir) + priv->last_mdio_gpio |= MDIOCTRL_MDIOOEN_MASK; // output driving + else + priv->last_mdio_gpio &= ~MDIOCTRL_MDIOOEN_MASK; // input receiving + eth_base[MDIOCTRL_OFFSET >> 3] = priv->last_mdio_gpio; + mmiowb(); +} + +static int mdio_get(struct mdiobb_ctrl *ctrl) +{ + int retval; + struct net_local *priv = (struct net_local *)ctrl; /* struct mdiobb_ctrl must be first in net_local for bitbang driver to work */ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + retval = eth_base[MDIOCTRL_OFFSET >> 3]; + return retval & MDIOCTRL_MDIOIN_MASK ? 1:0; +} + +static void mdio_set(struct mdiobb_ctrl *ctrl, int what) +{ + struct net_local *priv = (struct net_local *)ctrl; /* struct mdiobb_ctrl must be first in net_local for bitbang driver to work */ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + if (what) + priv->last_mdio_gpio |= MDIOCTRL_MDIOOUT_MASK; + else + priv->last_mdio_gpio &= ~MDIOCTRL_MDIOOUT_MASK; + eth_base[MDIOCTRL_OFFSET >> 3] = priv->last_mdio_gpio; + mmiowb(); +} + +static void mdc_set(struct mdiobb_ctrl *ctrl, int what) +{ + struct net_local *priv = (struct net_local *)ctrl; /* struct mdiobb_ctrl must be first in net_local for bitbang driver to work */ + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + if (what) + priv->last_mdio_gpio |= MDIOCTRL_MDIOCLK_MASK; + else + priv->last_mdio_gpio &= ~MDIOCTRL_MDIOCLK_MASK; + eth_base[MDIOCTRL_OFFSET >> 3] = priv->last_mdio_gpio; + mmiowb(); +} + +static struct mdiobb_ops mdio_gpio_ops = { + .owner = THIS_MODULE, + .set_mdc = mdc_set, + .set_mdio_dir = mdio_dir, + .set_mdio_data = mdio_set, + .get_mdio_data = mdio_get, +}; + +static int lowrisc_mii_init(struct net_device *ndev) +{ + struct mii_bus *new_bus; + struct net_local *priv = netdev_priv(ndev); + int err = -ENXIO; + + priv->ctrl.ops = &mdio_gpio_ops; + new_bus = alloc_mdio_bitbang(&(priv->ctrl)); + + if (!new_bus) { + err = -ENOMEM; + goto err_out_1; + } + snprintf(new_bus->id, MII_BUS_ID_SIZE, "lowrisc-0"); + new_bus->name = "GPIO Bitbanged LowRISC", + + new_bus->phy_mask = ~(1 << 1); + new_bus->phy_ignore_ta_mask = 0; + + mutex_init(&(new_bus->mdio_lock)); + + priv->mii_bus = new_bus; + priv->mii_bus->priv = priv; + + /* Mask all PHYs except ID 1 (internal) */ + priv->mii_bus->phy_mask = ~(1 << 1); + + if (mdiobus_register(priv->mii_bus)) { + netif_warn(priv, probe, priv->ndev, "Error registering mii bus\n"); + goto err_out_free_bus_2; + } + + if (lowrisc_mii_probe(ndev) < 0) { + netif_warn(priv, probe, priv->ndev, "Error probing mii bus\n"); + goto err_out_unregister_bus_3; + } + + return 0; + +err_out_unregister_bus_3: + mdiobus_unregister(priv->mii_bus); +err_out_free_bus_2: + mdiobus_free(priv->mii_bus); +err_out_1: + return err; +} +/**********************/ +/* Interrupt Handlers */ +/**********************/ + +/** + * lowrisc_ether_isr - Interrupt handler for frames received + * @priv: Pointer to the struct net_local + * + * This function allocates memory for a socket buffer, fills it with data + * received and hands it over to the TCP/IP stack. + */ + +static int lowrisc_ether_poll(struct napi_struct *napiptr, int budget) +{ + int rsr, buf, rx_count = 0; + struct net_local *priv = container_of(napiptr, struct net_local, napi); + struct net_device *ndev = priv->ndev; + rsr = eth_read(priv, RSR_OFFSET); + buf = rsr & RSR_RECV_FIRST_MASK; + /* Check if there is Rx Data available */ + while ((rsr & RSR_RECV_DONE_MASK) && (rx_count < budget)) + { + int len = eth_read(priv, RPLR_OFFSET+((buf&7)<<3)) - 4; /* discard FCS bytes ?? */ + if ((len >= 60) && (len <= ETH_FRAME_LEN + ETH_FCS_LEN)) + { + int rnd = ((len-1)|7)+1; /* round to a multiple of 8 */ + struct sk_buff *skb = __napi_alloc_skb(&priv->napi, rnd, GFP_ATOMIC|__GFP_NOWARN); // Don't warn, just drop surplus packets + if (unlikely(!skb)) + { + /* Couldn't get memory, we carry on regardless and drop if necessary */ + ndev->stats.rx_dropped++; + } + else + { + int start = RXBUFF_OFFSET/8 + ((buf&7)<<8); + skb_put(skb, len); /* Tell the skb how much data we got */ + + eth_copyin(priv, skb->data, len, start); + skb->protocol = eth_type_trans(skb, ndev); + netif_receive_skb(skb); + ndev->stats.rx_packets++; + ndev->stats.rx_bytes += len; + ++rx_count; + } + } + else + ndev->stats.rx_errors++; + /* acknowledge, even if an error occurs, to reset irq */ + eth_write(priv, RSR_OFFSET, ++buf); + rsr = eth_read(priv, RSR_OFFSET); + } + + if (rsr & RSR_RECV_DONE_MASK) + { + return 1; + } + else + { + napi_complete_done(&priv->napi, rx_count); + eth_enable_irq(priv); + return 0; + } +} + +irqreturn_t lowrisc_ether_isr(int irq, void *priv_id) +{ + int rsr = 0; + struct net_local *priv = priv_id; + struct net_device *ndev = priv->ndev; + if (napi_schedule_prep(&priv->napi)) + { + eth_disable_irq(priv); + __napi_schedule(&priv->napi); + } + else /* we are in denial of service mode */ + do + { + int buf = rsr & RSR_RECV_FIRST_MASK; + ndev->stats.rx_dropped++; + eth_write(priv, RSR_OFFSET, ++buf); + rsr = eth_read(priv, RSR_OFFSET); + } + while (rsr & RSR_RECV_DONE_MASK); + return IRQ_HANDLED; +} + +static int lowrisc_get_regs_len(struct net_device __always_unused *netdev) +{ +#define LOWRISC_REGS_LEN 64 /* overestimate */ + return LOWRISC_REGS_LEN * sizeof(u32); +} + +static void lowrisc_get_regs(struct net_device *ndev, + struct ethtool_regs *regs, void *p) +{ + struct net_local *priv = netdev_priv(ndev); + struct phy_device *phy = priv->phy_dev; + + u32 *regs_buff = p; + int i; + + memset(p, 0, LOWRISC_REGS_LEN * sizeof(u32)); + + regs->version = 0; + mutex_lock(&priv->lock); + for (i = 0; i < LOWRISC_REGS_LEN; i++) + { + if (i >= 32) + regs_buff[i] = eth_read(priv, MACLO_OFFSET+((i-32)<<3)); + else + { + regs_buff[i] = phy_read(phy, i); + } + } + mutex_unlock(&priv->lock); +} + +static const struct ethtool_ops lowrisc_ethtool_ops = { + .get_regs_len = lowrisc_get_regs_len, + .get_regs = lowrisc_get_regs, + .get_link_ksettings = phy_ethtool_get_link_ksettings, + .set_link_ksettings = phy_ethtool_set_link_ksettings +}; + +/** + * lowrisc_open - Open the network device + * @dev: Pointer to the network device + * + * This function sets the MAC address, requests an IRQ and enables interrupts + * for the Ether100MHz device and starts the Tx queue. + * It also connects to the phy device, if MDIO is included in Ether100MHz device. + */ + +static int lowrisc_open(struct net_device *ndev) +{ + int retval = 0; + struct net_local *priv = netdev_priv(ndev); + ndev->ethtool_ops = &lowrisc_ethtool_ops; + + /* Set the MAC address each time opened */ + lowrisc_update_address(priv, ndev->dev_addr); + + if (priv->phy_dev) { + linkmode_copy(priv->phy_dev->advertising, priv->phy_dev->supported); + phy_start(priv->phy_dev); + } + + /* Grab the IRQ */ + printk("Open device, request interrupt %d\n", priv->irq); + retval = request_irq(priv->irq, lowrisc_ether_isr, 0, ndev->name, priv); + if (retval) { + dev_err(&priv->ndev->dev, "Could not allocate interrupt %d\n", priv->irq); + if (priv->phy_dev) + phy_disconnect(priv->phy_dev); + priv->phy_dev = NULL; + return retval; + } + + lowrisc_update_address(priv, ndev->dev_addr); + + /* We're ready to go */ + napi_enable(&priv->napi); + netif_start_queue(ndev); + + /* enable the irq */ + eth_enable_irq(priv); + return 0; +} + +/** + * lowrisc_send - Transmit a frame + * @orig_skb: Pointer to the socket buffer to be transmitted + * @dev: Pointer to the network device + * + * This function checks if the Tx buffer of the Ether100MHz device is free to send + * data. If so, it fills the Tx buffer with data from socket buffer data, + * updates the stats and frees the socket buffer. + * Return: 0, always. + */ +static netdev_tx_t lowrisc_send(struct sk_buff *new_skb, struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + unsigned int len = new_skb->len; + int rslt; + if (mutex_is_locked(&priv->lock)) + return NETDEV_TX_BUSY; + rslt = eth_read(priv, TPLR_OFFSET); + if (rslt & TPLR_BUSY_MASK) + return NETDEV_TX_BUSY; + eth_copyout(priv, new_skb->data, len); + eth_write(priv, TPLR_OFFSET, len); + + skb_tx_timestamp(new_skb); + + ndev->stats.tx_bytes += len; + ndev->stats.tx_packets++; + dev_consume_skb_any(new_skb); + + return NETDEV_TX_OK; +} + +static int lowrisc_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) +{ + struct net_local *priv = netdev_priv(netdev); + struct phy_device *phy = priv->phy_dev; + struct mii_ioctl_data *data = if_mii(ifr); + + switch (cmd) { + case SIOCGMIIPHY: + data->phy_id = 1; + break; + case SIOCGMIIREG: + data->val_out = phy_read(phy, data->reg_num); + break; + case SIOCSMIIREG: + phy_write(phy, data->reg_num, data->val_in); + break; + default: + return -EOPNOTSUPP; + } + return 0; + } + +static struct net_device_stats *lowrisc_get_stats(struct net_device *ndev) +{ + return &ndev->stats; +} + +static void lowrisc_set_rx_mode(struct net_device *ndev) +{ + struct net_local *priv = netdev_priv(ndev); + volatile uint64_t *eth_base = (volatile uint64_t *)(priv->ioaddr); + + if (ndev->flags & IFF_PROMISC) + { + /* Set promiscuous. */ + eth_base[MACHI_OFFSET >> 3] |= MACHI_ALLPKTS_MASK; + } + else + { + eth_base[MACHI_OFFSET >> 3] &= ~MACHI_ALLPKTS_MASK; + } +} +static struct net_device_ops lowrisc_netdev_ops = { + .ndo_open = lowrisc_open, + .ndo_stop = lowrisc_close, + .ndo_start_xmit = lowrisc_send, + .ndo_get_stats = lowrisc_get_stats, + .ndo_set_rx_mode = lowrisc_set_rx_mode, + .ndo_set_mac_address = lowrisc_set_mac_address, + .ndo_tx_timeout = lowrisc_tx_timeout, + .ndo_do_ioctl = lowrisc_mii_ioctl, +}; + +/** + * lowrisc_of_probe - Probe method for the Ether100MHz device. + * @ofdev: Pointer to OF device structure + * @match: Pointer to the structure used for matching a device + * + * This function probes for the Ether100MHz device in the device tree. + * It initializes the driver data structure and the hardware, sets the MAC + * address and registers the network device. + * It also registers a mii_bus for the Ether100MHz device, if MDIO is included + * in the device. + * + * Return: 0, if the driver is bound to the Ether100MHz device, or + * a negative error if there is failure. + */ +static int lowrisc_100MHz_probe(struct platform_device *ofdev) +{ + struct net_device *ndev = NULL; + struct net_local *priv = NULL; + struct device *dev = &ofdev->dev; + struct resource *lowrisc_ethernet; + unsigned char mac_address[7]; + int rc = 0; + + lowrisc_ethernet = platform_get_resource(ofdev, IORESOURCE_MEM, 0); + + /* Create an ethernet device instance */ + ndev = alloc_etherdev(sizeof(struct net_local)); + if (!ndev) + return -ENOMEM; + + dev_set_drvdata(dev, ndev); + SET_NETDEV_DEV(ndev, &ofdev->dev); + platform_set_drvdata(ofdev, ndev); + + priv = netdev_priv(ndev); + priv->ndev = ndev; + priv->ioaddr = devm_ioremap_resource(&ofdev->dev, lowrisc_ethernet); + mutex_init(&priv->lock); + + priv->num_tests = 1; + + ndev->netdev_ops = &lowrisc_netdev_ops; + ndev->flags &= ~IFF_MULTICAST; + ndev->watchdog_timeo = TX_TIMEOUT; + netif_napi_add(ndev, &priv->napi, lowrisc_ether_poll, 64); + + printk("lowrisc-digilent-ethernet: Lowrisc ethernet platform (%llX-%llX) mapped to %lx\n", + lowrisc_ethernet[0].start, + lowrisc_ethernet[0].end, + (size_t)(priv->ioaddr)); + + priv->irq = platform_get_irq(ofdev, 0); + + /* get the MAC address set by the boot loader */ + lowrisc_read_mac_address(priv, mac_address); + memcpy(ndev->dev_addr, mac_address, ETH_ALEN); + + /* Set the MAC address in the Ether100MHz device */ + lowrisc_update_address(priv, ndev->dev_addr); + + lowrisc_mii_init(ndev); + + /* Finally, register the device */ + rc = register_netdev(ndev); + if (rc) { + dev_err(dev, + "Cannot register network device, aborting\n"); + goto error; + } + + dev_info(dev, "Lowrisc Ether100MHz registered\n"); + + return 0; + +error: + lowrisc_remove_ndev(ndev); + return rc; +} + +/* Match table for OF platform binding */ +static const struct of_device_id lowrisc_100MHz_of_match[] = { + { .compatible = DRIVER_NAME }, + { /* end of list */ }, +}; +MODULE_DEVICE_TABLE(of, lowrisc_100MHz_of_match); + +void lowrisc_100MHz_free(struct platform_device *of_dev) +{ + struct resource *iomem = platform_get_resource(of_dev, IORESOURCE_MEM, 0); + release_mem_region(iomem->start, resource_size(iomem)); +} + +int lowrisc_100MHz_unregister(struct platform_device *of_dev) +{ + lowrisc_100MHz_free(of_dev); + return 0; +} + +static struct platform_driver lowrisc_100MHz_driver = { + .driver = { + .name = DRIVER_NAME, + .of_match_table = lowrisc_100MHz_of_match, + }, + .probe = lowrisc_100MHz_probe, + .remove = lowrisc_100MHz_unregister, +}; + +module_platform_driver(lowrisc_100MHz_driver); + +MODULE_AUTHOR("Jonathan Kimmitt"); +MODULE_DESCRIPTION("Lowrisc Ethernet 100MHz driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/net/ethernet/lowrisc/lowrisc_100MHz.h b/drivers/net/ethernet/lowrisc/lowrisc_100MHz.h new file mode 100644 index 00000000000000..9d227c10dd36c5 --- /dev/null +++ b/drivers/net/ethernet/lowrisc/lowrisc_100MHz.h @@ -0,0 +1,55 @@ +// See LICENSE for license details. + +#ifndef ETH_HEADER_H +#define ETH_HEADER_H + +/* Register offsets for the LowRISC Ethernet Core */ + +/* Register offsets (in bytes) for the LowRISC Core */ +#define TXBUFF_OFFSET 0x1000 /* Transmit Buffer */ + +#define MACLO_OFFSET 0x0800 /* MAC address low 32-bits */ +#define MACHI_OFFSET 0x0808 /* MAC address high 16-bits and MAC ctrl */ +#define TPLR_OFFSET 0x0810 /* Tx packet length */ +#define TFCS_OFFSET 0x0818 /* Tx frame check sequence register */ +#define MDIOCTRL_OFFSET 0x0820 /* MDIO Control Register */ +#define RFCS_OFFSET 0x0828 /* Rx frame check sequence register(read) and last register(write) */ +#define RSR_OFFSET 0x0830 /* Rx status and reset register */ +#define RBAD_OFFSET 0x0838 /* Rx bad frame and bad fcs register arrays */ +#define RPLR_OFFSET 0x0840 /* Rx packet length register array */ + +#define RXBUFF_OFFSET 0x4000 /* Receive Buffer */ + +/* MAC Ctrl Register (MACHI) Bit Masks */ +#define MACHI_MACADDR_MASK 0x0000FFFF /* MAC high 16-bits mask */ +#define MACHI_COOKED_MASK 0x00010000 /* obsolete flag */ +#define MACHI_LOOPBACK_MASK 0x00020000 /* Rx loopback packets */ +#define MACHI_ALLPKTS_MASK 0x00400000 /* Rx all packets (promiscuous mode) */ +#define MACHI_IRQ_EN 0x00800000 /* Rx packet interrupt enable */ + +/* MDIO Control Register Bit Masks */ +#define MDIOCTRL_MDIOCLK_MASK 0x00000001 /* MDIO Clock Mask */ +#define MDIOCTRL_MDIOOUT_MASK 0x00000002 /* MDIO Output Mask */ +#define MDIOCTRL_MDIOOEN_MASK 0x00000004 /* MDIO Output Enable Mask, 3-state enable, high=input, low=output */ +#define MDIOCTRL_MDIORST_MASK 0x00000008 /* MDIO Input Mask */ +#define MDIOCTRL_MDIOIN_MASK 0x00000008 /* MDIO Input Mask */ + +/* Transmit Status Register (TPLR) Bit Masks */ +#define TPLR_FRAME_ADDR_MASK 0x0FFF0000 /* Tx frame address */ +#define TPLR_PACKET_LEN_MASK 0x00000FFF /* Tx packet length */ +#define TPLR_BUSY_MASK 0x80000000 /* Tx busy mask */ + +/* Receive Status Register (RSR) */ +#define RSR_RECV_FIRST_MASK 0x0000000F /* first available buffer (static) */ +#define RSR_RECV_NEXT_MASK 0x000000F0 /* current rx buffer (volatile) */ +#define RSR_RECV_LAST_MASK 0x00000F00 /* last available rx buffer (static) */ +#define RSR_RECV_DONE_MASK 0x00001000 /* Rx complete */ +#define RSR_RECV_IRQ_MASK 0x00002000 /* Rx irq bit */ + +/* General Ethernet Definitions */ +#define HEADER_OFFSET 12 /* Offset to length field */ +#define HEADER_SHIFT 16 /* Shift value for length */ +#define ARP_PACKET_SIZE 28 /* Max ARP packet size */ +#define HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */ + +#endif diff --git a/drivers/net/ethernet/xilinx/Kconfig b/drivers/net/ethernet/xilinx/Kconfig index da4ec575ccf9ba..0699b54ee75950 100644 --- a/drivers/net/ethernet/xilinx/Kconfig +++ b/drivers/net/ethernet/xilinx/Kconfig @@ -5,7 +5,7 @@ config NET_VENDOR_XILINX bool "Xilinx devices" default y - depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS + depends on PPC || PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS || RISCV ---help--- If you have a network (Ethernet) card belonging to this class, say Y. @@ -18,7 +18,7 @@ if NET_VENDOR_XILINX config XILINX_EMACLITE tristate "Xilinx 10/100 Ethernet Lite support" - depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS + depends on PPC32 || MICROBLAZE || ARCH_ZYNQ || MIPS || RISCV select PHYLIB ---help--- This driver supports the 10/100 Ethernet Lite from Xilinx. diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c index b03a417d0073eb..7c49db3dcabf20 100644 --- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c +++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c @@ -99,7 +99,7 @@ #define ALIGNMENT 4 /* BUFFER_ALIGN(adr) calculates the number of bytes to the next alignment. */ -#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32)adr)) % ALIGNMENT) +#define BUFFER_ALIGN(adr) ((ALIGNMENT - ((u64)adr)) % ALIGNMENT) #ifdef __BIG_ENDIAN #define xemaclite_readl ioread32be @@ -340,7 +340,7 @@ static int xemaclite_send_data(struct net_local *drvdata, u8 *data, * if it is configured in HW */ - addr = (void __iomem __force *)((u32 __force)addr ^ + addr = (void __iomem __force *)((u64 __force)addr ^ XEL_BUFFER_OFFSET); reg_data = xemaclite_readl(addr + XEL_TSR_OFFSET); @@ -401,7 +401,7 @@ static u16 xemaclite_recv_data(struct net_local *drvdata, u8 *data, int maxlen) * will correct on subsequent calls */ if (drvdata->rx_ping_pong != 0) - addr = (void __iomem __force *)((u32 __force)addr ^ + addr = (void __iomem __force *)((u64 __force)addr ^ XEL_BUFFER_OFFSET); else return 0; /* No data was available */ @@ -1176,9 +1176,9 @@ static int xemaclite_of_probe(struct platform_device *ofdev) } dev_info(dev, - "Xilinx EmacLite at 0x%08X mapped to 0x%08X, irq=%d\n", - (unsigned int __force)ndev->mem_start, - (unsigned int __force)lp->base_addr, ndev->irq); + "Xilinx EmacLite at 0x%p mapped to 0x%p, irq=%d\n", + (void *)ndev->mem_start, + lp->base_addr, ndev->irq); return 0; error: