From f26a54b08f244ecb1bb0e690ede06fd7d5ba1bb0 Mon Sep 17 00:00:00 2001 From: jcoulon Date: Wed, 7 Oct 2020 17:29:06 +0200 Subject: [PATCH] dm_top.sv, dm_mem.sv: define Xlen input parameter to make dm support CPU with buswidth different from core data width --- src/dm_mem.sv | 3 ++- src/dm_top.sv | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/dm_mem.sv b/src/dm_mem.sv index 6c6400b..9582916 100644 --- a/src/dm_mem.sv +++ b/src/dm_mem.sv @@ -19,6 +19,7 @@ module dm_mem #( parameter int NrHarts = -1, parameter int BusWidth = -1, + parameter int Xlen = -1, parameter logic [NrHarts-1:0] SelectableHarts = -1 )( input logic clk_i, // Clock @@ -58,7 +59,7 @@ module dm_mem #( ); localparam int HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts); - localparam int MaxAar = (BusWidth == 64) ? 4 : 3; + localparam int MaxAar = (Xlen == 64) ? 4 : 3; localparam DbgAddressBits = 12; localparam logic [DbgAddressBits-1:0] DataBase = (dm::DataAddr); localparam logic [DbgAddressBits-1:0] DataEnd = (dm::DataAddr + 4*dm::DataCount); diff --git a/src/dm_top.sv b/src/dm_top.sv index ad20535..96bc096 100644 --- a/src/dm_top.sv +++ b/src/dm_top.sv @@ -20,6 +20,7 @@ module dm_top #( parameter int NrHarts = 1, parameter int BusWidth = 32, + parameter int Xlen = 32, parameter logic [NrHarts-1:0] SelectableHarts = 1 // Bitmask to select physically available harts for systems // that don't use hart numbers in a contiguous fashion. @@ -183,6 +184,7 @@ module dm_top #( dm_mem #( .NrHarts(NrHarts), .BusWidth(BusWidth), + .Xlen(Xlen), .SelectableHarts(SelectableHarts) ) i_dm_mem ( .clk_i ( clk_i ),