From 1e79901de140c000441b76c39a5392a7ee1d223e Mon Sep 17 00:00:00 2001
From: Arjan Bink <Arjan.Bink@silabs.com>
Date: Thu, 8 Oct 2020 09:21:47 -0500
Subject: [PATCH] Fix for issue #58

Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
---
 src/dm_csrs.sv |  3 +--
 src/dm_sba.sv  | 27 ++++++++++++++++++++-------
 2 files changed, 21 insertions(+), 9 deletions(-)

diff --git a/src/dm_csrs.sv b/src/dm_csrs.sv
index 78fd32a..f943537 100644
--- a/src/dm_csrs.sv
+++ b/src/dm_csrs.sv
@@ -520,7 +520,7 @@ module dm_csrs #(
     if (dmcontrol_q.resumereq && resumeack_i) begin
       dmcontrol_d.resumereq = 1'b0;
     end
-    // static values for dcsr
+    // static values for sbcs
     sbcs_d.sbversion            = 3'b1;
     sbcs_d.sbbusy               = sbbusy_i;
     sbcs_d.sbasize              = $bits(sbcs_d.sbasize)'(BusWidth);
@@ -529,7 +529,6 @@ module dm_csrs #(
     sbcs_d.sbaccess32           = logic'(BusWidth == 32'd32);
     sbcs_d.sbaccess16           = 1'b0;
     sbcs_d.sbaccess8            = 1'b0;
-    sbcs_d.sbaccess             = (BusWidth == 32'd64) ? 3'd3 : 3'd2;
   end
 
   // output multiplexer
diff --git a/src/dm_sba.sv b/src/dm_sba.sv
index b78fb31..d96af35 100644
--- a/src/dm_sba.sv
+++ b/src/dm_sba.sv
@@ -102,7 +102,7 @@ module dm_sba #(
     unique case (state_q)
       Idle: begin
         // debugger requested a read
-        if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;
+        if (sbaddress_write_valid_i && sbreadonaddr_i) state_d = Read;
         // debugger requested a write
         if (sbdata_write_valid_i) state_d = Write;
         // perform another read
@@ -141,12 +141,25 @@ module dm_sba #(
       default: state_d = Idle; // catch parasitic state
     endcase
 
-    // handle error case
-    if (sbaccess_i > 3 && state_q != Idle) begin
-      req             = 1'b0;
-      state_d         = Idle;
-      sberror_valid_o = 1'b1;
-      sberror_o       = 3'd3;
+    // check for SBA configuration errors at start of transaction
+    if (state_q != Idle) begin
+      // handle unsupported sbaccess value error case (currently only supporting full bus width transfers)
+      if (!(((sbaccess_i == 3'd2) && (BusWidth == 32'd32)) || ((sbaccess_i == 3'd3) && (BusWidth == 32'd64)))) begin
+        req             = 1'b0;
+        state_d         = Idle;
+        sberror_valid_o = 1'b1;
+        sberror_o       = 3'd4;
+      end else begin
+        // handle misalignment case
+        if (((sbaccess_i == 3'd1) && (sbaddress_i[0:0] != 1'b0)) ||
+            ((sbaccess_i == 3'd2) && (sbaddress_i[1:0] != 2'b0)) ||
+            ((sbaccess_i == 3'd3) && (sbaddress_i[2:0] != 3'b0))) begin
+          req             = 1'b0;
+          state_d         = Idle;
+          sberror_valid_o = 1'b1;
+          sberror_o       = 3'd3;
+        end
+      end
     end
     // further error handling should go here ...
   end