Problem
spar's latency.rs traces thread chains end-to-end but uses a single scalar Bus_Properties::Latency per network hop — a placeholder, not a real bound. Real embedded systems alternate WCET (compute stages) and WCTT (communication stages):
```
sensor → [WCTT₁] → ECU_A → [WCET_a] → ECU_A → [WCTT₂] → ECU_B → [WCET_b] → … → actuator
```
Without per-stream WCTT, every network hop is undercounted at the latency analysis layer. This produces optimistic end-to-end bounds that miss real deadline misses on contended networks.
WCTT is not a TSN-only advanced feature — it's foundational for honest end-to-end timing. Classical Ethernet, CAN, FlexRay all need it. TSN-specific features (TAS gate-control, CBS, frame preemption) are upgrades within the WCTT engine, not separate concerns.
Today:
- `bus_bandwidth.rs` — summed throughput per bus, no per-stream WCTT
- `latency.rs` — thread chains with scalar bus latency
- AADL spec has no first-class switch component
- IEEE 802.1Qbv (TAS), 802.1Qbu (preemption), 802.1Qcr — no AADL vocabulary
Customer driver: vehicle E/E architectures gateway → switches → Cortex-M0 ECUs. Sensor-to-actuator latency claims must compose WCTT and WCET correctly.
Acceptance — phased
Phase 1 (v0.8.0): WCTT engine for FIFO+priority networks
Phase 2 (v0.8.x or v0.9.0): TSN extensions
Research output
PR #152 — comprehensive research and design proposal (1264 lines, 50 citations). Recommended:
- Option C for switch modeling (`bus impl` + `Spar_Network::Switch_Type`)
- spar's positioning: complementary primary, competitive stretch goal (mirrors RocqStat decision)
- ~7-week scope across 6 commits
A follow-up RTaW-Pegase deep-dive + extended commercial-tool survey is in progress to refine acceptance criteria further.
Notes
- Network Calculus computations can be expensive on large graphs — performance budget needed (target: ≤30s for 100-ECU topologies)
- `Stream_ID` semantics across redundant paths (802.1CB FRER) deferred beyond Phase 2
- Lean foundations for min-plus algebra are bigger than RTA — full proofs target v1.0.0
- ~7-week scope for Phase 1, comparable to Track A
Problem
spar's
latency.rstraces thread chains end-to-end but uses a single scalarBus_Properties::Latencyper network hop — a placeholder, not a real bound. Real embedded systems alternate WCET (compute stages) and WCTT (communication stages):```
sensor → [WCTT₁] → ECU_A → [WCET_a] → ECU_A → [WCTT₂] → ECU_B → [WCET_b] → … → actuator
```
Without per-stream WCTT, every network hop is undercounted at the latency analysis layer. This produces optimistic end-to-end bounds that miss real deadline misses on contended networks.
WCTT is not a TSN-only advanced feature — it's foundational for honest end-to-end timing. Classical Ethernet, CAN, FlexRay all need it. TSN-specific features (TAS gate-control, CBS, frame preemption) are upgrades within the WCTT engine, not separate concerns.
Today:
Customer driver: vehicle E/E architectures gateway → switches → Cortex-M0 ECUs. Sensor-to-actuator latency claims must compose WCTT and WCET correctly.
Acceptance — phased
Phase 1 (v0.8.0): WCTT engine for FIFO+priority networks
Phase 2 (v0.8.x or v0.9.0): TSN extensions
Research output
PR #152 — comprehensive research and design proposal (1264 lines, 50 citations). Recommended:
A follow-up RTaW-Pegase deep-dive + extended commercial-tool survey is in progress to refine acceptance criteria further.
Notes