esp32: Update with master up to release 1.10.1.b1

Author: Daniel Campora

esp32/Makefile

@@ -48,15 +48,12 @@ CFLAGS_XTENSA = -DESP_PLATFORM -Wpointer-arith -Wall -Werror=all -Wno-error=unus
                 -mlongcalls -Wall -ffunction-sections -fdata-sections -fno-common \
                 -Wno-sign-compare -Wno-old-style-declaration -fstrict-volatile-bitfields \
                 -Wno-error=deprecated-declarations -Wno-unused-parameter -DWITH_POSIX \
-                -mfix-esp32-psram-cache-issue
 
-ifeq ($(TARGET), app)
 CFLAGS_XTENSA_OPT = -Os
-else
-CFLAGS_XTENSA_OPT = -Og
-endif
+CFLAGS_XTENSA_PSRAM = -mfix-esp32-psram-cache-issue
 
-CFLAGS = $(CFLAGS_XTENSA) $(CFLAGS_XTENSA_OPT) -nostdlib -std=gnu99 -g3 -ggdb -fstrict-volatile-bitfields -Iboards/$(BOARD)
+CFLAGS = $(CFLAGS_XTENSA) $(CFLAGS_XTENSA_PSRAM) $(CFLAGS_XTENSA_OPT) -nostdlib -std=gnu99 -g3 -ggdb -fstrict-volatile-bitfields -Iboards/$(BOARD)
+CFLAGS_SIGFOX = $(CFLAGS_XTENSA) -O2 -nostdlib -std=gnu99 -g3 -ggdb -fstrict-volatile-bitfields -Iboards/$(BOARD)
 
 LDFLAGS = -nostdlib -Wl,-Map=$(@:.elf=.map) -Wl,--no-check-sections -u call_user_start_cpu0
 LDFLAGS += -Wl,-static -Wl,--undefined=uxTopUsedPriority -Wl,--gc-sections

esp32/application.mk

@@ -273,6 +273,7 @@ APP_LDFLAGS += $(LDFLAGS) -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T
 
 # add the application specific CFLAGS
 CFLAGS += $(APP_INC) -DMICROPY_NLR_SETJMP=1 -D$(LORA_BAND) -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H -DESP_PLATFORM
+CFLAGS_SIGFOX += $(APP_INC) -DMICROPY_NLR_SETJMP=1 -D$(LORA_BAND) -DMBEDTLS_CONFIG_FILE='"mbedtls/esp_config.h"' -DHAVE_CONFIG_H -DESP_PLATFORM
 
 # add the application archive, this order is very important
 APP_LIBS = -Wl,--start-group $(LIBS) $(BUILD)/application.a -Wl,--end-group -Wl,-EL
@@ -281,16 +282,19 @@ BOOT_LIBS = -Wl,--start-group $(B_LIBS) $(BUILD)/bootloader/bootloader.a -Wl,--e
 
 # debug / optimization options
 ifeq ($(BTYPE), debug)
-    CFLAGS += -DDEBUG_B -DNDEBUG -DPYCOM_DEBUG
+    CFLAGS += -DDEBUG
+    CFLAGS_SIGFOX += -DDEBUG
 else
     ifeq ($(BTYPE), release)
         CFLAGS += -DNDEBUG
+        CFLAGS_SIGFOX += -DNDEBUG
     else
         $(error Invalid BTYPE specified)
     endif
 endif
 
 $(BUILD)/bootloader/%.o: CFLAGS += -D BOOTLOADER_BUILD=1
+$(BUILD)/bootloader/%.o: CFLAGS_SIGFOX += -D BOOTLOADER_BUILD=1
 
 BOOT_OFFSET = 0x1000
 PART_OFFSET = 0x8000
@@ -306,9 +310,10 @@ ifeq ($(BOARD), LOPY)
 else
     ifeq ($(BOARD), SIPY)
         APP_BIN = $(BUILD)/sipy.bin
-        $(BUILD)/sigfox/radio.o: CFLAGS += -O2
-        $(BUILD)/sigfox/timer.o: CFLAGS += -O2
-        $(BUILD)/sigfox/targets/%.o: CFLAGS += -O2
+        $(BUILD)/sigfox/radio.o: CFLAGS = $(CFLAGS_SIGFOX)
+        $(BUILD)/sigfox/timer.o: CFLAGS = $(CFLAGS_SIGFOX)
+        $(BUILD)/sigfox/transmission.o: CFLAGS = $(CFLAGS_SIGFOX)
+        $(BUILD)/sigfox/targets/%.o: CFLAGS = $(CFLAGS_SIGFOX)
     else
         APP_BIN = $(BUILD)/wipy.bin
     endif
@@ -320,8 +325,8 @@ PART_BIN = $(BUILD)/lib/partitions.bin
 ESPPORT ?= /dev/ttyUSB0
 ESPBAUD ?= 921600
 
-FLASH_SIZE = 4MB
-ESPFLASHFREQ = 40m
+FLASH_SIZE = detect
+ESPFLASHFREQ = 80m
 ESPFLASHMODE = dio
 
 PIC_TOOL = $(PYTHON) tools/pypic.py --port $(ESPPORT)

esp32/bootloader/bootloader.c

@@ -23,6 +23,7 @@
 #include "esp_system.h"
 
 #include "rom/cache.h"
+#include "rom/efuse.h"
 #include "rom/ets_sys.h"
 #include "rom/spi_flash.h"
 #include "rom/crc.h"
@@ -84,6 +85,8 @@ static void set_cache_and_start_app(uint32_t drom_addr,
     uint32_t irom_size,
     uint32_t entry_addr);
 static void update_flash_config(const esp_image_header_t* pfhdr);
+static void vddsdio_configure();
+static void flash_gpio_configure();
 static void clock_configure(void);
 static void uart_console_configure(void);
 static void wdt_reset_check(void);
@@ -106,13 +109,15 @@ void call_start_cpu0()
     cpu_configure_region_protection();
 
     /* Sanity check that static RAM is after the stack */
+#ifndef NDEBUG
     {
         int *sp = get_sp();
         assert(&_bss_start <= &_bss_end);
         assert(&_data_start <= &_data_end);
         assert(sp < &_bss_start);
         assert(sp < &_data_start);
     }
+#endif
 
     //Clear bss
     memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
@@ -272,13 +277,10 @@ static IRAM_ATTR void calculate_signature (uint8_t *signature) {
     MD5Init(&md5_context);
     ESP_LOGI(TAG, "md5 init sig");
     while (total_len < 0x7000) {
-        // Cache_Read_Disable(0);
         if (ESP_ROM_SPIFLASH_RESULT_OK != bootloader_flash_read(0x1000 + total_len, (void *)bootloader_buf, SPI_SEC_SIZE, false)) {
             ESP_LOGE(TAG, SPI_ERROR_LOG);
-            // Cache_Read_Enable(0);
             return;
         }
-        // Cache_Read_Enable(0);
         total_len += SPI_SEC_SIZE;
         MD5Update(&md5_context, (void *)bootloader_buf, SPI_SEC_SIZE);
     }
@@ -372,16 +374,9 @@ static bool get_image_from_partition(const esp_partition_pos_t *partition, esp_i
 
 static bool find_active_image(bootloader_state_t *bs, esp_partition_pos_t *partition)
 {
-    uint32_t chip_revision = 0;
     boot_info_t *boot_info;
     boot_info_t _boot_info;
 
-    // TODO
-    // uint32_t reg = REG_READ(EFUSE_BLK0_RDATA3_REG);
-    // if ((reg & EFUSE_RD_CHIP_VER_REV1_M) != 0) {
-    //     chip_revision = 1;
-    // }
-
     if (bs->ota_info.size < 2 * sizeof(esp_ota_select_entry_t)) {
         ESP_LOGE(TAG, "ERROR: ota_info partition size %d is too small (minimum %d bytes)", bs->ota_info.size, sizeof(esp_ota_select_entry_t));
         return false;
@@ -440,10 +435,8 @@ static bool find_active_image(bootloader_state_t *bs, esp_partition_pos_t *parti
 
         // do we have a new image that needs to be verified?
         if ((boot_info->ActiveImg != IMG_ACT_FACTORY) && (boot_info->Status == IMG_STATUS_CHECK)) {
-            if (chip_revision == 0) {
-                if (boot_info->ActiveImg == IMG_ACT_UPDATE2) {
-                    boot_info->ActiveImg = IMG_ACT_FACTORY;    // we only have space for 1 OTAA image
-                }
+            if (boot_info->ActiveImg == IMG_ACT_UPDATE2) {
+                boot_info->ActiveImg = IMG_ACT_FACTORY;    // we only have space for 1 OTAA image
             }
             if (!bootloader_verify(&bs->image[boot_info->ActiveImg], boot_info->size)) {
                 // switch to the previous image
@@ -494,15 +487,17 @@ static bool find_active_image(bootloader_state_t *bs, esp_partition_pos_t *parti
 
 static void bootloader_main()
 {
+    vddsdio_configure();
+    flash_gpio_configure();
     clock_configure();
     uart_console_configure();
     wdt_reset_check();
     ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader");
 
-    esp_image_header_t fhdr;
-    bootloader_state_t bootloader_state;
-    esp_partition_pos_t partition;
-    esp_image_metadata_t image_data;
+    esp_image_header_t fhdr __attribute__((aligned (4)));
+    bootloader_state_t bootloader_state __attribute__((aligned (4)));
+    esp_partition_pos_t partition __attribute__((aligned (4)));
+    esp_image_metadata_t image_data __attribute__((aligned (4)));
 
     memset(&bootloader_state, 0, sizeof(bootloader_state));
     ets_set_appcpu_boot_addr(0);
@@ -755,6 +750,105 @@ static void print_flash_info(const esp_image_header_t* phdr)
 }
 
 
+static void vddsdio_configure()
+{
+#if CONFIG_BOOTLOADER_VDDSDIO_BOOST
+    rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
+    if (cfg.tieh == 0) {    // 1.8V is used
+        cfg.drefh = 3;
+        cfg.drefm = 3;
+        cfg.drefl = 3;
+        cfg.force = 1;
+        cfg.enable = 1;
+        rtc_vddsdio_set_config(cfg);
+        ets_delay_us(10); // wait for regulator to become stable
+    }
+#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
+}
+
+
+#define FLASH_CLK_IO      6
+#define FLASH_CS_IO       11
+#define FLASH_SPIQ_IO     7
+#define FLASH_SPID_IO     8
+#define FLASH_SPIWP_IO    10
+#define FLASH_SPIHD_IO    9
+#define FLASH_IO_MATRIX_DUMMY_40M   1
+#define FLASH_IO_MATRIX_DUMMY_80M   2
+static void IRAM_ATTR flash_gpio_configure()
+{
+    int spi_cache_dummy = 0;
+    int drv = 2;
+#if CONFIG_FLASHMODE_QIO
+    spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;   //qio 3
+#elif CONFIG_FLASHMODE_QOUT
+    spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;  //qout 7
+#elif CONFIG_FLASHMODE_DIO
+    spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;   //dio 3
+#elif CONFIG_FLASHMODE_DOUT
+    spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;  //dout 7
+#endif
+    /* dummy_len_plus values defined in ROM for SPI flash configuration */
+    extern uint8_t g_rom_spiflash_dummy_len_plus[];
+#if CONFIG_ESPTOOLPY_FLASHFREQ_40M
+    g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
+    g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
+    SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
+#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
+    g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
+    g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
+    SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S);  //DUMMY
+    drv = 3;
+#endif
+
+    uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
+    uint32_t pkg_ver = chip_ver & 0x7;
+
+    if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
+        // For ESP32D2WD the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32D2WD");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
+        // For ESP32PICOD2 the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32PICOD2");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
+        // For ESP32PICOD4 the SPI pins are already configured
+        ESP_LOGI(TAG, "Detected ESP32PICOD4");
+        //flash clock signal should come from IO MUX.
+        PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+        SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+    } else {
+        ESP_LOGI(TAG, "Detected ESP32");
+        const uint32_t spiconfig = ets_efuse_get_spiconfig();
+        if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
+            gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
+            gpio_matrix_out(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPID_IO, SPID_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0);
+            gpio_matrix_out(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
+            gpio_matrix_in(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0);
+            //select pin function gpio
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
+            // flash clock signal should come from IO MUX.
+            // set drive ability for clock
+            PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
+            SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
+        }
+    }
+}
+
 static void clock_configure(void)
 {
     /* Set CPU to 80MHz. Keep other clocks unmodified. */

esp32/bootloader/lib/libbootloader_support.a

@@ -145,7 +145,7 @@ DRESULT disk_ioctl (
         case CTRL_SYNC:
             return sflash_disk_flush();
         case GET_SECTOR_COUNT:
-            *((DWORD*)buff) = SFLASH_FS_SECTOR_COUNT;
+            *((DWORD*)buff) = sflash_get_sector_count();
             return RES_OK;
         case GET_SECTOR_SIZE:
             *((DWORD*)buff) = SFLASH_FS_SECTOR_SIZE;

esp32/bootloader/lib/liblog.a

@@ -18,6 +18,9 @@ static bool sflash_cache_is_dirty;
 static uint32_t sflash_prev_block_addr;
 static bool sflash_init_done = false;
 
+static uint32_t sflash_start_address;
+static uint32_t sflash_fs_sector_count;
+
 
 static bool sflash_write (void) {
     // erase the block first
@@ -30,6 +33,13 @@ static bool sflash_write (void) {
 
 DRESULT sflash_disk_init (void) {
     if (!sflash_init_done) {
+        if (esp_get_revision() > 0) {
+            sflash_start_address = SFLASH_START_ADDR_8MB;
+            sflash_fs_sector_count = SFLASH_FS_SECTOR_COUNT_8MB;
+        } else {
+            sflash_start_address = SFLASH_START_ADDR_4MB;
+            sflash_fs_sector_count = SFLASH_FS_SECTOR_COUNT_4MB;
+        }
         sflash_block_cache = (uint8_t *)heap_caps_malloc(SFLASH_BLOCK_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
         sflash_prev_block_addr = UINT32_MAX;
         sflash_cache_is_dirty = false;
@@ -48,7 +58,7 @@ DRESULT sflash_disk_status(void) {
 DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count) {
     uint32_t secindex;
 
-    if ((sector + count > SFLASH_FS_SECTOR_COUNT) || !count) {
+    if ((sector + count > sflash_fs_sector_count) || !count) {
         // TODO sl_LockObjLock (&flash_LockObj, SL_OS_WAIT_FOREVER);
         sflash_disk_flush();
         // TODO sl_LockObjUnlock (&flash_LockObj);
@@ -58,7 +68,7 @@ DRESULT sflash_disk_read(BYTE *buff, DWORD sector, UINT count) {
     // TODO sl_LockObjLock (&flash_LockObj, SL_OS_WAIT_FOREVER);
     for (int index = 0; index < count; index++) {
         secindex = (sector + index) % SFLASH_SECTORS_PER_BLOCK;
-        uint32_t sflash_block_addr = SFLASH_START_ADDR + (((sector + index) / SFLASH_SECTORS_PER_BLOCK) * SFLASH_BLOCK_SIZE);
+        uint32_t sflash_block_addr = sflash_start_address + (((sector + index) / SFLASH_SECTORS_PER_BLOCK) * SFLASH_BLOCK_SIZE);
         // Check if it's a different block than last time
         if (sflash_prev_block_addr != sflash_block_addr) {
             if (sflash_disk_flush() != RES_OK) {
@@ -84,7 +94,7 @@ DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count) {
     uint32_t secindex;
     uint32_t index = 0;
 
-    if ((sector + count > SFLASH_FS_SECTOR_COUNT) || !count) {
+    if ((sector + count > sflash_fs_sector_count) || !count) {
         // TODO sl_LockObjLock (&flash_LockObj, SL_OS_WAIT_FOREVER);
         sflash_disk_flush();
         // TODO sl_LockObjUnlock (&flash_LockObj);
@@ -94,7 +104,7 @@ DRESULT sflash_disk_write(const BYTE *buff, DWORD sector, UINT count) {
     // TODO sl_LockObjLock (&flash_LockObj, SL_OS_WAIT_FOREVER);
     do {
         secindex = (sector + index) % SFLASH_SECTORS_PER_BLOCK;
-        uint32_t sflash_block_addr = SFLASH_START_ADDR + (((sector + index) / SFLASH_SECTORS_PER_BLOCK) * SFLASH_BLOCK_SIZE);
+        uint32_t sflash_block_addr = sflash_start_address + (((sector + index) / SFLASH_SECTORS_PER_BLOCK) * SFLASH_BLOCK_SIZE);
         // Check if it's a different block than last time
         if (sflash_prev_block_addr != sflash_block_addr) {
             if (sflash_disk_flush() != RES_OK) {
@@ -127,3 +137,7 @@ DRESULT sflash_disk_flush (void) {
     }
     return RES_OK;
 }
+
+uint32_t sflash_get_sector_count(void) {
+    return sflash_fs_sector_count;
+}