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iHP0p2: updated files for iHP process
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‎.github/workflows/gds.yaml

Lines changed: 75 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,28 +14,85 @@ jobs:
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submodules: recursive
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- name: Build GDS
17-
uses: TinyTapeout/tt-gds-action@tt09
18-
with:
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flow: openlane2
17+
uses: TinyTapeout/tt-gds-action/orfs@tt09
2018

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precheck:
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needs: gds
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runs-on: ubuntu-24.04
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steps:
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- name: Run Tiny Tapeout Precheck
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uses: TinyTapeout/tt-gds-action/precheck@tt09
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#precheck:
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# needs: gds
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# runs-on: ubuntu-24.04
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# steps:
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# - name: Run Tiny Tapeout Precheck
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# uses: TinyTapeout/tt-gds-action/precheck@tt09
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gl_test:
29-
needs: gds
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runs-on: ubuntu-24.04
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steps:
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- name: checkout repo
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uses: actions/checkout@v4
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with:
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submodules: recursive
27+
needs: gds
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runs-on: ubuntu-24.04
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env:
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PDK_ROOT: ${{ github.workspace }}/IHP-Open-PDK
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TEST_DIR: ${{ github.workspace }}/test
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steps:
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- name: checkout repo
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uses: actions/checkout@v4
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with:
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submodules: recursive
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- name: Download GDS artifact
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uses: actions/download-artifact@v4
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with:
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name: tt_submission
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- name: install PDK
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uses: actions/checkout@v4
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with:
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repository: tinytapeout/IHP-Open-PDK
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ref: tt
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path: IHP-Open-PDK
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- name: Setup python
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uses: actions/setup-python@v5
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with:
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python-version: '3.11'
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- name: Install Python packages
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shell: bash
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run: pip install -r test/requirements.txt
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- name: ccache
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uses: hendrikmuhs/ccache-action@v1.2
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- name: Install iverilog
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shell: bash
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run: |
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wget https://github.com/htfab/iverilog/releases/download/13.0-git-d8c3c51/iverilog_13.0-git-d8c3c51a-1_amd64.deb
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sudo apt-get update -y
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sudo apt-get install -y ./iverilog_13.0-git-d8c3c51a-1_amd64.deb
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- name: Run tests
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shell: bash
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run: |
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cp tt_submission/*.v "$TEST_DIR/gate_level_netlist.v"
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cd "$TEST_DIR"
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rm -f tb.vcd results.xml
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make clean
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GATES=yes make
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# `make` will return success even if the tests fail, so check for failure in results.xml
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test -f results.xml
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! grep failure results.xml
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- name: Upload VCD
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if: always()
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uses: actions/upload-artifact@v4
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with:
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name: gatelevel_test_vcd
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path: |
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${{ env.TEST_DIR }}/tb.vcd
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${{ env.TEST_DIR }}/results.xml
3690
37-
- name: GL test
38-
uses: TinyTapeout/tt-gds-action/gl_test@tt09
91+
- name: Test Summary
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if: always()
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uses: test-summary/action@v2.3
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with:
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paths: ${{ env.TEST_DIR }}/results.xml
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viewer:
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needs: gds

‎info.yaml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ project:
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clock_hz: 4000000 # Clock frequency in Hz
99

1010
# How many tiles your design occupies? A single tile is about 167x108 uM.
11-
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
11+
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 6x2
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# Your top module name must start with "tt_um_". Make it unique by including your github username:
1414
top_module: "tt_um_rejunity_sn76489"

‎src/config.json

Lines changed: 12 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -11,74 +11,25 @@
1111

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"//": "Here are some of the variables you may want to change:",
1313

14-
"//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
15-
"//": "Users have reported that values up to 80 worked well for them.",
16-
"PL_TARGET_DENSITY_PCT": 80,
14+
"PLACE_DENSITY": 0.8,
15+
"TNS_END_PERCENT": 100,
1716

18-
"//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
19-
"//": "The value is in nanoseconds, so 20ns == 50MHz.",
20-
"CLOCK_PERIOD": 20,
17+
"//": "Change the clock period here. 20000 ps = 20 ns corresponds to 50 MHz",
18+
"ABC_CLOCK_PERIOD_IN_PS": 20000,
2119

22-
"//": "Hold slack margin - Increase them in case you are getting hold violations.",
23-
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
24-
"GRT_RESIZER_HOLD_SLACK_MARGIN": 0.05,
20+
"//": "Increase this if you are getting 'Synthesized memory size exceeds maximum allowed bits' error:",
21+
"SYNTH_MEMORY_MAX_BITS": 4096,
2522

26-
"//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
27-
"RUN_LINTER": 1,
28-
"LINTER_INCLUDE_PDK_MODELS": 1,
23+
"//": "Setting to 1 may help decrease design area utilization / speed up routing:",
24+
"ABC_AREA": 0,
2925

30-
"//": "If you need a custom clock configuration, read the following documentation first:",
31-
"//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
32-
"CLOCK_PORT": "clk",
33-
34-
"//": "Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html",
26+
"//": "Configuration docs: https://openroad-flow-scripts.readthedocs.io/en/latest/user/FlowVariables.html",
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3628
"//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
3729
"//": "!!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!",
3830
"//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
3931

40-
"//": "Save some time",
41-
"RUN_KLAYOUT_XOR": 0,
42-
"RUN_KLAYOUT_DRC": 0,
43-
44-
"//": "Don't put clock buffers on the outputs",
45-
"DESIGN_REPAIR_BUFFER_OUTPUT_PORTS": 0,
46-
47-
"//": "Reduce wasted space",
48-
"TOP_MARGIN_MULT": 1,
49-
"BOTTOM_MARGIN_MULT": 1,
50-
"LEFT_MARGIN_MULT": 6,
51-
"RIGHT_MARGIN_MULT": 6,
52-
53-
"//": "Absolute die size",
54-
"FP_SIZING": "absolute",
55-
56-
"GRT_ALLOW_CONGESTION": 1,
57-
58-
"FP_IO_HLENGTH": 2,
59-
"FP_IO_VLENGTH": 2,
60-
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"FP_PDN_VPITCH": 38.87,
62-
63-
"//": "Use alternative efabless decap cells to solve LI density issue",
64-
"DECAP_CELL": [
65-
"sky130_fd_sc_hd__decap_3",
66-
"sky130_fd_sc_hd__decap_4",
67-
"sky130_fd_sc_hd__decap_6",
68-
"sky130_fd_sc_hd__decap_8",
69-
"sky130_ef_sc_hd__decap_12"
70-
],
71-
72-
"//": "Clock",
73-
"RUN_CTS": 1,
74-
75-
"//": "Don't use power rings or met5 layer",
76-
"FP_PDN_MULTILAYER": 0,
77-
"RT_MAX_LAYER": "met4",
78-
79-
"//": "MAGIC_DEF_LABELS may cause issues with LVS",
80-
"MAGIC_DEF_LABELS": 0,
81-
82-
"//": "Only export pin area in LEF (without any connected nets)",
83-
"MAGIC_WRITE_LEF_PINONLY": 1
32+
"//": "Power nets for IR drop analysis",
33+
"PWR_NETS_VOLTAGES": "{VPWR 1.2}",
34+
"GND_NETS_VOLTAGES": "{VGND 0.0}"
8435
}

‎test/Makefile

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,11 +21,9 @@ else
2121
SIM_BUILD = sim_build/gl
2222
COMPILE_ARGS += -DGL_TEST
2323
COMPILE_ARGS += -DFUNCTIONAL
24-
COMPILE_ARGS += -DUSE_POWER_PINS
2524
COMPILE_ARGS += -DSIM
26-
COMPILE_ARGS += -DUNIT_DELAY=\#1
27-
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
28-
VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
25+
VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_io/verilog/sg13g2_io.v
26+
VERILOG_SOURCES += $(PDK_ROOT)/ihp-sg13g2/libs.ref/sg13g2_stdcell/verilog/sg13g2_stdcell.v
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3028
# this gets copied in by the GDS action workflow
3129
VERILOG_SOURCES += $(PWD)/gate_level_netlist.v

‎test/tb.v

Lines changed: 28 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1,51 +1,37 @@
11
`default_nettype none
2-
`timescale 1ns/1ps
2+
`timescale 1ns / 1ps
33

4-
/*
5-
this testbench just instantiates the module and makes some convenient wires
6-
that can be driven / tested by the cocotb test.py
4+
/* This testbench just instantiates the module and makes some convenient wires
5+
that can be driven / tested by the cocotb test.py.
76
*/
8-
9-
// testbench is controlled by test.py
107
module tb ();
118

12-
// this part dumps the trace to a vcd file that can be viewed with GTKWave
13-
initial begin
14-
$dumpfile ("tb.vcd");
15-
$dumpvars (0, tb);
16-
#1;
17-
end
18-
19-
// wire up the inputs and outputs
20-
wire [7:0] ui_in;
21-
wire [7:0] uo_out;
22-
wire [7:0] uio_in;
23-
wire [7:0] uio_out;
24-
wire [7:0] uio_oe;
25-
wire clk;
26-
wire rst_n;
27-
wire ena;
28-
`ifdef GL_TEST
29-
wire VPWR = 1'b1;
30-
wire VGND = 1'b0;
31-
`endif
9+
// Dump the signals to a VCD file. You can view it with gtkwave.
10+
initial begin
11+
$dumpfile("tb.vcd");
12+
$dumpvars(0, tb);
13+
#1;
14+
end
3215

16+
// Wire up the inputs and outputs:
17+
reg clk;
18+
reg rst_n;
19+
reg ena;
20+
reg [7:0] ui_in;
21+
reg [7:0] uio_in;
22+
wire [7:0] uo_out;
23+
wire [7:0] uio_out;
24+
wire [7:0] uio_oe;
3325

34-
tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut
35-
(
36-
// include power ports for the Gate Level test
37-
`ifdef GL_TEST
38-
.VPWR(VPWR),
39-
.VGND(VGND),
40-
`endif
41-
.ui_in (ui_in), // Dedicated inputs
42-
.uo_out (uo_out), // Dedicated outputs
43-
.uio_in (uio_in), // IOs: Input path
44-
.uio_out (uio_out), // IOs: Output path
45-
.uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output)
46-
.ena (ena), // enable - goes high when design is selected
47-
.clk (clk), // clock
48-
.rst_n (rst_n) // not reset
49-
);
26+
tt_um_rejunity_sn76489 tt_um_rejunity_sn76489_uut (
27+
.ui_in (ui_in), // Dedicated inputs
28+
.uo_out (uo_out), // Dedicated outputs
29+
.uio_in (uio_in), // IOs: Input path
30+
.uio_out(uio_out), // IOs: Output path
31+
.uio_oe (uio_oe), // IOs: Enable path (active high: 0=input, 1=output)
32+
.ena (ena), // enable - goes high when design is selected
33+
.clk (clk), // clock
34+
.rst_n (rst_n) // not reset
35+
);
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5137
endmodule

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