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Fix tests.
1 parent 3d9fafa commit 1ef1ab2

23 files changed

+1554
-1562
lines changed

compiler/rustc_codegen_llvm/src/base.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ pub(crate) fn compile_codegen_unit(
8888
cx.codegen_unit.items_in_deterministic_order(cx.tcx)
8989
} else {
9090
// The `items` has a deterministic order, so we can use it directly.
91-
cx.codegen_unit.items().iter().cloned().collect()
91+
cx.codegen_unit.items().iter().map(|(item, data)| (*item, *data)).collect()
9292
};
9393
for &(mono_item, data) in &mono_items {
9494
mono_item.predefine::<Builder<'_, '_, '_>>(

compiler/rustc_middle/src/mir/mono.rs

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,6 @@ use rustc_data_structures::unord::UnordMap;
1212
use rustc_hashes::Hash128;
1313
use rustc_hir::ItemId;
1414
use rustc_hir::def_id::{CrateNum, DefId, DefIdSet, LOCAL_CRATE};
15-
use rustc_index::Idx;
1615
use rustc_macros::{HashStable, TyDecodable, TyEncodable};
1716
use rustc_query_system::ich::StableHashingContext;
1817
use rustc_session::config::OptLevel;
@@ -540,7 +539,7 @@ impl<'tcx> CodegenUnit<'tcx> {
540539
) -> Option<T> {
541540
match item {
542541
MonoItem::Fn(ref instance) => match instance.def {
543-
InstanceKind::Item(def) => def.as_local().map(op),
542+
InstanceKind::Item(def) => def.as_local().map(|_| op(def)),
544543
InstanceKind::VTableShim(..)
545544
| InstanceKind::ReifyShim(..)
546545
| InstanceKind::Intrinsic(..)
@@ -556,14 +555,14 @@ impl<'tcx> CodegenUnit<'tcx> {
556555
| InstanceKind::FutureDropPollShim(..)
557556
| InstanceKind::AsyncDropGlueCtorShim(..) => None,
558557
},
559-
MonoItem::Static(def_id) => def_id.as_local().map(op),
560-
MonoItem::GlobalAsm(item_id) => Some(op(item_id.owner_id.def_id)),
558+
MonoItem::Static(def_id) => def_id.as_local().map(|_| op(def_id)),
559+
MonoItem::GlobalAsm(item_id) => Some(op(item_id.owner_id.def_id.to_def_id())),
561560
}
562561
}
563562
fn item_sort_key<'tcx>(tcx: TyCtxt<'tcx>, item: MonoItem<'tcx>) -> ItemSortKey<'tcx> {
564563
ItemSortKey(
565564
local_item_query(item, |def_id| tcx.def_span(def_id)),
566-
local_item_query(item, |def_id| tcx.def_path(id).to_string_no_crate_verbose()),
565+
local_item_query(item, |def_id| tcx.def_path(def_id).to_string_no_crate_verbose()),
567566
item.symbol_name(tcx),
568567
)
569568
}

src/tools/compiletest/src/runtest.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1694,10 +1694,10 @@ impl<'test> TestCx<'test> {
16941694
}
16951695
TestMode::Assembly | TestMode::Codegen => {
16961696
rustc.arg("-Cdebug-assertions=no");
1697-
// For assembly and codegen tests, we want to use the same order
1698-
// of the items of a codegen unit as the source order, so that
1697+
// For assembly and codegen tests, we want to use the same order
1698+
// of the items of a codegen unit as the source order,so that
16991699
// we can compare the output with the source code through filecheck.
1700-
rustc.arg("-Zcodegen-source-order")
1700+
rustc.arg("-Zcodegen-source-order");
17011701
}
17021702
TestMode::Crashes => {
17031703
set_mir_dump_dir(&mut rustc);

tests/assembly-llvm/asm/aarch64-modifiers.rs

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -55,35 +55,17 @@ check!(vreg vreg "add {0}.4s, {0}.4s, {0}.4s");
5555
// CHECK: //NO_APP
5656
check!(vreg_b vreg "ldr {:b}, [x0]");
5757

58-
// CHECK-LABEL: vreg_h:
59-
// CHECK: //APP
60-
// CHECK: ldr h0, [x0]
61-
// CHECK: //NO_APP
62-
check!(vreg_h vreg "ldr {:h}, [x0]");
63-
64-
// CHECK-LABEL: vreg_s:
65-
// CHECK: //APP
66-
// CHECK: ldr s0, [x0]
67-
// CHECK: //NO_APP
68-
check!(vreg_s vreg "ldr {:s}, [x0]");
69-
7058
// CHECK-LABEL: vreg_d:
7159
// CHECK: //APP
7260
// CHECK: ldr d0, [x0]
7361
// CHECK: //NO_APP
7462
check!(vreg_d vreg "ldr {:d}, [x0]");
7563

76-
// CHECK-LABEL: vreg_q:
77-
// CHECK: //APP
78-
// CHECK: ldr q0, [x0]
79-
// CHECK: //NO_APP
80-
check!(vreg_q vreg "ldr {:q}, [x0]");
81-
82-
// CHECK-LABEL: vreg_v:
64+
// CHECK-LABEL: vreg_h:
8365
// CHECK: //APP
84-
// CHECK: add v0.4s, v0.4s, v0.4s
66+
// CHECK: ldr h0, [x0]
8567
// CHECK: //NO_APP
86-
check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
68+
check!(vreg_h vreg "ldr {:h}, [x0]");
8769

8870
// CHECK-LABEL: vreg_low16:
8971
// CHECK: //APP
@@ -97,32 +79,50 @@ check!(vreg_low16 vreg_low16 "add {0}.4s, {0}.4s, {0}.4s");
9779
// CHECK: //NO_APP
9880
check!(vreg_low16_b vreg_low16 "ldr {:b}, [x0]");
9981

82+
// CHECK-LABEL: vreg_low16_d:
83+
// CHECK: //APP
84+
// CHECK: ldr d0, [x0]
85+
// CHECK: //NO_APP
86+
check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
87+
10088
// CHECK-LABEL: vreg_low16_h:
10189
// CHECK: //APP
10290
// CHECK: ldr h0, [x0]
10391
// CHECK: //NO_APP
10492
check!(vreg_low16_h vreg_low16 "ldr {:h}, [x0]");
10593

94+
// CHECK-LABEL: vreg_low16_q:
95+
// CHECK: //APP
96+
// CHECK: ldr q0, [x0]
97+
// CHECK: //NO_APP
98+
check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
99+
106100
// CHECK-LABEL: vreg_low16_s:
107101
// CHECK: //APP
108102
// CHECK: ldr s0, [x0]
109103
// CHECK: //NO_APP
110104
check!(vreg_low16_s vreg_low16 "ldr {:s}, [x0]");
111105

112-
// CHECK-LABEL: vreg_low16_d:
106+
// CHECK-LABEL: vreg_low16_v:
113107
// CHECK: //APP
114-
// CHECK: ldr d0, [x0]
108+
// CHECK: add v0.4s, v0.4s, v0.4s
115109
// CHECK: //NO_APP
116-
check!(vreg_low16_d vreg_low16 "ldr {:d}, [x0]");
110+
check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
117111

118-
// CHECK-LABEL: vreg_low16_q:
112+
// CHECK-LABEL: vreg_q:
119113
// CHECK: //APP
120114
// CHECK: ldr q0, [x0]
121115
// CHECK: //NO_APP
122-
check!(vreg_low16_q vreg_low16 "ldr {:q}, [x0]");
116+
check!(vreg_q vreg "ldr {:q}, [x0]");
123117

124-
// CHECK-LABEL: vreg_low16_v:
118+
// CHECK-LABEL: vreg_s:
119+
// CHECK: //APP
120+
// CHECK: ldr s0, [x0]
121+
// CHECK: //NO_APP
122+
check!(vreg_s vreg "ldr {:s}, [x0]");
123+
124+
// CHECK-LABEL: vreg_v:
125125
// CHECK: //APP
126126
// CHECK: add v0.4s, v0.4s, v0.4s
127127
// CHECK: //NO_APP
128-
check!(vreg_low16_v vreg_low16 "add {0:v}.4s, {0:v}.4s, {0:v}.4s");
128+
check!(vreg_v vreg "add {0:v}.4s, {0:v}.4s, {0:v}.4s");

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