From e5466d2f8134000425c80e11a58ce28eccb786b8 Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:22:26 +0800 Subject: [PATCH 1/6] Fix tests/codegen/const-vector.rs test failure on riscv64 --- tests/codegen/const-vector.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/codegen/const-vector.rs b/tests/codegen/const-vector.rs index 42921442e039f..62026012d65c9 100644 --- a/tests/codegen/const-vector.rs +++ b/tests/codegen/const-vector.rs @@ -14,6 +14,7 @@ #![feature(simd_ffi)] #![feature(arm_target_feature)] #![feature(mips_target_feature)] +#![feature(riscv_target_feature)] #![allow(non_camel_case_types)] // Setting up structs that can be used as const vectors @@ -51,6 +52,7 @@ extern "unadjusted" { #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] pub fn do_call() { unsafe { // CHECK: call void @test_i8x2(<2 x i8> From f335927ce8ee4b050477644f53b933ff9cebbbb5 Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:28:29 +0800 Subject: [PATCH 2/6] Fix tests/codegen/enum/enum-aggregate-riscv64.rs test failure on riscv64 --- ...aggregate.rs => enum-aggregate-generic.rs} | 1 + tests/codegen/enum/enum-aggregate-riscv64.rs | 127 ++++++++++++++++++ 2 files changed, 128 insertions(+) rename tests/codegen/enum/{enum-aggregate.rs => enum-aggregate-generic.rs} (99%) create mode 100644 tests/codegen/enum/enum-aggregate-riscv64.rs diff --git a/tests/codegen/enum/enum-aggregate.rs b/tests/codegen/enum/enum-aggregate-generic.rs similarity index 99% rename from tests/codegen/enum/enum-aggregate.rs rename to tests/codegen/enum/enum-aggregate-generic.rs index 0161e5f3fa1a1..773a06fabb4c6 100644 --- a/tests/codegen/enum/enum-aggregate.rs +++ b/tests/codegen/enum/enum-aggregate-generic.rs @@ -1,6 +1,7 @@ //@ compile-flags: -Copt-level=0 -Cno-prepopulate-passes //@ min-llvm-version: 19 //@ only-64bit +//@ ignore-riscv64 #![crate_type = "lib"] diff --git a/tests/codegen/enum/enum-aggregate-riscv64.rs b/tests/codegen/enum/enum-aggregate-riscv64.rs new file mode 100644 index 0000000000000..c388723b59b0e --- /dev/null +++ b/tests/codegen/enum/enum-aggregate-riscv64.rs @@ -0,0 +1,127 @@ +//@ compile-flags: -Copt-level=0 -Cno-prepopulate-passes +//@ min-llvm-version: 19 +//@ only-64bit +//@ only-riscv64 + +#![crate_type = "lib"] + +use std::cmp::Ordering; +use std::num::NonZero; +use std::ptr::NonNull; + +#[no_mangle] +fn make_some_bool(x: bool) -> Option { + // CHECK-LABEL: i8 @make_some_bool(i1 zeroext %x) + // CHECK-NEXT: start: + // CHECK-NEXT: %[[WIDER:.+]] = zext i1 %x to i8 + // CHECK-NEXT: ret i8 %[[WIDER]] + Some(x) +} + +#[no_mangle] +fn make_none_bool() -> Option { + // CHECK-LABEL: i8 @make_none_bool() + // CHECK-NEXT: start: + // CHECK-NEXT: ret i8 2 + None +} + +#[no_mangle] +fn make_some_ordering(x: Ordering) -> Option { + // CHECK-LABEL: i8 @make_some_ordering(i8 signext %x) + // CHECK-NEXT: start: + // CHECK-NEXT: ret i8 %x + Some(x) +} + +#[no_mangle] +fn make_some_u16(x: u16) -> Option { + // CHECK-LABEL: { i16, i16 } @make_some_u16(i16 zeroext %x) + // CHECK-NEXT: start: + // CHECK-NEXT: %0 = insertvalue { i16, i16 } { i16 1, i16 poison }, i16 %x, 1 + // CHECK-NEXT: ret { i16, i16 } %0 + Some(x) +} + +#[no_mangle] +fn make_none_u16() -> Option { + // CHECK-LABEL: { i16, i16 } @make_none_u16() + // CHECK-NEXT: start: + // CHECK-NEXT: ret { i16, i16 } { i16 0, i16 undef } + None +} + +#[no_mangle] +fn make_some_nzu32(x: NonZero) -> Option> { + // CHECK-LABEL: i32 @make_some_nzu32(i32 signext %x) + // CHECK-NEXT: start: + // CHECK-NEXT: ret i32 %x + Some(x) +} + +#[no_mangle] +fn make_ok_ptr(x: NonNull) -> Result, usize> { + // CHECK-LABEL: { i64, ptr } @make_ok_ptr(ptr %x) + // CHECK-NEXT: start: + // CHECK-NEXT: %0 = insertvalue { i64, ptr } { i64 0, ptr poison }, ptr %x, 1 + // CHECK-NEXT: ret { i64, ptr } %0 + Ok(x) +} + +#[no_mangle] +fn make_ok_int(x: usize) -> Result> { + // CHECK-LABEL: { i64, ptr } @make_ok_int(i64 %x) + // CHECK-NEXT: start: + // CHECK-NEXT: %[[NOPROV:.+]] = getelementptr i8, ptr null, i64 %x + // CHECK-NEXT: %[[R:.+]] = insertvalue { i64, ptr } { i64 0, ptr poison }, ptr %[[NOPROV]], 1 + // CHECK-NEXT: ret { i64, ptr } %[[R]] + Ok(x) +} + +#[no_mangle] +fn make_some_ref(x: &u16) -> Option<&u16> { + // CHECK-LABEL: ptr @make_some_ref(ptr align 2 %x) + // CHECK-NEXT: start: + // CHECK-NEXT: ret ptr %x + Some(x) +} + +#[no_mangle] +fn make_none_ref<'a>() -> Option<&'a u16> { + // CHECK-LABEL: ptr @make_none_ref() + // CHECK-NEXT: start: + // CHECK-NEXT: ret ptr null + None +} + +#[inline(never)] +fn make_err_generic(e: E) -> Result { + // CHECK-LABEL: define{{.+}}make_err_generic + // CHECK-NEXT: start: + // CHECK-NEXT: call void @llvm.trap() + // CHECK-NEXT: ret i32 poison + Err(e) +} + +#[no_mangle] +fn make_uninhabited_err_indirectly(n: Never) -> Result { + // CHECK-LABEL: i32 @make_uninhabited_err_indirectly() + // CHECK-NEXT: start: + // CHECK-NEXT: call{{.+}}make_err_generic + make_err_generic(n) +} + +#[no_mangle] +fn make_fully_uninhabited_result(v: u32, n: Never) -> Result<(u32, Never), (Never, u32)> { + // Actually reaching this would be UB, so we don't actually build a result. + + // CHECK-LABEL: { i32, i32 } @make_fully_uninhabited_result(i32 signext %v) + // CHECK-NEXT: start: + // CHECK-NEXT: call void @llvm.trap() + // CHECK-NEXT: call void @llvm.trap() + // CHECK-NEXT: call void @llvm.trap() + // CHECK-NEXT: unreachable + Ok((v, n)) +} + +enum Never {} From e140b9ebf45e4fb9ab07eeca32f834f576b0d0a4 Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:30:49 +0800 Subject: [PATCH 3/6] Fix tests/codegen/simd/extract-insert-dyn.rs test failure on riscv64 --- tests/codegen/simd/extract-insert-dyn.rs | 27 ++++++++++++++++-------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/tests/codegen/simd/extract-insert-dyn.rs b/tests/codegen/simd/extract-insert-dyn.rs index 729f0145314a3..9c17b82e55352 100644 --- a/tests/codegen/simd/extract-insert-dyn.rs +++ b/tests/codegen/simd/extract-insert-dyn.rs @@ -5,7 +5,8 @@ repr_simd, arm_target_feature, mips_target_feature, - s390x_target_feature + s390x_target_feature, + riscv_target_feature )] #![no_std] #![crate_type = "lib"] @@ -25,97 +26,105 @@ pub struct u32x16([u32; 16]); pub struct i8x16([i8; 16]); // CHECK-LABEL: dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 %idx +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 %idx #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn dyn_simd_extract(x: i8x16, idx: u32) -> i8 { simd_extract_dyn(x, idx) } // CHECK-LABEL: literal_dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn literal_dyn_simd_extract(x: i8x16) -> i8 { simd_extract_dyn(x, 7) } // CHECK-LABEL: const_dyn_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_dyn_simd_extract(x: i8x16) -> i8 { simd_extract_dyn(x, const { 3 + 4 }) } // CHECK-LABEL: const_simd_extract -// CHECK: extractelement <16 x i8> %x, i32 7 +// CHECK: extractelement <16 x i8> %[[TEMP:.+]], i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_simd_extract(x: i8x16) -> i8 { simd_extract(x, const { 3 + 4 }) } // CHECK-LABEL: dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 %idx +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 %idx #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn dyn_simd_insert(x: i8x16, e: i8, idx: u32) -> i8x16 { simd_insert_dyn(x, idx, e) } // CHECK-LABEL: literal_dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn literal_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert_dyn(x, 7, e) } // CHECK-LABEL: const_dyn_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_dyn_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert_dyn(x, const { 3 + 4 }, e) } // CHECK-LABEL: const_simd_insert -// CHECK: insertelement <16 x i8> %x, i8 %e, i32 7 +// CHECK: insertelement <16 x i8> %[[TEMP:.+]], i8 %e, i32 7 #[no_mangle] #[cfg_attr(target_family = "wasm", target_feature(enable = "simd128"))] #[cfg_attr(target_arch = "arm", target_feature(enable = "neon"))] #[cfg_attr(target_arch = "x86", target_feature(enable = "sse"))] #[cfg_attr(target_arch = "mips", target_feature(enable = "msa"))] #[cfg_attr(target_arch = "s390x", target_feature(enable = "vector"))] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] unsafe extern "C" fn const_simd_insert(x: i8x16, e: i8) -> i8x16 { simd_insert(x, const { 3 + 4 }, e) } From 7de63ec742505ea6aaa2c20cf69d9f14ede338dd Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:34:12 +0800 Subject: [PATCH 4/6] Fix tests/codegen/transmute-scalar.rs test failure on riscv64 --- ...-scalar.rs => transmute-scalar-generic.rs} | 1 + tests/codegen/transmute-scalar-riscv64.rs | 137 ++++++++++++++++++ 2 files changed, 138 insertions(+) rename tests/codegen/{transmute-scalar.rs => transmute-scalar-generic.rs} (99%) create mode 100644 tests/codegen/transmute-scalar-riscv64.rs diff --git a/tests/codegen/transmute-scalar.rs b/tests/codegen/transmute-scalar-generic.rs similarity index 99% rename from tests/codegen/transmute-scalar.rs rename to tests/codegen/transmute-scalar-generic.rs index ce1b0558b2eec..e8fda2cd566c3 100644 --- a/tests/codegen/transmute-scalar.rs +++ b/tests/codegen/transmute-scalar-generic.rs @@ -1,5 +1,6 @@ //@ add-core-stubs //@ compile-flags: -C opt-level=0 -C no-prepopulate-passes +//@ ignore-riscv64 #![crate_type = "lib"] #![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature)] diff --git a/tests/codegen/transmute-scalar-riscv64.rs b/tests/codegen/transmute-scalar-riscv64.rs new file mode 100644 index 0000000000000..058bdf200f06f --- /dev/null +++ b/tests/codegen/transmute-scalar-riscv64.rs @@ -0,0 +1,137 @@ +//@ add-core-stubs +//@ compile-flags: -C opt-level=0 -C no-prepopulate-passes +//@only-riscv64 + +#![crate_type = "lib"] +#![feature(no_core, repr_simd, arm_target_feature, mips_target_feature, s390x_target_feature)] +#![no_core] +#![feature(riscv_target_feature)] +extern crate minicore; + +use minicore::*; + +// With opaque ptrs in LLVM, `transmute` can load/store any `alloca` as any type, +// without needing to pointercast, and SRoA will turn that into a `bitcast`. +// Thus memory-to-memory transmutes don't need to generate them ourselves. + +// However, `bitcast`s and `ptrtoint`s and `inttoptr`s are still worth doing when +// that allows us to avoid the `alloca`s entirely; see `rvalue_creates_operand`. + +// CHECK-LABEL: define{{.*}}i32 @f32_to_bits(float %x) +// CHECK: %_0 = bitcast float %x to i32 +// CHECK-NEXT: ret i32 %_0 +#[no_mangle] +pub fn f32_to_bits(x: f32) -> u32 { + unsafe { mem::transmute(x) } +} + +// CHECK-LABEL: define{{.*}}i8 @bool_to_byte(i1 zeroext %b) +// CHECK: %_0 = zext i1 %b to i8 +// CHECK-NEXT: ret i8 %_0 +#[no_mangle] +pub fn bool_to_byte(b: bool) -> u8 { + unsafe { mem::transmute(b) } +} + +// CHECK-LABEL: define{{.*}}zeroext i1 @byte_to_bool(i8{{.*}} %byte) +// CHECK: %_0 = trunc{{( nuw)?}} i8 %byte to i1 +// CHECK-NEXT: ret i1 %_0 +#[no_mangle] +pub unsafe fn byte_to_bool(byte: u8) -> bool { + mem::transmute(byte) +} + +// CHECK-LABEL: define{{.*}}ptr @ptr_to_ptr(ptr %p) +// CHECK: ret ptr %p +#[no_mangle] +pub fn ptr_to_ptr(p: *mut u16) -> *mut u8 { + unsafe { mem::transmute(p) } +} + +// CHECK: define{{.*}}[[USIZE:i[0-9]+]] @ptr_to_int(ptr %p) +// CHECK: %_0 = ptrtoint ptr %p to [[USIZE]] +// CHECK-NEXT: ret [[USIZE]] %_0 +#[no_mangle] +pub fn ptr_to_int(p: *mut u16) -> usize { + unsafe { mem::transmute(p) } +} + +// CHECK: define{{.*}}ptr @int_to_ptr([[USIZE]] %i) +// CHECK: %_0 = getelementptr i8, ptr null, [[USIZE]] %i +// CHECK-NEXT: ret ptr %_0 +#[no_mangle] +pub fn int_to_ptr(i: usize) -> *mut u16 { + unsafe { mem::transmute(i) } +} + +// This is the one case where signedness matters to transmuting: +// the LLVM type is `i8` here because of `repr(i8)`, +// whereas below with the `repr(u8)` it's `i1` in LLVM instead. +#[repr(i8)] +pub enum FakeBoolSigned { + False = 0, + True = 1, +} + +// CHECK-LABEL: define{{.*}}i8 @bool_to_fake_bool_signed(i1 zeroext %b) +// CHECK: %_0 = zext i1 %b to i8 +// CHECK-NEXT: ret i8 %_0 +#[no_mangle] +pub fn bool_to_fake_bool_signed(b: bool) -> FakeBoolSigned { + unsafe { mem::transmute(b) } +} + +// CHECK-LABEL: define{{.*}}i1 @fake_bool_signed_to_bool(i8 signext %b) +// CHECK: %_0 = trunc nuw i8 %b to i1 +// CHECK-NEXT: ret i1 %_0 +#[no_mangle] +pub fn fake_bool_signed_to_bool(b: FakeBoolSigned) -> bool { + unsafe { mem::transmute(b) } +} + +#[repr(u8)] +pub enum FakeBoolUnsigned { + False = 0, + True = 1, +} + +// CHECK-LABEL: define{{.*}}i1 @bool_to_fake_bool_unsigned(i1 zeroext %b) +// CHECK: ret i1 %b +#[no_mangle] +pub fn bool_to_fake_bool_unsigned(b: bool) -> FakeBoolUnsigned { + unsafe { mem::transmute(b) } +} + +// CHECK-LABEL: define{{.*}}i1 @fake_bool_unsigned_to_bool(i1 zeroext %b) +// CHECK: ret i1 %b +#[no_mangle] +pub fn fake_bool_unsigned_to_bool(b: FakeBoolUnsigned) -> bool { + unsafe { mem::transmute(b) } +} + +#[repr(simd)] +struct S([i64; 1]); + +// CHECK-LABEL: define{{.*}}i64 @single_element_simd_to_scalar(i64 %{{.*}}) +// CHECK-NEXT: start: +// CHECK-NEXT: %[[RET:.+]] = alloca [8 x i8] +// CHECK: store <1 x i64> %[[TEMP:.+]], ptr %[[RET]] +// CHECK: %[[TEMP:.+]] = load i64, ptr %[[RET]] +// CHECK: ret i64 %[[TEMP]] +#[no_mangle] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] +pub extern "C" fn single_element_simd_to_scalar(b: S) -> i64 { + unsafe { mem::transmute(b) } +} + +// CHECK-LABEL: define{{.*}}i64 @scalar_to_single_element_simd(i64 %b) +// CHECK-NEXT: start: +// CHECK-NEXT: %[[RET:.+]] = alloca [8 x i8] +// CHECK-NEXT: store i64 %b, ptr %[[RET]] +// CHECK-NEXT: %[[TEMP:.+]] = load i64, ptr %[[RET]] +// CHECK-NEXT: ret i64 %[[TEMP]] +#[no_mangle] +#[cfg_attr(target_arch = "riscv64", target_feature(enable = "v"))] +pub extern "C" fn scalar_to_single_element_simd(b: i64) -> S { + unsafe { mem::transmute(b) } +} From 2a5a001629a108bb52fe7023ddd1c26ca8a4b390 Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:36:01 +0800 Subject: [PATCH 5/6] Fix tests/uninhabited-transparent-return-abi.rs test failure on riscv64 --- ...habited-transparent-return-abi-generic.rs} | 1 + ...nhabited-transparent-return-abi-riscv64.rs | 45 +++++++++++++++++++ 2 files changed, 46 insertions(+) rename tests/codegen/{uninhabited-transparent-return-abi.rs => uninhabited-transparent-return-abi-generic.rs} (98%) create mode 100644 tests/codegen/uninhabited-transparent-return-abi-riscv64.rs diff --git a/tests/codegen/uninhabited-transparent-return-abi.rs b/tests/codegen/uninhabited-transparent-return-abi-generic.rs similarity index 98% rename from tests/codegen/uninhabited-transparent-return-abi.rs rename to tests/codegen/uninhabited-transparent-return-abi-generic.rs index face1577c3f69..09e0846bad0f3 100644 --- a/tests/codegen/uninhabited-transparent-return-abi.rs +++ b/tests/codegen/uninhabited-transparent-return-abi-generic.rs @@ -1,4 +1,5 @@ //@ compile-flags: -Copt-level=3 +//@ ignore-riscv64 // See https://github.com/rust-lang/rust/issues/135802 diff --git a/tests/codegen/uninhabited-transparent-return-abi-riscv64.rs b/tests/codegen/uninhabited-transparent-return-abi-riscv64.rs new file mode 100644 index 0000000000000..de575b4b529bf --- /dev/null +++ b/tests/codegen/uninhabited-transparent-return-abi-riscv64.rs @@ -0,0 +1,45 @@ +//@ compile-flags: -Copt-level=3 +//@ only-riscv64 + +// See https://github.com/rust-lang/rust/issues/135802 + +#![crate_type = "lib"] + +enum Void {} + +// Should be ABI-compatible with T, but wasn't prior to the PR adding this test. +#[repr(transparent)] +struct NoReturn(T, Void); + +// Returned by invisible reference (in most ABIs) +#[allow(dead_code)] +struct Large(u64, u64, u64); + +extern "Rust" { + fn opaque() -> NoReturn; + fn opaque_with_arg(rsi: u32) -> NoReturn; +} + +// CHECK-LABEL: @test_uninhabited_ret_by_ref +#[no_mangle] +pub fn test_uninhabited_ret_by_ref() { + // CHECK: %_1 = alloca [24 x i8], align {{8|4}} + // CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %_1) + // CHECK-NEXT: call void @opaque({{.*}} sret([24 x i8]) {{.*}} %_1) #2 + // CHECK-NEXT: unreachable + unsafe { + opaque(); + } +} + +// CHECK-LABEL: @test_uninhabited_ret_by_ref_with_arg +#[no_mangle] +pub fn test_uninhabited_ret_by_ref_with_arg(rsi: u32) { + // CHECK: %_2 = alloca [24 x i8], align {{8|4}} + // CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 24, ptr nonnull %_2) + // CHECK-NEXT: call void @opaque_with_arg({{.*}} sret([24 x i8]) {{.*}} %_2, i32 noundef signext %rsi) #2 + // CHECK-NEXT: unreachable + unsafe { + opaque_with_arg(rsi); + } +} From a5b6dba8ff269a2df8c9d0048efa3a1d329b8e29 Mon Sep 17 00:00:00 2001 From: CaiWeiran Date: Thu, 10 Jul 2025 21:36:53 +0800 Subject: [PATCH 6/6] Fix tests/assembly/dwarf-mixed-versions-lto.rs test failure on riscv64 --- tests/assembly/dwarf-mixed-versions-lto.rs | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tests/assembly/dwarf-mixed-versions-lto.rs b/tests/assembly/dwarf-mixed-versions-lto.rs index 9910a6e2f5fcc..828328df84330 100644 --- a/tests/assembly/dwarf-mixed-versions-lto.rs +++ b/tests/assembly/dwarf-mixed-versions-lto.rs @@ -1,6 +1,7 @@ // This test ensures that if LTO occurs between crates with different DWARF versions, we // will choose the highest DWARF version for the final binary. This matches Clang's behavior. // Note: `.2byte` directive is used on MIPS. +// Note: `.half` directive is used on RISC-V. //@ only-linux //@ aux-build:dwarf-mixed-versions-lto-aux.rs @@ -15,6 +16,6 @@ fn main() { } // CHECK: .section .debug_info -// CHECK-NOT: {{\.(short|hword|2byte)}} 2 -// CHECK-NOT: {{\.(short|hword|2byte)}} 4 -// CHECK: {{\.(short|hword|2byte)}} 5 +// CHECK-NOT: {{\.(short|hword|2byte|half)}} 2 +// CHECK-NOT: {{\.(short|hword|2byte|half)}} 4 +// CHECK: {{\.(short|hword|2byte|half)}} 5