From 0d4239b21152236308c7b2d2144bc2e94a5462e9 Mon Sep 17 00:00:00 2001 From: Alexey Minnekhanov Date: Thu, 4 Aug 2022 03:43:17 +0300 Subject: [PATCH 001/143] sdm660_defconfig Generated with: $ make savedefconfig && cp defconfig ../arch/arm64/configs/sdm660_defconfig Signed-off-by: Alexey Minnekhanov --- arch/arm64/configs/sdm660_defconfig | 660 ++++++++++++++++++++++++++++ 1 file changed, 660 insertions(+) create mode 100644 arch/arm64/configs/sdm660_defconfig diff --git a/arch/arm64/configs/sdm660_defconfig b/arch/arm64/configs/sdm660_defconfig new file mode 100644 index 00000000000000..8163a7e7cd284d --- /dev/null +++ b/arch/arm64/configs/sdm660_defconfig @@ -0,0 +1,660 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_PSI=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_MISC=y +CONFIG_USER_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PROFILING=y +CONFIG_ARCH_QCOM=y +# CONFIG_ARM64_ERRATUM_2077057 is not set +# CONFIG_ROCKCHIP_ERRATUM_3588001 is not set +CONFIG_ARM64_VA_BITS_48=y +CONFIG_SCHED_MC=y +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +CONFIG_COMPAT_ALIGNMENT_FIXUPS=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_CMDLINE="earlycon debug clk_ignore_unused pd_ignore_unused ignore_loglevel fw_devlink=permissive" +CONFIG_CMDLINE_FORCE=y +# CONFIG_EFI is not set +CONFIG_HIBERNATION=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +CONFIG_CPU_IDLE=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=m +CONFIG_CPU_FREQ_GOV_USERSPACE=m +CONFIG_CPU_FREQ_GOV_ONDEMAND=m +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_QCOM_CPUFREQ_NVMEM=m +CONFIG_ARM_QCOM_CPUFREQ_HW=m +CONFIG_JUMP_LABEL=y +# CONFIG_GCC_PLUGINS is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_COMPRESS_GZIP=y +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_IOSCHED_BFQ is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_KSM=y +CONFIG_MEMORY_FAILURE=y +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_CMA=y +CONFIG_LRU_GEN=y +CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IPV6=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_CT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_FIB_INET=m +CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_IP_VS=m +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_NFCT=y +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_NET_SCHED=y +CONFIG_NET_CLS_CGROUP=m +CONFIG_QRTR=m +CONFIG_QRTR_SMD=m +CONFIG_QRTR_TUN=m +CONFIG_CGROUP_NET_PRIO=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HS=y +CONFIG_BT_LEDS=y +CONFIG_BT_MSFTEXT=y +CONFIG_BT_AOSPEXT=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_RTL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_QCOMSMD=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=m +CONFIG_NFC=m +CONFIG_NFC_NCI=m +CONFIG_NFC_S3FWRN5_I2C=m +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +# CONFIG_QCOM_EBI2 is not set +CONFIG_QCOM_SSC_BLOCK_BUS=y +CONFIG_CONNECTOR=y +CONFIG_GNSS=y +CONFIG_OF_OVERLAY=y +CONFIG_ZRAM=m +CONFIG_ZRAM_WRITEBACK=y +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NBD=y +CONFIG_BLK_DEV_RAM=y +CONFIG_VIRTIO_BLK=m +CONFIG_QCOM_COINCELL=m +CONFIG_QCOM_FASTRPC=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_LINEAR=y +CONFIG_MD_RAID0=y +CONFIG_MD_RAID1=y +CONFIG_MD_RAID10=y +CONFIG_MD_RAID456=y +CONFIG_BLK_DEV_DM=y +CONFIG_DM_CRYPT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_RAID=m +CONFIG_DM_VERITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_WIREGUARD=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_IPVLAN=m +CONFIG_VXLAN=m +CONFIG_TUN=m +CONFIG_VETH=m +CONFIG_VIRTIO_NET=m +CONFIG_NLMON=m +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ASIX is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DAVICOM is not set +# CONFIG_NET_VENDOR_ENGLEDER is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FUNGIBLE is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_ADI is not set +# CONFIG_NET_VENDOR_LITEX is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MICROSOFT is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +CONFIG_RMNET=m +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VERTEXCOM is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WANGXUN is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_QCOM_IPA=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_USB_CATC=m +CONFIG_USB_KAWETH=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_USBNET=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_SR9700=m +CONFIG_USB_NET_SR9800=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_AQC111=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_DYNACK=y +CONFIG_ATH9K_WOW=y +CONFIG_ATH9K_CHANNEL_CONTEXT=y +CONFIG_ATH9K_HTC=m +CONFIG_ATH9K_HWRNG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +CONFIG_ATH6KL_USB=m +CONFIG_AR5523=m +CONFIG_ATH10K=m +CONFIG_ATH10K_SDIO=m +CONFIG_ATH10K_SNOC=m +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K_DEBUGFS=y +CONFIG_WCN36XX=m +# CONFIG_WLAN_VENDOR_ATMEL is not set +# CONFIG_WLAN_VENDOR_BROADCOM is not set +# CONFIG_WLAN_VENDOR_CISCO is not set +# CONFIG_WLAN_VENDOR_INTEL is not set +# CONFIG_WLAN_VENDOR_INTERSIL is not set +# CONFIG_WLAN_VENDOR_MARVELL is not set +# CONFIG_WLAN_VENDOR_MEDIATEK is not set +# CONFIG_WLAN_VENDOR_MICROCHIP is not set +# CONFIG_WLAN_VENDOR_PURELIFI is not set +# CONFIG_WLAN_VENDOR_RALINK is not set +# CONFIG_WLAN_VENDOR_REALTEK is not set +# CONFIG_WLAN_VENDOR_RSI is not set +# CONFIG_WLAN_VENDOR_SILABS is not set +# CONFIG_WLAN_VENDOR_ST is not set +# CONFIG_WLAN_VENDOR_TI is not set +# CONFIG_WLAN_VENDOR_ZYDAS is not set +# CONFIG_WLAN_VENDOR_QUANTENNA is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_GPIO_POLLED=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +CONFIG_TOUCHSCREEN_NT36XXX=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_PM8941_PWRKEY=y +CONFIG_INPUT_PM8XXX_VIBRATOR=y +CONFIG_INPUT_QCOM_SPMI_HAPTICS=m +CONFIG_INPUT_UINPUT=y +CONFIG_RMI4_CORE=y +CONFIG_RMI4_I2C=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +# CONFIG_SERIO is not set +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +CONFIG_RPMSG_TTY=m +CONFIG_SERIAL_DEV_BUS=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_GPIO=y +CONFIG_I2C_QUP=y +CONFIG_I2C_SLAVE=y +CONFIG_SPI=y +CONFIG_SPI_MEM=y +CONFIG_SPI_BITBANG=m +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=m +CONFIG_SPMI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_MSM=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y +CONFIG_PINCTRL_QCOM_SSBI_PMIC=y +CONFIG_PINCTRL_SDM660=y +CONFIG_POWER_RESET_MSM=y +CONFIG_POWER_RESET_QCOM_PON=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_NVMEM_REBOOT_MODE=y +CONFIG_BATTERY_QCOM_BATTMGR=m +CONFIG_CHARGER_QCOM_SMBB=m +CONFIG_BATTERY_RT5033=m +CONFIG_CHARGER_QCOM_SMB2=m +CONFIG_BATTERY_QCOM_FG=m +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_QCOM_TSENS=y +CONFIG_QCOM_SPMI_TEMP_ALARM=m +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_QCOM_WDT=m +CONFIG_MFD_QCOM_RPM=y +CONFIG_MFD_SPMI_PMIC=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_QCOM_RPMH=y +CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y +CONFIG_REGULATOR_QCOM_USB_VBUS=y +CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_DRM=y +CONFIG_DRM_FBDEV_OVERALLOC=200 +CONFIG_DRM_MSM=m +# CONFIG_DRM_MSM_MDP4 is not set +# CONFIG_DRM_MSM_HDMI is not set +CONFIG_DRM_PANEL_DSI_CM=y +CONFIG_DRM_PANEL_SIMPLE=y +CONFIG_DRM_PANEL_FT8716U=m +CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +CONFIG_DRM_PANEL_NOVATEK_NT36672_TIANMA_JASMINE=m +CONFIG_DRM_SIMPLEDRM=y +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_BACKLIGHT_QCOM_WLED=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_LOGO=y +CONFIG_DRM_ACCEL=y +CONFIG_SOUND=m +CONFIG_SND=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SOC=m +CONFIG_SND_SOC_QCOM=m +CONFIG_SND_SOC_APQ8016_SBC=m +CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m +CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m +CONFIG_HID_RAZER=m +CONFIG_I2C_HID_OF=m +CONFIG_I2C_HID_OF_GOODIX=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_CONN_GPIO=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_OTG=y +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI_RENESAS=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_HCD_PLATFORM=y +CONFIG_USB_STORAGE=y +CONFIG_USB_UAS=m +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_ULPI=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_QCOM_EUD=m +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y +CONFIG_U_SERIAL_CONSOLE=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_MIDI=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_TYPEC=y +CONFIG_TYPEC_UCSI=y +CONFIG_UCSI_PMIC_GLINK=m +CONFIG_TYPEC_QCOM_PMIC=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_PM8XXX=y +CONFIG_DMADEVICES=y +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_GPI_DMA=y +# CONFIG_SURFACE_PLATFORMS is not set +CONFIG_COMMON_CLK_QCOM=y +CONFIG_QCOM_CLK_SMD_RPM=y +CONFIG_QCOM_CLK_RPMH=y +CONFIG_SDM_MMCC_660=y +CONFIG_SDM_GPUCC_660=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_MAILBOX=y +CONFIG_QCOM_APCS_IPC=y +CONFIG_QCOM_IPCC=m +CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y +CONFIG_IOMMU_DEBUGFS=y +CONFIG_ARM_SMMU=y +CONFIG_ARM_SMMU_V3=y +CONFIG_QCOM_IOMMU=y +CONFIG_REMOTEPROC=y +CONFIG_QCOM_Q6V5_MSS=m +CONFIG_QCOM_Q6V5_PAS=m +CONFIG_QCOM_Q6V5_WCSS=m +CONFIG_QCOM_SYSMON=m +CONFIG_QCOM_WCNSS_PIL=m +CONFIG_RPMSG_CHAR=y +CONFIG_RPMSG_CTRL=y +CONFIG_RPMSG_NS=y +CONFIG_RPMSG_QCOM_GLINK_RPM=y +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +CONFIG_SOUNDWIRE=m +CONFIG_SOUNDWIRE_QCOM=m +CONFIG_QCOM_AOSS_QMP=m +CONFIG_QCOM_COMMAND_DB=y +CONFIG_QCOM_CPR=m +CONFIG_QCOM_GENI_SE=m +CONFIG_QCOM_GSBI=m +CONFIG_QCOM_LLCC=m +CONFIG_QCOM_OCMEM=m +CONFIG_QCOM_PMIC_GLINK=m +CONFIG_QCOM_RAMP_CTRL=m +CONFIG_QCOM_RMTFS_MEM=m +CONFIG_QCOM_RPMH=y +CONFIG_QCOM_RPMHPD=y +CONFIG_QCOM_RPMPD=y +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMD_RPM=y +CONFIG_QCOM_SMP2P=y +CONFIG_QCOM_SMSM=y +CONFIG_QCOM_SOCINFO=y +CONFIG_QCOM_SPM=m +CONFIG_QCOM_STATS=m +CONFIG_QCOM_WCNSS_CTRL=m +CONFIG_QCOM_APR=m +CONFIG_QCOM_ICC_BWMON=m +CONFIG_PM_DEVFREQ=y +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +CONFIG_DEVFREQ_GOV_PERFORMANCE=y +CONFIG_DEVFREQ_GOV_POWERSAVE=y +CONFIG_DEVFREQ_GOV_USERSPACE=y +CONFIG_DEVFREQ_GOV_PASSIVE=y +CONFIG_EXTCON_GPIO=y +CONFIG_EXTCON_SM5502=y +CONFIG_EXTCON_USB_GPIO=y +CONFIG_MEMORY=y +CONFIG_IIO=m +CONFIG_BMC150_ACCEL=m +CONFIG_QCOM_SPMI_RRADC=m +CONFIG_QCOM_SPMI_IADC=m +CONFIG_QCOM_SPMI_VADC=m +CONFIG_QCOM_SPMI_ADC5=m +CONFIG_BMG160=m +CONFIG_LTR501=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_PWM=y +CONFIG_PWM_CLK=m +CONFIG_PHY_QCOM_QMP=y +CONFIG_PHY_QCOM_QUSB2=y +CONFIG_PHY_QCOM_SNPS_EUSB2=y +CONFIG_PHY_QCOM_EUSB2_REPEATER=y +CONFIG_PHY_QCOM_USB_HS=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_SLIM_QCOM_CTRL=m +CONFIG_SLIM_QCOM_NGD_CTRL=m +CONFIG_INTERCONNECT=y +CONFIG_INTERCONNECT_QCOM=y +CONFIG_INTERCONNECT_QCOM_SDM660=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_F2FS_FS=y +CONFIG_FANOTIFY=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_QUOTA=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_UTF8=y +CONFIG_EXFAT_FS=y +CONFIG_NTFS3_FS=m +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +CONFIG_PSTORE=y +# CONFIG_PSTORE_DEFLATE_COMPRESS is not set +CONFIG_PSTORE_CONSOLE=y +CONFIG_PSTORE_PMSG=y +CONFIG_PSTORE_RAM=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITYFS=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_CRYPTD=y +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_ZSTD=y +CONFIG_CRYPTO_ANSI_CPRNG=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_NHPOLY1305_NEON=m +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=m +CONFIG_CRYPTO_SHA3_ARM64=m +CONFIG_CRYPTO_SM3_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_CRYPTO_SM4_ARM64_CE=m +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_DEV_QCOM_RNG=y +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=32 +CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +CONFIG_PANIC_TIMEOUT=-1 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set From 5a320bfab77726feca7acb92cf4c701f39644341 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 20:38:28 +0200 Subject: [PATCH 002/143] iommu/arm-smmu-qcom: Skip the TTBR1 quirk for MSM8998 and SDM630 Similarly to MSM8996 DragonBoard 820c, MSM8998 and SDM630 are equipped with Adreno 5xx series, which doesn't have separate pagetables support at the moment of writing. Skip the TTBR1 quirk for these two SoCs as to get Adreno in a usable state. --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index c71afda79d6442..b208854b54dd36 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -199,7 +199,9 @@ static bool qcom_adreno_can_do_ttbr1(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; - if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2")) + if (of_device_is_compatible(np, "qcom,msm8996-smmu-v2") || + of_device_is_compatible(np, "qcom,msm8998-smmu-v2") || + of_device_is_compatible(np, "qcom,sdm630-smmu-v2")) return false; return true; From 364257d63f83b5b81784c54b13f870cd6a801779 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 10 Aug 2021 20:42:48 +0200 Subject: [PATCH 003/143] iommu/arm-smmu-qcom: Add MSM8998 and SDM660 mss compatibles for identity Add MSM8998 and SDM660's mss-pil compatibles to switch the default iommu domain type to IDENTITY, as similarly required by SDM845 and others. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for 6.0-rc2) --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index b208854b54dd36..2432b1c723b77c 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -247,6 +247,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,adreno" }, { .compatible = "qcom,mdp4" }, { .compatible = "qcom,mdss" }, + { .compatible = "qcom,msm8998-mss-pil" }, { .compatible = "qcom,sc7180-mdss" }, { .compatible = "qcom,sc7180-mss-pil" }, { .compatible = "qcom,sc7280-mdss" }, @@ -255,6 +256,7 @@ static const struct of_device_id qcom_smmu_client_of_match[] __maybe_unused = { { .compatible = "qcom,sc8280xp-mdss" }, { .compatible = "qcom,sm8150-mdss" }, { .compatible = "qcom,sm8250-mdss" }, + { .compatible = "qcom,sdm660-mss-pil" }, { .compatible = "qcom,sdm845-mdss" }, { .compatible = "qcom,sdm845-mss-pil" }, { } From 4d815506ba955bddb6863acb633b604a9def911a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 4 Aug 2021 16:39:35 +0200 Subject: [PATCH 004/143] iommu/arm-smmu-qcom: Allow choosing a custom bypass emulation context It cannot be taken for granted that the last IOMMU context is free and available for us to use it to emulate bypass streams and, at least on MSM8998's lpass iommu, using the last one will produce a crash; please note that this may not be only dependant on the SoC, but also on the firmware version. To overcome to this issue, allow specifying a different context for bypass emulation with the optional DT property "qcom,bypass-cbndx": if this property is not found this means that we are either booting with ACPI instead or that we don't want to specify a custom cb because the default one (the last context bank) is fine. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for v6.0-rc1) --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 2432b1c723b77c..a446819520ff1b 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -305,7 +305,8 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) reg = arm_smmu_gr0_read(smmu, last_s2cr); if (FIELD_GET(ARM_SMMU_S2CR_TYPE, reg) != S2CR_TYPE_BYPASS) { qsmmu->bypass_quirk = true; - qsmmu->bypass_cbndx = smmu->num_context_banks - 1; + if (qsmmu->bypass_cbndx == 0xff) + qsmmu->bypass_cbndx = smmu->num_context_banks - 1; set_bit(qsmmu->bypass_cbndx, smmu->context_map); @@ -467,6 +468,16 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; + qsmmu->bypass_cbndx = 0xff; + + if (np != NULL) { + /* + * This property is optional and we expect to fail finding it if: + * - Using the default bypass_cbndx (in the .cfg_probe cb) is fine; or + * - We are booting on ACPI + */ + of_property_read_u8(np, "qcom,bypass-cbndx", &qsmmu->bypass_cbndx); + } return &qsmmu->smmu; } From 3a238a041067fec6581b9525e0213976b0218224 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 13:14:41 +0200 Subject: [PATCH 005/143] iommu/arm-smmu: Allow skipping context bank disable at reset time On some SoCs some IOMMU context banks are actively used from TZ during system boot, or some hypervisor configurations will trigger a system reset upon disabling some protected/secured CBs. Allow skipping the disablement of such contexts at IOMMU reset time during initialization with a new implementation detail to work around this quirk. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu.c | 10 ++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + 2 files changed, 11 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 6e0813b26fb698..d3c21de1f33c8a 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -1603,6 +1603,16 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu) /* Make sure all context banks are disabled and clear CB_FSR */ for (i = 0; i < smmu->num_context_banks; ++i) { + /* + * Some context banks cannot be disabled due to hypervisor + * configuration on some systems; if this is the case, + * skip disabling and writing FAULT on the CB FSR in order + * to avoid a system crash. + */ + if (smmu->impl && smmu->impl->reset_cb_nodisable && + smmu->impl->reset_cb_nodisable(smmu, i)) { + continue; + } arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 703fd5817ec11f..2f1364b1a9682d 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -430,6 +430,7 @@ struct arm_smmu_impl { u64 val); int (*cfg_probe)(struct arm_smmu_device *smmu); int (*reset)(struct arm_smmu_device *smmu); + bool (*reset_cb_nodisable)(struct arm_smmu_device *smmu, int cbndx); int (*init_context)(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *cfg, struct device *dev); void (*tlb_sync)(struct arm_smmu_device *smmu, int page, int sync, From 611048081e6f4b1a4e607a123f5991921bdaa64f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 13:19:14 +0200 Subject: [PATCH 006/143] iommu/arm-smmu-qcom: Avoid disabling secured context banks Some Qualcomm SoCs' TZ/hypervisor configuration is disallowing the disablement of some context banks, being them used for tzapps and/or remote processors; any attempt to disable such CBs will result in triggering a fault and the system will freeze and/or reset. For this reason, get a list of context banks that should never get disabled during smmu initialization through a DT array property `qcom,reset-nodisable-cbs`. It was chosen to not hardcode the CBs as this is dependant on the SoC's firmware, which may vary on different boards. Signed-off-by: AngeloGioacchino Del Regno (JAMI: fixup for v6.0-rc1) --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 44 ++++++++++++++++++++++ drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h | 1 + 2 files changed, 45 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index a446819520ff1b..99e31e7a998e75 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -397,10 +397,32 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) return ret; } +static int qcom_smmu500_reset(struct arm_smmu_device *smmu) +{ + const struct device_node *np = smmu->dev->of_node; + + arm_mmu500_reset(smmu); + + if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) + return qcom_sdm845_smmu500_reset(smmu); + + return 0; +} + +static bool qcom_smmu500_reset_cb_nodisable(struct arm_smmu_device *smmu, + int cbndx) +{ + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); + + return test_bit(cbndx, qsmmu->reset_cb_nodisable_mask); +} + static const struct arm_smmu_impl qcom_smmu_v2_impl = { .init_context = qcom_smmu_init_context, .cfg_probe = qcom_smmu_cfg_probe, .def_domain_type = qcom_smmu_def_domain_type, + .reset = qcom_smmu500_reset, + .reset_cb_nodisable = qcom_smmu500_reset_cb_nodisable, .write_s2cr = qcom_smmu_write_s2cr, .tlb_sync = qcom_smmu_tlb_sync, }; @@ -426,6 +448,8 @@ static const struct arm_smmu_impl sdm845_smmu_500_impl = { static const struct arm_smmu_impl qcom_adreno_smmu_v2_impl = { .init_context = qcom_adreno_smmu_init_context, .def_domain_type = qcom_smmu_def_domain_type, + .reset = qcom_smmu500_reset, + .reset_cb_nodisable = qcom_smmu500_reset_cb_nodisable, .alloc_context_bank = qcom_adreno_smmu_alloc_context_bank, .write_sctlr = qcom_adreno_smmu_write_sctlr, .tlb_sync = qcom_smmu_tlb_sync, @@ -446,6 +470,8 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, const struct device_node *np = smmu->dev->of_node; const struct arm_smmu_impl *impl; struct qcom_smmu *qsmmu; + u8 reset_nodisable_cbs[ARM_SMMU_MAX_CBS]; + int i, sz; if (!data) return ERR_PTR(-EINVAL); @@ -469,6 +495,7 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, qsmmu->smmu.impl = impl; qsmmu->cfg = data->cfg; qsmmu->bypass_cbndx = 0xff; + bitmap_zero(qsmmu->reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS); if (np != NULL) { /* @@ -477,6 +504,23 @@ static struct arm_smmu_device *qcom_smmu_create(struct arm_smmu_device *smmu, * - We are booting on ACPI */ of_property_read_u8(np, "qcom,bypass-cbndx", &qsmmu->bypass_cbndx); + + /* + * Some context banks may not be disabled because they are + * secured: read from DT a list of secured contexts that cannot + * be disabled without crashing the system. + * This list is optional, as not all firmware configurations do + * require us skipping disablement of context banks. + */ + sz = of_property_read_variable_u8_array(np, "qcom,reset-nodisable-cbs", + reset_nodisable_cbs, + 1, ARM_SMMU_MAX_CBS); + if (sz > 0) { + for (i = 0; i < sz; i++) { + __set_bit(reset_nodisable_cbs[i], + qsmmu->reset_cb_nodisable_mask); + } + } } return &qsmmu->smmu; diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h index 593910567b8842..5dd38996f1e472 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.h @@ -9,6 +9,7 @@ struct qcom_smmu { struct arm_smmu_device smmu; const struct qcom_smmu_config *cfg; + DECLARE_BITMAP(reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS); bool bypass_quirk; u8 bypass_cbndx; u32 stall_enabled; From b476b8a4519376f8105df68b6d21f43ccecd255d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 6 Aug 2021 15:15:33 +0200 Subject: [PATCH 007/143] iommu/arm-smmu-qcom: Don't modify sACR on hypervisor secured iommus Avoid modifying the contents of the secure Auxiliary Control Register on some Qualcomm SoCs: due to a hypervisor configuration on some firmware versions, this would result in a system crash. Signed-off-by: AngeloGioacchino Del Regno --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 99e31e7a998e75..6a62c001436c5f 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -400,8 +400,15 @@ static int qcom_sdm845_smmu500_reset(struct arm_smmu_device *smmu) static int qcom_smmu500_reset(struct arm_smmu_device *smmu) { const struct device_node *np = smmu->dev->of_node; + struct qcom_smmu *qsmmu = to_qcom_smmu(smmu); - arm_mmu500_reset(smmu); + /* + * Execute the mmu-500 reset implementation detail only if there + * are no secured untouchable contexts in this iommu, otherwise + * the system will crash. + */ + if (bitmap_empty(qsmmu->reset_cb_nodisable_mask, ARM_SMMU_MAX_CBS)) + arm_mmu500_reset(smmu); if (of_device_is_compatible(np, "qcom,sdm845-smmu-500")) return qcom_sdm845_smmu500_reset(smmu); From 9d4367889c6303dad8636a651c023f2f22085229 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 4 Aug 2021 17:38:27 +0200 Subject: [PATCH 008/143] arm64: dts: sdm630: Override bypass emulation context for lpass, anoc2 On the LPASS and ANOC2 IOMMUs, we cannot use the last context to emulate bypass streams: set the right context banks to avoid crashes. --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index eaead2f7beb4ea..8ead357af907fa 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -25,6 +25,7 @@ mmc2 = &sdhc_2; }; + chosen { }; clocks { @@ -639,6 +640,7 @@ clock-names = "bus"; #global-interrupts = <2>; #iommu-cells = <1>; + qcom,bypass-cbndx = /bits/ 8 <3>; interrupts = , @@ -1162,6 +1164,7 @@ compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; reg = <0x05100000 0x40000>; #iommu-cells = <1>; + qcom,bypass-cbndx = /bits/ 8 <12>; #global-interrupts = <2>; interrupts = From 887742c7868797a5b3c266eb26e47641ce69fe84 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 4 Aug 2021 23:10:04 +0200 Subject: [PATCH 009/143] arm64: dts: qcom: sdm630: Disallow disabling secured iommu context banks Some IOMMU context banks are secured and any attempt to disable them during arm-smmu initialization will result in a system crash. To work around this issue, add a list of context banks that will never be disabled, but only reconfigured, at initialization time. Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 8ead357af907fa..3b9223c0be187d 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -640,7 +640,9 @@ clock-names = "bus"; #global-interrupts = <2>; #iommu-cells = <1>; - qcom,bypass-cbndx = /bits/ 8 <3>; + qcom,bypass-cbndx = /bits/ 8 <6>; + qcom,reset-nodisable-cbs = /bits/ 8 <7 8 9 10 11 12 13 14 + 15 16 17 18 19 20>; interrupts = , @@ -1127,6 +1129,7 @@ clock-names = "iface", "mem", "mem_iface"; #global-interrupts = <2>; #iommu-cells = <1>; + qcom,reset-nodisable-cbs = /bits/ 8 <2 3 4>; interrupts = , @@ -1165,6 +1168,7 @@ reg = <0x05100000 0x40000>; #iommu-cells = <1>; qcom,bypass-cbndx = /bits/ 8 <12>; + qcom,reset-nodisable-cbs = /bits/ 8 <13>; #global-interrupts = <2>; interrupts = From ce5f73de567f1967b140de608eca146891307e59 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 28 Oct 2020 23:13:01 +0100 Subject: [PATCH 010/143] Input: Add Novatek NT36xxx touchscreen driver This is a driver for the Novatek in-cell touch controller and supports various chips from the NT36xxx family, currently including NT36525, NT36672A, NT36676F, NT36772 and NT36870. Functionality like wake gestures and firmware flashing is not included: I am not aware of any of these DrIC+Touch combo chips not including a non-volatile memory and it should be highly unlikely to find one, since the touch firmware is embedded into the DriverIC one, which is obviously necessary to drive the display unit. However, the necessary address for the firmware update procedure was included into the address table in this driver so, in the event that someone finds the need to implement it for a reason or another, it will be pretty straightforward to. This driver is lightly based on the downstream implementation [1]. [1] https://github.com/Rasenkai/caf-tsoft-Novatek-nt36xxx Signed-off-by: AngeloGioacchino Del Regno --- drivers/input/touchscreen/Kconfig | 12 + drivers/input/touchscreen/Makefile | 1 + drivers/input/touchscreen/nt36xxx.c | 893 ++++++++++++++++++++++++++++ drivers/input/touchscreen/nt36xxx.h | 122 ++++ 4 files changed, 1028 insertions(+) create mode 100644 drivers/input/touchscreen/nt36xxx.c create mode 100644 drivers/input/touchscreen/nt36xxx.h diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 143ff43c67ae33..fc2a2e97fd89b8 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -674,6 +674,18 @@ config TOUCHSCREEN_IMAGIS To compile this driver as a module, choose M here: the module will be called imagis. +config TOUCHSCREEN_NT36XXX + tristate "Novatek NT36XXX In-Cell I2C touchscreen controller" + depends on I2C + help + Say Y here if you have a Novatek NT36xxx series In-Cell + touchscreen connected to your system over I2C. + + If unsure, say N. + + To compile this driver as a module, choose M here: the + module will be called nt36xxx. + config TOUCHSCREEN_IMX6UL_TSC tristate "Freescale i.MX6UL touchscreen controller" depends on ((OF && GPIOLIB) || COMPILE_TEST) && HAS_IOMEM diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 159cd5136fdbca..41a100c90ad2b3 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -68,6 +68,7 @@ obj-$(CONFIG_TOUCHSCREEN_MSG2638) += msg2638.o obj-$(CONFIG_TOUCHSCREEN_MTOUCH) += mtouch.o obj-$(CONFIG_TOUCHSCREEN_MK712) += mk712.o obj-$(CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS) += novatek-nvt-ts.o +obj-$(CONFIG_TOUCHSCREEN_NT36XXX) += nt36xxx.o obj-$(CONFIG_TOUCHSCREEN_HP600) += hp680_ts_input.o obj-$(CONFIG_TOUCHSCREEN_HP7XX) += jornada720_ts.o obj-$(CONFIG_TOUCHSCREEN_IPAQ_MICRO) += ipaq-micro-ts.o diff --git a/drivers/input/touchscreen/nt36xxx.c b/drivers/input/touchscreen/nt36xxx.c new file mode 100644 index 00000000000000..ee8cdeea78c832 --- /dev/null +++ b/drivers/input/touchscreen/nt36xxx.c @@ -0,0 +1,893 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for Novatek NT36xxx series touchscreens + * + * Copyright (C) 2010 - 2017 Novatek, Inc. + * Copyright (C) 2020 AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* FW Param address */ +#define NT36XXX_FW_ADDR 0x01 + +/* Number of bytes for chip identification */ +#define NT36XXX_ID_LEN_MAX 6 + +/* Touch info */ +#define TOUCH_DEFAULT_MAX_WIDTH 1080 +#define TOUCH_DEFAULT_MAX_HEIGHT 2246 +#define TOUCH_MAX_FINGER_NUM 10 +#define TOUCH_MAX_PRESSURE 1000 + +/* Point data length */ +#define POINT_DATA_LEN 65 + +/* Global pages */ +#define NT36XXX_PAGE_CHIP_INFO 0x0001f64e +#define NT36XXX_PAGE_CRC 0x0003f135 + +/* Misc */ +#define NT36XXX_NUM_SUPPLIES 2 +#define NT36XXX_MAX_RETRIES 5 +#define NT36XXX_MAX_FW_RST_RETRY 50 + +struct nt36xxx_abs_object { + u16 x; + u16 y; + u16 z; + u8 tm; +}; + +struct nt36xxx_fw_info { + u8 fw_ver; + u8 x_num; + u8 y_num; + u8 max_buttons; + u16 abs_x_max; + u16 abs_y_max; + u16 nvt_pid; +}; + +struct nt36xxx_mem_map { + u32 evtbuf_addr; + u32 pipe0_addr; + u32 pipe1_addr; + u32 flash_csum_addr; + u32 flash_data_addr; +}; + +struct nt36xxx_i2c { + struct i2c_client *hw_client; + struct i2c_client *fw_client; + struct regmap *regmap; + struct regmap *fw_regmap; + struct input_dev *input; + struct regulator_bulk_data *supplies; + struct gpio_desc *reset_gpio; + + struct mutex lock; + + struct touchscreen_properties prop; + struct nt36xxx_fw_info fw_info; + struct nt36xxx_abs_object abs_obj; + + const struct nt36xxx_mem_map *mmap; +}; + +enum nt36xxx_chips { + NT36525_IC = 0, + NT36672A_IC, + NT36676F_IC, + NT36772_IC, + NT36870_IC, + NTMAX_IC, +}; + +struct nt36xxx_trim_table { + u8 id[NT36XXX_ID_LEN_MAX]; + u8 mask[NT36XXX_ID_LEN_MAX]; + enum nt36xxx_chips mapid; +}; + +enum nt36xxx_cmds { + NT36XXX_CMD_ENTER_SLEEP = 0x11, + NT36XXX_CMD_ENTER_WKUP_GESTURE = 0x13, + NT36XXX_CMD_UNLOCK = 0x35, + NT36XXX_CMD_BOOTLOADER_RESET = 0x69, + NT36XXX_CMD_SW_RESET = 0xa5, + NT36XXX_CMD_SET_PAGE = 0xff, +}; + +/** + * enum nt36xxx_fw_state - Firmware state + * @NT36XXX_STATE_INIT: IC Reset + * @NT36XXX_STATE_REK: ReK baseline + * @NT36XXX_STATE_REK_FINISH: Baseline is ready + * @NT36XXX_STATE_NORMAL_RUN: Firmware is running + */ +enum nt36xxx_fw_state { + NT36XXX_STATE_INIT = 0xa0, + NT36XXX_STATE_REK, + NT36XXX_STATE_REK_FINISH, + NT36XXX_STATE_NORMAL_RUN, + NT36XXX_STATE_MAX = 0xaf +}; + +enum nt36xxx_i2c_events { + NT36XXX_EVT_REPORT = 0x00, + NT36XXX_EVT_CRC = 0x35, + NT36XXX_EVT_CHIPID = 0x4e, + NT36XXX_EVT_HOST_CMD = 0x50, + NT36XXX_EVT_HS_OR_SUBCMD = 0x51, /* Handshake or subcommand byte */ + NT36XXX_EVT_RESET_COMPLETE = 0x60, + NT36XXX_EVT_FWINFO = 0x78, + NT36XXX_EVT_PROJECTID = 0x9a, +}; + +static const struct nt36xxx_mem_map nt36xxx_memory_maps[] = { + [NT36525_IC] = { 0x11a00, 0x10000, 0x12000, 0x14000, 0x14002 }, + [NT36672A_IC] = { 0x21c00, 0x20000, 0x23000, 0x24000, 0x24002 }, + [NT36676F_IC] = { 0x11a00, 0x10000, 0x12000, 0x14000, 0x14002 }, + [NT36772_IC] = { 0x11e00, 0x10000, 0x12000, 0x14000, 0x14002 }, + [NT36870_IC] = { 0x25000, 0x20000, 0x23000, 0x24000, 0x24002 }, +}; + +static const struct nt36xxx_trim_table trim_id_table[] = { + { + .id = { 0x0A, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 1, 0, 0, 1, 1, 1 }, + .mapid = NT36672A_IC, + }, + { + .id = { 0x55, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0x55, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xAA, 0x00, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xAA, 0x72, 0xFF, 0x00, 0x00, 0x00 }, + .mask = { 1, 1, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x67, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x72, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x25, 0x65, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x70, 0x68, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36772_IC, + }, + { + .id = { 0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x03 }, + .mask = { 0, 0, 0, 1, 1, 1 }, + .mapid = NT36676F_IC, + }, +}; + +/** + * nt36xxx_set_page - Set page number for read/write + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_set_page(struct nt36xxx_i2c *ts, u32 pageaddr) +{ + u32 data = cpu_to_be32(pageaddr) >> 8; + int ret; + + ret = regmap_noinc_write(ts->fw_regmap, NT36XXX_CMD_SET_PAGE, + &data, sizeof(data)); + if (ret) + return ret; + + usleep_range(100, 200); + return ret; +} + +/** + * nt36xxx_sw_reset_idle - Warm restart the firmware + * @ts: Main driver structure + * + * This function restarts the running firmware without rebooting to + * the bootloader (warm restart) + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_sw_reset_idle(struct nt36xxx_i2c *ts) +{ + int ret; + + ret = regmap_write(ts->regmap, ts->hw_client->addr, + NT36XXX_CMD_SW_RESET); + if (ret) + return ret; + + /* Wait until the MCU resets the fw state */ + usleep_range(15000, 16000); + return ret; +} + +/** + * nt36xxx_bootloader_reset - Reset MCU to bootloader + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_bootloader_reset(struct nt36xxx_i2c *ts) +{ + int ret; + + ret = regmap_write(ts->regmap, ts->hw_client->addr, + NT36XXX_CMD_BOOTLOADER_RESET); + if (ret) + return ret; + + /* MCU has to reboot from bootloader: this is the typical boot time */ + msleep(35); + return ret; +} + +/** + * nt36xxx_check_reset_state - Check the boot state during reset + * @ts: Main driver structure + * @fw_state: Enumeration containing firmware states + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_check_reset_state(struct nt36xxx_i2c *ts, + enum nt36xxx_fw_state fw_state) +{ + u8 buf[2] = { 0 }; + int ret, retry = NT36XXX_MAX_FW_RST_RETRY; + + do { + ret = regmap_noinc_read(ts->fw_regmap, + NT36XXX_EVT_RESET_COMPLETE, + buf, sizeof(buf)); + if (likely(ret == 0) && + (buf[0] >= fw_state) && + (buf[0] <= NT36XXX_STATE_MAX)) { + ret = 0; + break; + } + usleep_range(10000, 11000); + } while (--retry); + + if (!retry) { + dev_err(&ts->hw_client->dev, "Firmware reset failed.\n"); + ret = -EBUSY; + } + + return ret; +} + +/** + * nt36xxx_read_pid - Read Novatek Project ID + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_read_pid(struct nt36xxx_i2c *ts) +{ + __be16 pid; + int ret; + + ret = nt36xxx_set_page(ts, ts->mmap->evtbuf_addr); + if (ret) + return ret; + + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_PROJECTID, + &pid, sizeof(pid)); + if (ret < 0) + return ret; + + ts->fw_info.nvt_pid = be16_to_cpu(pid); + return 0; +} + +/** + * __nt36xxx_get_fw_info - Get working params from firmware + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static int __nt36xxx_get_fw_info(struct nt36xxx_i2c *ts) +{ + struct nt36xxx_fw_info *fwi = &ts->fw_info; + u8 buf[11] = { 0 }; + int ret = 0; + + ret = nt36xxx_set_page(ts, ts->mmap->evtbuf_addr); + if (ret) + return ret; + + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_FWINFO, + buf, sizeof(buf)); + if (ret) + return ret; + + fwi->fw_ver = buf[0]; + fwi->x_num = buf[2]; + fwi->y_num = buf[3]; + fwi->abs_x_max = get_unaligned_be16(&buf[4]); + fwi->abs_y_max = get_unaligned_be16(&buf[6]); + fwi->max_buttons = buf[10]; + + /* Check fw info integrity and clear x_num, y_num if broken */ + if ((buf[0] + buf[1]) != 0xFF) { + dev_err(&ts->hw_client->dev, + "FW info is broken! fw_ver=0x%02X, ~fw_ver=0x%02X\n", + buf[0], buf[1]); + fwi->fw_ver = 0; + fwi->x_num = 18; + fwi->y_num = 32; + fwi->abs_x_max = TOUCH_DEFAULT_MAX_WIDTH; + fwi->abs_y_max = TOUCH_DEFAULT_MAX_HEIGHT; + fwi->max_buttons = 0; + return -EINVAL; + } + + /* Get Novatek ProjectID */ + return nt36xxx_read_pid(ts); +} + +static int nt36xxx_get_fw_info(struct nt36xxx_i2c *ts) +{ + struct nt36xxx_fw_info *fwi = &ts->fw_info; + int i, ret = 0; + + for (i = 0; i < NT36XXX_MAX_RETRIES; i++) { + ret = __nt36xxx_get_fw_info(ts); + if (ret == 0) + break; + } + + dev_dbg(&ts->hw_client->dev, + "FW Info: PID=0x%x, ver=0x%x res=%ux%u max=%ux%u buttons=%u", + fwi->nvt_pid, fwi->fw_ver, fwi->x_num, fwi->y_num, + fwi->abs_x_max, fwi->abs_y_max, fwi->max_buttons); + + return ret; +} + +/** + * nt36xxx_report - Report touch events + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static void nt36xxx_report(struct nt36xxx_i2c *ts) +{ + struct nt36xxx_abs_object *obj = &ts->abs_obj; + struct input_dev *input = ts->input; + u8 input_id = 0; + u8 point[POINT_DATA_LEN + 1] = { 0 }; + unsigned int ppos = 0; + int i, ret, finger_cnt = 0; + + mutex_lock(&ts->lock); + + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_REPORT, + point, sizeof(point)); + if (ret < 0) { + dev_err(&ts->hw_client->dev, + "Cannot read touch point data: %d\n", ret); + goto xfer_error; + } + + for (i = 0; i < TOUCH_MAX_FINGER_NUM; i++) { + ppos = 6 * i; + input_id = point[ppos + 0] >> 3; + if ((input_id == 0) || (input_id > TOUCH_MAX_FINGER_NUM)) + continue; + + if (((point[ppos] & 0x07) == 0x01) || + ((point[ppos] & 0x07) == 0x02)) { + obj->x = (point[ppos + 1] << 4) + + (point[ppos + 3] >> 4); + obj->y = (point[ppos + 2] << 4) + + (point[ppos + 3] & 0xf); + if ((obj->x > ts->prop.max_x) || + (obj->y > ts->prop.max_y)) + continue; + + obj->tm = point[ppos + 4]; + if (obj->tm == 0) + obj->tm = 1; + + obj->z = point[ppos + 5]; + if (i < 2) { + obj->z += point[i + 63] << 8; + if (obj->z > TOUCH_MAX_PRESSURE) + obj->z = TOUCH_MAX_PRESSURE; + } + + if (obj->z == 0) + obj->z = 1; + + input_mt_slot(input, input_id - 1); + input_mt_report_slot_state(input, + MT_TOOL_FINGER, true); + touchscreen_report_pos(input, &ts->prop, obj->x, + obj->y, true); + + input_report_abs(input, ABS_MT_TOUCH_MAJOR, obj->tm); + input_report_abs(input, ABS_MT_PRESSURE, obj->z); + + finger_cnt++; + } + } + input_mt_sync_frame(input); + input_sync(input); + +xfer_error: + enable_irq(ts->hw_client->irq); + + mutex_unlock(&ts->lock); +} + +static irqreturn_t nt36xxx_i2c_irq_handler(int irq, void *dev_id) +{ + struct nt36xxx_i2c *ts = dev_id; + + disable_irq_nosync(ts->hw_client->irq); + nt36xxx_report(ts); + + return IRQ_HANDLED; +} + +static bool nt36xxx_in_crc_reboot_loop(u8 *buf) +{ + return ((buf[0] == 0xFC) && (buf[1] == 0xFC) && (buf[2] == 0xFC)) || + ((buf[0] == 0xFF) && (buf[1] == 0xFF) && (buf[2] == 0xFF)); +} + +/** + * nt36xxx_stop_crc_reboot - Stop CRC reboot loop and warm-reboot the firmware + * @ts: Main driver structure + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_stop_crc_reboot(struct nt36xxx_i2c *ts) +{ + u8 buf[3] = { 0 }; + u8 val; + int ret, retry = NT36XXX_MAX_RETRIES; + + /* Read dummy buffer to check CRC fail reboot is happening or not */ + + /* Change I2C index to prevent getting 0xFF, but not 0xFC */ + ret = nt36xxx_set_page(ts, NT36XXX_PAGE_CHIP_INFO); + if (ret) { + dev_dbg(&ts->hw_client->dev, + "CRC reset failed: Cannot select page.\n"); + return ret; + } + + /* If ChipID command returns 0xFC or 0xFF, the MCU is in CRC reboot */ + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_CHIPID, + buf, sizeof(buf)); + if (ret) + return ret; + + if (!nt36xxx_in_crc_reboot_loop(buf)) + return 0; + + /* IC is in CRC fail reboot loop, needs to be stopped! */ + do { + /* Special reset-idle sequence for CRC failure */ + ret = regmap_write(ts->regmap, ts->hw_client->addr, + NT36XXX_CMD_SW_RESET); + if (ret) + dev_dbg(&ts->hw_client->dev, + "SW Reset 1 failed: may not recover\n"); + + ret = regmap_write(ts->regmap, ts->hw_client->addr, + NT36XXX_CMD_SW_RESET); + if (ret) + dev_dbg(&ts->hw_client->dev, + "SW Reset 2 failed: may not recover\n"); + usleep_range(1000, 1100); + + /* Clear CRC_ERR_FLAG */ + ret = nt36xxx_set_page(ts, NT36XXX_PAGE_CRC); + if (ret) + continue; + + val = 0xA5; + ret = regmap_raw_write(ts->fw_regmap, NT36XXX_EVT_CRC, + &val, sizeof(val)); + if (ret) + continue; + + /* Check CRC_ERR_FLAG */ + ret = nt36xxx_set_page(ts, NT36XXX_PAGE_CRC); + if (ret) + continue; + + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_CRC, + &buf, sizeof(buf)); + if (ret) + continue; + + if (buf[0] == 0xA5) + break; + } while (--retry); + + if (retry == 0) { + dev_err(&ts->hw_client->dev, + "CRC reset failed: buf=0x%2ph\n", buf); + } + + return ret; +} + +/** + * nt36xxx_i2c_chip_version_init - Detect Novatek NT36xxx family IC + * @ts: Main driver structure + * + * This function reads the ChipID from the IC and sets the right + * memory map for the detected chip. + * + * Return: Always zero for success, negative number for error + */ +static int nt36xxx_i2c_chip_version_init(struct nt36xxx_i2c *ts) +{ + u8 buf[7] = { 0 }; + int retry = NT36XXX_MAX_RETRIES; + int sz = sizeof(trim_id_table) / sizeof(struct nt36xxx_trim_table); + int i, list, mapid, ret; + + ret = nt36xxx_bootloader_reset(ts); + if (ret) { + dev_err(&ts->hw_client->dev, "Can't reset the nvt IC\n"); + return ret; + } + + do { + ret = nt36xxx_sw_reset_idle(ts); + if (ret) + continue; + + ret = regmap_write(ts->regmap, ts->hw_client->addr, NT36XXX_CMD_UNLOCK); + if (ret) + continue; + usleep_range(10000, 11000); + + ret = nt36xxx_set_page(ts, NT36XXX_PAGE_CHIP_INFO); + if (ret) + continue; + + memset(buf, 0, ARRAY_SIZE(buf)); + ret = regmap_noinc_read(ts->fw_regmap, NT36XXX_EVT_CHIPID, + buf, sizeof(buf)); + if (ret) + continue; + + /* Compare read chip id with trim list */ + for (list = 0; list < sz; list++) { + /* Compare each not masked byte */ + for (i = 0; i < NT36XXX_ID_LEN_MAX; i++) { + if (trim_id_table[list].mask[i] && + buf[i] != trim_id_table[list].id[i]) + break; + } + + if (i == NT36XXX_ID_LEN_MAX) { + mapid = trim_id_table[list].mapid; + ts->mmap = &nt36xxx_memory_maps[mapid]; + return 0; + } + + ts->mmap = NULL; + ret = -ENOENT; + } + + /* Stop CRC check to prevent IC auto reboot */ + if (nt36xxx_in_crc_reboot_loop(buf)) { + ret = nt36xxx_stop_crc_reboot(ts); + if (ret) + continue; + } + + usleep_range(10000, 11000); + } while (--retry); + + return ret; +} + +static const struct regmap_config nt36xxx_i2c_regmap_hw_config = { + .name = "nt36xxx_i2c_hw", + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_NONE, +}; + +static const struct regmap_config nt36xxx_i2c_regmap_fw_config = { + .name = "nt36xxx_i2c_fw", + .reg_bits = 8, + .val_bits = 8, + .cache_type = REGCACHE_NONE, +}; + +static void nt36xxx_disable_regulators(void *data) +{ + struct nt36xxx_i2c *ts = data; + + regulator_bulk_disable(NT36XXX_NUM_SUPPLIES, ts->supplies); +} + +static int nt36xxx_i2c_probe(struct i2c_client *hw_client) +{ + struct nt36xxx_i2c *ts; + struct input_dev *input; + int ret; + + if (!i2c_check_functionality(hw_client->adapter, I2C_FUNC_I2C)) { + dev_err(&hw_client->dev, "i2c_check_functionality error\n"); + return -EIO; + } + + if (!hw_client->irq) { + dev_err(&hw_client->dev, "No irq specified\n"); + return -EINVAL; + } + + ts = devm_kzalloc(&hw_client->dev, sizeof(*ts), GFP_KERNEL); + if (!ts) + return -ENOMEM; + + ts->supplies = devm_kcalloc(&hw_client->dev, + NT36XXX_NUM_SUPPLIES, + sizeof(*ts->supplies), + GFP_KERNEL); + if (!ts->supplies) + return -ENOMEM; + + input = devm_input_allocate_device(&hw_client->dev); + if (!input) + return -ENOMEM; + + ts->fw_client = i2c_new_dummy_device(hw_client->adapter, + NT36XXX_FW_ADDR); + if (IS_ERR(ts->fw_client)) { + dev_err(&hw_client->dev, "Cannot add FW I2C device\n"); + return PTR_ERR(ts->fw_client); + } + + ts->hw_client = hw_client; + ts->input = input; + i2c_set_clientdata(ts->hw_client, ts); + i2c_set_clientdata(ts->fw_client, ts); + + ts->reset_gpio = devm_gpiod_get_optional(&hw_client->dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(ts->reset_gpio)) + return PTR_ERR(ts->reset_gpio); + gpiod_set_consumer_name(ts->reset_gpio, "nt36xxx reset"); + + /* These supplies are optional */ + ts->supplies[0].supply = "vdd"; + ts->supplies[1].supply = "vio"; + ret = devm_regulator_bulk_get(&hw_client->dev, + NT36XXX_NUM_SUPPLIES, + ts->supplies); + if (ret) + return dev_err_probe(&hw_client->dev, ret, + "Cannot get supplies: %d\n", ret); + + ts->regmap = devm_regmap_init_i2c(ts->hw_client, + &nt36xxx_i2c_regmap_hw_config); + if (IS_ERR(ts->regmap)) { + dev_err(&hw_client->dev, "regmap (hw-addr) init failed\n"); + return PTR_ERR(ts->regmap); + } + + ts->fw_regmap = devm_regmap_init_i2c(ts->fw_client, + &nt36xxx_i2c_regmap_fw_config); + if (IS_ERR(ts->fw_regmap)) { + dev_err(&hw_client->dev, "regmap (fw-addr) init failed\n"); + return PTR_ERR(ts->fw_regmap); + } + + ret = regulator_bulk_enable(NT36XXX_NUM_SUPPLIES, ts->supplies); + if (ret) + return ret; + + usleep_range(10000, 11000); + + ret = devm_add_action_or_reset(&hw_client->dev, + nt36xxx_disable_regulators, ts); + if (ret) + return ret; + + mutex_init(&ts->lock); + + /* Set memory maps for the specific chip version */ + ret = nt36xxx_i2c_chip_version_init(ts); + if (ret) { + dev_err(&hw_client->dev, "Failed to check chip version\n"); + return ret; + } + + /* Reset the MCU */ + ret = nt36xxx_bootloader_reset(ts); + if (ret < 0) + return ret; + + /* Check and eventually wait until the MCU goes in reset state */ + ret = nt36xxx_check_reset_state(ts, NT36XXX_STATE_INIT); + if (ret < 0) + return ret; + + /* Get informations from the TS firmware */ + ret = nt36xxx_get_fw_info(ts); + if (ret < 0) + return ret; + + input->phys = devm_kasprintf(&hw_client->dev, GFP_KERNEL, + "%s/input0", dev_name(&hw_client->dev)); + if (!input->phys) + return -ENOMEM; + + input->name = "Novatek NT36XXX Touchscreen"; + input->id.bustype = BUS_I2C; + input->dev.parent = &hw_client->dev; + + __set_bit(EV_KEY, input->evbit); + __set_bit(EV_ABS, input->evbit); + input_set_capability(input, EV_KEY, BTN_TOUCH); + + ret = input_mt_init_slots(input, TOUCH_MAX_FINGER_NUM, + INPUT_MT_DIRECT | INPUT_MT_DROP_UNUSED); + if (ret) { + dev_err(&hw_client->dev, "Cannot init MT slots (%d)\n", ret); + return ret; + } + + input_set_abs_params(input, ABS_MT_PRESSURE, 0, + TOUCH_MAX_PRESSURE, 0, 0); + input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); + + input_set_abs_params(input, ABS_MT_POSITION_X, 0, + ts->fw_info.abs_x_max - 1, 0, 0); + input_set_abs_params(input, ABS_MT_POSITION_Y, 0, + ts->fw_info.abs_y_max - 1, 0, 0); + + /* Override the firmware defaults, if needed */ + touchscreen_parse_properties(input, true, &ts->prop); + + input_set_drvdata(input, ts); + + ret = input_register_device(ts->input); + if (ret) { + dev_err(&hw_client->dev, "Failed to register input device: %d\n", + ret); + return ret; + } + + ret = devm_request_threaded_irq(&hw_client->dev, hw_client->irq, NULL, + nt36xxx_i2c_irq_handler, IRQF_ONESHOT, + hw_client->name, ts); + if (ret) { + dev_err(&hw_client->dev, "request irq failed: %d\n", ret); + return ret; + } + + return ret; +} + +static int __maybe_unused nt36xxx_i2c_suspend(struct device *dev) +{ + struct nt36xxx_i2c *ts = i2c_get_clientdata(to_i2c_client(dev)); + int ret; + + disable_irq(ts->hw_client->irq); + + ret = regmap_write(ts->fw_regmap, NT36XXX_EVT_HOST_CMD, + NT36XXX_CMD_ENTER_SLEEP); + if (ret) { + dev_err(&ts->hw_client->dev, "Cannot enter suspend!!\n"); + return ret; + } + + gpiod_set_value(ts->reset_gpio, 1); + + return 0; +} + +static int __maybe_unused nt36xxx_i2c_resume(struct device *dev) +{ + struct nt36xxx_i2c *ts = i2c_get_clientdata(to_i2c_client(dev)); + int ret; + + mutex_lock(&ts->lock); + + gpiod_set_value(ts->reset_gpio, 0); + + /* Reboot the MCU (also recalibrates the TS) */ + ret = nt36xxx_bootloader_reset(ts); + if (ret < 0) + goto end; + + ret = nt36xxx_check_reset_state(ts, NT36XXX_STATE_REK); + if (ret < 0) + goto end; + + enable_irq(ts->hw_client->irq); +end: + mutex_unlock(&ts->lock); + return ret; +} + +static SIMPLE_DEV_PM_OPS(nt36xxx_i2c_pm, + nt36xxx_i2c_suspend, nt36xxx_i2c_resume); + +static const struct of_device_id nt36xxx_of_match[] = { + { .compatible = "novatek,nt36525" }, + { } +}; +MODULE_DEVICE_TABLE(of, nt36xxx_of_match); + +static const struct i2c_device_id nt36xxx_i2c_ts_id[] = { + { "NVT-ts", 0 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, nt36xxx_i2c_ts_id); + +static struct i2c_driver nt36xxx_i2c_ts_driver = { + .driver = { + .name = "nt36xxx_ts", + .pm = &nt36xxx_i2c_pm, + .of_match_table = nt36xxx_of_match, + }, + .id_table = nt36xxx_i2c_ts_id, + .probe = nt36xxx_i2c_probe, +}; +module_i2c_driver(nt36xxx_i2c_ts_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Novatek NT36XXX Touchscreen Driver"); +MODULE_AUTHOR("AngeloGioacchino Del Regno "); diff --git a/drivers/input/touchscreen/nt36xxx.h b/drivers/input/touchscreen/nt36xxx.h new file mode 100644 index 00000000000000..6f03dfb456567a --- /dev/null +++ b/drivers/input/touchscreen/nt36xxx.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2010 - 2017 Novatek, Inc. + * Copyright (C) 2020 AngeloGioacchino Del Regno + */ + +#ifndef NT36XXX_H +#define NT36XXX_H + +#define NT36XXX_INPUT_DEVICE_NAME "Novatek NT36XXX Touch Sensor" + +/* These chips have this fixed address when in bootloader :( */ +#define NT36XXX_BLDR_ADDR 0x01 + +/* Input device info */ +#define NVT_TS_NAME "NVTCapacitiveTouchScreen" + +/* Number of bytes for chip identification */ +#define NT36XXX_ID_LEN_MAX 6 + +/* Touch info */ +#define TOUCH_DEFAULT_MAX_WIDTH 1080 +#define TOUCH_DEFAULT_MAX_HEIGHT 2246 +#define TOUCH_MAX_FINGER_NUM 10 +#define TOUCH_MAX_PRESSURE 1000 + +/* Point data length */ +#define POINT_DATA_LEN 65 + +/* Global pages */ +#define NT36XXX_PAGE_CHIP_INFO 0x0001f64e +#define NT36XXX_PAGE_CRC 0x0003f135 + +/* Misc */ +#define NT36XXX_NUM_SUPPLIES 2 +#define NT36XXX_MAX_RETRIES 5 +#define NT36XXX_MAX_FW_RST_RETRY 50 + +struct nt36xxx_abs_object { + u16 x; + u16 y; + u16 z; + u8 tm; +}; + +struct nt36xxx_fw_info { + u8 fw_ver; + u8 x_num; + u8 y_num; + u8 max_buttons; + u16 abs_x_max; + u16 abs_y_max; + u16 nvt_pid; +}; + +struct nt36xxx_mem_map { + u32 evtbuf_addr; + u32 pipe0_addr; + u32 pipe1_addr; + u32 flash_csum_addr; + u32 flash_data_addr; +}; + +struct nt36xxx_i2c { + struct i2c_client *client; + struct input_dev *input; + struct regulator_bulk_data *supplies; + struct gpio_desc *reset_gpio; + + struct work_struct ts_work; + struct workqueue_struct *ts_workq; + struct mutex lock; + + struct nt36xxx_fw_info fw_info; + struct nt36xxx_abs_object abs_obj; + + const struct nt36xxx_mem_map *mmap; + u8 max_fingers; +}; + +enum nt36xxx_chips { + NT36525_IC = 0, + NT36672A_IC, + NT36676F_IC, + NT36772_IC, + NT36870_IC, + NTMAX_IC, +}; + +struct nt36xxx_trim_table { + u8 id[NT36XXX_ID_LEN_MAX]; + u8 mask[NT36XXX_ID_LEN_MAX]; + enum nt36xxx_chips mapid; +}; + +enum nt36xxx_cmds { + NT36XXX_CMD_ENTER_SLEEP = 0x11, + NT36XXX_CMD_ENTER_WKUP_GESTURE = 0x13, + NT36XXX_CMD_UNLOCK = 0x35, + NT36XXX_CMD_BOOTLOADER_RESET = 0x69, + NT36XXX_CMD_SW_RESET = 0xa5, + NT36XXX_CMD_SET_PAGE = 0xff, +}; + +enum nt36xxx_fw_state { + NT36XXX_STATE_INIT = 0xa0, /* IC reset */ + NT36XXX_STATE_REK, /* ReK baseline */ + NT36XXX_STATE_REK_FINISH, /* Baseline is ready */ + NT36XXX_STATE_NORMAL_RUN, /* Normal run */ + NT36XXX_STATE_MAX = 0xaf +}; + +enum nt36xxx_i2c_events { + NT36XXX_EVT_CHIPID = 0x4e, + NT36XXX_EVT_HOST_CMD = 0x50, + NT36XXX_EVT_HS_OR_SUBCMD = 0x51, /* Handshake or subcommand byte */ + NT36XXX_EVT_RESET_COMPLETE = 0x60, + NT36XXX_EVT_FWINFO = 0x78, + NT36XXX_EVT_PROJECTID = 0x9a, +}; + +#endif From 13ac201a35783207ccc6069106b9309e12f2712e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 28 Oct 2020 23:13:02 +0100 Subject: [PATCH 011/143] dt-bindings: touchscreen: Add binding for Novatek NT36xxx series driver Add binding for the Novatek NT36xxx series touchscreen driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- .../bindings/input/touchscreen/nt36xxx.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/input/touchscreen/nt36xxx.yaml diff --git a/Documentation/devicetree/bindings/input/touchscreen/nt36xxx.yaml b/Documentation/devicetree/bindings/input/touchscreen/nt36xxx.yaml new file mode 100644 index 00000000000000..a360a9f5d43b5f --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/nt36xxx.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/nt36xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT36xxx series touchscreen controller Bindings + +maintainers: + - AngeloGioacchino Del Regno + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + const: novatek,nt36525 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + vdd-supply: + description: Power supply regulator for VDD pin + + vio-supply: + description: Power supply regulator on VDD-IO pin + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@62 { + compatible = "novatek,nt36525"; + reg = <0x62>; + interrupt-parent = <&tlmm>; + interrupts = <45 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; + }; + }; + +... From 1c1d52a41c01d6fa4a3b75be7b79f2753cb6a87c Mon Sep 17 00:00:00 2001 From: iAboothahir Date: Sat, 26 Mar 2022 19:50:55 +0530 Subject: [PATCH 012/143] drm/panel-simple: Add NT36672_TXD FHD+ IPS LCD Panel Signed-off-by: Aboothahir U --- .../display/panel/panel-simple-dsi.yaml | 2 ++ drivers/gpu/drm/panel/panel-simple.c | 35 +++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 90c04cff828120..8a82a9a405d479 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -54,6 +54,8 @@ properties: - samsung,sofef00 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel - tdo,tl070wsh30 + # Asus Zenfone Max Pro M1 (x00td) nt36672_1080p_video_txd FHD+ IPS LCD Panel + - asus,nt36672-txd reg: maxItems: 1 diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 065f378bba9d22..f19d5d4999058c 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -4574,6 +4574,38 @@ static const struct panel_desc_dsi osd101t2045_53ts = { .lanes = 4, }; +static const struct drm_display_mode nt36672_txd_mode = { + .clock = (1080 + 122 + 8 + 76) * (2160 + 20 + 4 + 28) * 60 / 1000, + .hdisplay = 1080, + .hsync_start = 1080 + 122, + .hsync_end = 1080 + 122 + 8, + .htotal = 1080 + 122 + 8 + 76, + .vdisplay = 2160, + .vsync_start = 2160 + 20, + .vsync_end = 2160 + 20 + 4, + .vtotal = 2160 + 20 + 4 + 28, + .width_mm = 68, + .height_mm = 136, +}; + +static const struct panel_desc_dsi nt36672_txd = { + .desc = { + .modes = &nt36672_txd_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 68, + .height = 136, + }, + .connector_type = DRM_MODE_CONNECTOR_DSI, + }, + .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_NO_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS | MIPI_DSI_MODE_LPM, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 4, +}; + static const struct of_device_id dsi_of_match[] = { { .compatible = "auo,b080uan01", @@ -4596,6 +4628,9 @@ static const struct of_device_id dsi_of_match[] = { }, { .compatible = "osddisplays,osd101t2045-53ts", .data = &osd101t2045_53ts + }, { + .compatible = "asus,nt36672-txd", + .data = &nt36672_txd }, { /* sentinel */ } From 23dfbbfeff66d53c7787a8ff170b22d6fe4fbc1a Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Sat, 26 Mar 2022 20:00:45 +0530 Subject: [PATCH 013/143] ath10k: Fake MSA ready event after event server arrival This finally allowed me to get past the 2 ath10k_info()'s in qmi.c! However, this doesn't fix everything; it seems you *have* to run diag-router from https://github.com/andersson/diag to calm the firmware down and stop constantly crashing; need to look into a way to get Wi-Fi working later without needing this debug crap to be running. link: https://github.com/JamiKettunen/linux-mainline-oneplus5/commit/088eaa9153803e2b028e092f88539036442da4a3 Signed-off-by: Jami Kettunen --- drivers/net/wireless/ath/ath10k/qmi.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/wireless/ath/ath10k/qmi.c b/drivers/net/wireless/ath/ath10k/qmi.c index 038c5903c0dc15..5433f7c5b970f8 100644 --- a/drivers/net/wireless/ath/ath10k/qmi.c +++ b/drivers/net/wireless/ath/ath10k/qmi.c @@ -1039,6 +1039,8 @@ static void ath10k_qmi_driver_event_work(struct work_struct *work) switch (event->type) { case ATH10K_QMI_EVENT_SERVER_ARRIVE: ath10k_qmi_event_server_arrive(qmi); + // HACK: Fake MSA being ready + ath10k_qmi_event_msa_ready(qmi); break; case ATH10K_QMI_EVENT_SERVER_EXIT: ath10k_qmi_event_server_exit(qmi); From 9f2246f61a3e8b457ab3e4e99869adef71d88f47 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sun, 18 Oct 2020 16:10:41 +0200 Subject: [PATCH 014/143] gpu go 700mhz Signed-off-by: Marijn Suijten Signed-off-by: Aboothahir U --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 3b9223c0be187d..014237d4b5b243 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1065,6 +1065,20 @@ gpu_sdm630_opp_table: opp-table { compatible = "operating-points-v2"; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-peak-kBps = <5184000>; + opp-supported-hw = <0xFF>; + }; + + /* + * 775MHz is only available on default speed bin + * or 0xA2 (speed bin 1). Though it cannot be used + * for now due to interconnect framework not supporting + * multiple frequencies at the same opp-level + opp-775000000 { opp-hz = /bits/ 64 <775000000>; opp-level = ; @@ -1107,6 +1121,7 @@ opp-peak-kBps = <1200000>; opp-supported-hw = <0xff>; }; + */ }; }; From b94ff0cacbdb2c7a38860d832ad34f0dcf457abc Mon Sep 17 00:00:00 2001 From: iAboothahir Date: Sun, 27 Mar 2022 11:46:08 +0530 Subject: [PATCH 015/143] arm64: dts: qcom: Add initial support for asus-x00td Initial support for Asus Zenfone Max Pro M1 (SDM636) * Currently works -Simple-framebuffer -eMMC,SDCard -Power Button -Volume-keys -Wifi(Partial) -Bluetooth -Touchscreen-NT36XXX -Display -GPU(Partial) -USB Signed-off-by: Aboothahir U --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/sdm636-asus-x00td.dts | 740 ++++++++++++++++++ 2 files changed, 741 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d42c59572ace0f..3640fa8eb13ab9 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -150,6 +150,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm636-asus-x00td.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts b/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts new file mode 100644 index 00000000000000..f9f657a42a839b --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm636-asus-x00td.dts @@ -0,0 +1,740 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022, Aboothahir U + */ + +/dts-v1/; + +#include "sdm636.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" +#include +#include + +/delete-node/ &qhee_code; +/delete-node/ &smem_region; +/delete-node/ &tz_mem; +/delete-node/ &mpss_region; +/delete-node/ &mba_region; +/delete-node/ &adsp_region; +/delete-node/ &buffer_mem; +/delete-node/ &zap_shader_region; + +/ { + model = "Asus Zenfone Max Pro M1"; + compatible = "asus,x00td", "qcom,sdm660", "qcom, sdm636"; + chassis-type = "handset"; + + qcom,msm-id = <0x159 0x0>; + qcom,board-id = <0x1000b 0x0>; + qcom,pmic-id = <0x1001b 0x101011a 0x0 0x0 0x1001b 0x201011a 0x0 0x0 0x1001b 0x102001a 0x0 0x0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "framebuffer0"; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>; + status = "okay"; + width = <1080>; + height = <2160>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + status = "okay"; + compatible = "gpio-keys"; + + vol_up { + label = "Volume Up"; + gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + vol_down { + label = "Volume Down"; + gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + wlan_msa_guard: wlan-msa-guard@85600000 { + reg = <0x0 0x85600000 0x0 0x100000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-mem@85700000 { + reg = <0x0 0x85700000 0x0 0x100000>; + no-map; + }; + + /* removed_regions in downstream / qhee_code */ + removed_region: removed_region@85800000 { + reg = <0x0 0x85800000 0x0 0x600000>; + no-map; + }; + + smem_region: smem_memory@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + /* tz_mem */ + tz_mem: tz_memory@86200000 { + reg = <0x0 0x86200000 0x0 0x2D00000>; + /* 0x86200000 + 0x2D00000 = 0x88F00000 */ + no-map; + }; + + /* downstream has this: */ + /* removed_regions@85800000 { + reg = <0x0 0x85800000 0x0 0x3700000>; + no-map; + }; */ + /* which covers region starting from removed_regions to 0x88F00000 (end of our tz_mem) */ + + /* modem_fw_region */ + modem_fw_mem: modem_fw_region@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0x7e00000>; + no-map; + }; + + /* adsp_fw_region */ + adsp_region: adsp@92a00000 { + reg = <0x0 0x92a00000 0x0 0x1e00000>; + no-map; + }; + + /* pil_mba_mem */ + pil_mba_mem: mba@94800000 { + reg = <0x0 0x94800000 0x0 0x200000>; + no-map; + }; + + /* cdsp_fw_region */ + buffer_mem: buffer_region@94a00000 { + reg = <0x0 0x94a00000 0x0 0x600000>; + no-map; + }; + + /* cont_splash_region / framebuffer */ + cont_splash: splash_region@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + zap_shader_region: gpu@fa800000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xfa800000 0x0 0x2000>; + no-map; + }; + + ramoops@a0000000 { + compatible = "ramoops"; + reg = <0x0 0xa0000000 0x0 0x400000>; + console-size = <0x20000>; + record-size = <0x20000>; + ftrace-size = <0x0>; + pmsg-size = <0x20000>; + }; + }; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + regulator-always-on; + regulator-boot-on; + }; + + /* Add support of modem and Wi-Fi */ + soc { + /* + * We don't know origin of remoteproc + * description now, it was provided on Github + * by konradybcio/58ninges_labs + */ + remoteproc_mss: remoteproc@4080000 { + compatible = "qcom,msm8998-mss-pil"; + reg = <0x04080000 0x100>, <0x04180000 0x40>; + reg-names = "qdsp6", "rmb"; + status = "okay"; + + interrupts-extended = + <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&gcc GPLL0_OUT_MSSCC>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&rpmcc RPM_SMD_QDSS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "bus", "mem", "gpll0_mss", + "snoc_axi", "mnoc_axi", "qdss", "xo"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; + + power-domains = <&rpmpd SDM660_VDDCX>, + <&rpmpd SDM660_VDDMX>; + power-domain-names = "cx", "mx"; + + /* firmware from device */ + firmware-name = "mba.mbn", "modem.mdt"; + + /* modem regions */ + mba { + memory-region = <&pil_mba_mem>; + }; + + mpss { + memory-region = <&modem_fw_mem>; + }; + + glink-edge { + interrupts = ; + label = "modem"; + qcom,remote-pid = <1>; + mboxes = <&apcs_glb 15>; + }; + }; + + wifi: wifi@18800000 { + /* + * Generated from ICNSS - they have same + * membase, clocks, iommus and interrupts + * However, SMMU not working now :( + */ + compatible = "qcom,wcn3990-wifi"; /* common for all QCOMs */ + reg = <0x18800000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; + clock-names = "cxo_ref_clk_pin"; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + ; + + iommus = <&anoc2_smmu 0x1a00>, + <&anoc2_smmu 0x1a01>; + qcom,snoc-host-cap-8bit-quirk; /* unknown property */ + status = "okay"; + + /* supplies are same with downstream */ + vdd-1.8-xo-supply = <&vreg_l9a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l6a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l19a_3p3>; + }; + }; +}; + +&blsp2_uart1 { + status = "okay"; + /* HCI Bluetooth */ + bluetooth { + compatible = "qcom,wcn3990-bt"; // common for all QCOM + vddxo-supply = <&vreg_l9a_1p8>; // downstream: vdd-core-supply + vddrf-supply = <&vreg_l6a_1p3>; // vdd-pa-supply + vddch0-supply = <&vreg_l19a_3p3>; // vdd-ldo-supply + max-speed = <3200000>; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + /* SDHCI 3.3V signal doesn't seem to be supported. */ + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + bus-width = <8>; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_2p95>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; + + panel_reset_gpio: panel-reset-gpio { + pins = "gpio53"; + function = "gpio"; + drive-strength = <8>; + bias-disable = <0>; + }; + + mdss_dsi_suspend: mdss-dsi-suspend { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + panel_te_gpio: panel-te-gpio { + pins = "gpio59"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; + +&qusb2phy0 { + status = "okay"; +}; + +&blsp_i2c2 { + status = "okay"; +}; + +&blsp_i2c4 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + touchscreen@62 { + compatible = "novatek,nt36525"; + reg = <0x62>; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; + }; +}; + +&blsp_i2c6 { + status = "okay"; + + tfa98xx@34 { + compatible = "nxp,tfa98xx"; + reg = <0x34>; + }; +}; + +&blsp_i2c7 { /* for P/L Sensor */ + status = "okay"; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&vreg_l1b_0p925>; + vdda-supply = <&vreg_l1a_1p225>; + status = "okay"; + panel@0 { + compatible = "asus,nt36672-txd"; + reg = <0>; + + backlight = <&pm660l_wled>; + //reset-gpios = <&tlmm XY GPIO_ACTIVE_LOW>; + reset-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + disp-te-gpios = <&tlmm 59 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_gpio &panel_te_gpio>; + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + data-lanes = <0 1 2 3>; + remote-endpoint = <&panel_in>; +}; + +&dsi0_phy { + vcca-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&pm660l_wled { + status = "okay"; + default-brightness = <512>; +}; + +&dsi1_phy{ + status = "disabled"; +}; + +&dsi1{ + status = "disabled"; +}; + +&gcc { + status = "okay"; +}; + +&gpucc { + status = "okay"; +}; + +&mmcc { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&anoc2_smmu { + status = "okay"; +}; + +&kgsl_smmu { + status = "okay"; +}; + +&lpass_smmu { + status = "okay"; +}; + + /* firmware from device */ + + +&adreno_gpu { + status = "okay"; + zap-shader { + memory-region = <&zap_shader_region>; + firmware-name = "qcom/a512_zap.mdt"; + }; + // These OPPs are correct, but we are lacking support for the + // GPU regulator. Hence, disable them for now to prevent the + // platform from hanging on high graphics loads + opp-table { + /delete-node/ opp-700000000; + /delete-node/ opp-266000000; + }; +}; + +&adsp_pil { + status = "okay"; + firmware-name = "adsp.mdt"; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/venus-4.4/venus.mdt"; +}; From 438e10d874069de728435b7feacd05b353bce223 Mon Sep 17 00:00:00 2001 From: Mark Hargreaves Date: Tue, 2 Mar 2021 17:05:18 +0200 Subject: [PATCH 016/143] arm64: dts: qcom: sdm660: Add initial support for xiaomi-clover Initial support for Xiaomi Mi Pad 4. Currently works: * simple-framebuffer * USB * touchscreen * GPIO buttons Signed-off-by: Mark Hargreaves --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm660-xiaomi-clover.dts | 518 ++++++++++++++++++ 2 files changed, 519 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-clover.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 3640fa8eb13ab9..7bb49465140fa6 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -152,6 +152,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-asus-x00td.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-clover.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-clover.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-clover.dts new file mode 100644 index 00000000000000..11bfdce4311672 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-clover.dts @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, Mark Hargreaves + */ + +/dts-v1/; +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" + +/ { + model = "Xiaomi Mi Pad 4"; + compatible = "xiaomi,clover", "qcom,sda660", "qcom,sda660-mtp", "qcom,mtp"; + qcom,board-id = <11 0>; + qcom,msm-id = <324 0>; + qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>, <0x0001001b 0x0201011a 0x0 0x0>,<0x0001001b 0x0102001a 0x0 0x0>; + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1200 * 1920 * 4)>; + width = <1200>; + height = <1920>; + stride = <(1200 * 4)>; + format = "a8r8g8b8"; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-always-on; + regulator-boot-on; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + gpio_keys { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + label = "Volume up"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_active>; + + vol-up { + label = "Volume up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + ramoops@9fe00000 { + compatible = "ramoops"; + reg = <0x0 0x9fe00000 0x0 0x400000>; + console-size = <0x20000>; + record-size = <0x20000>; + ftrace-size = <0x0>; + pmsg-size = <0x20000>; + }; + framebuffer_memory@9d400000 { + reg = <0x0 0x9d400000 0x0 (1200 * 1920 * 4)>; + no-map; + }; + }; + +}; + +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + /* + * This regulator supports 1.648 - 3.104V on this board + * but we set a max voltage of anything less than 2.7V + * to satisfy a condition in sdhci.c that will disable + * 3.3V SDHCI signaling, which happens to be not really + * supported on the Xperia Nile/Ganges platform. + */ + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p0: l3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + regulator-always-on; + }; + + vreg_l4b_29p5: l4 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_29p5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l6b_3p3: l6 { + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l9b_0p87: l9 { + /* Unused */ + status = "disabled"; + }; + + vreg_l10b_0p915: l10 { + /* Unused */ + status = "disabled"; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + + vreg_bob_pin1: bob_pin1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + qcom,bob-pin-id = <1>; + }; + + vreg_bob_pin2: bob_pin2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + qcom,bob-pin-id = <2>; + }; + + vreg_bob_pin3: bob_pin3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + qcom,bob-pin-id = <3>; + }; + }; + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s1a_ftapc0: s1 { + /* Unused */ + status = "disabled"; + }; + + vreg_s2a_ftapc1: s2 { + /* Unused */ + status = "disabled"; + }; + + vreg_s3a_hfapc1: s3 { + /* Unused */ + status = "disabled"; + }; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + /* regulator-always-on; */ + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1368000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1784000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* This gives power to the LPDDR4: never turn it off! */ + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1904000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l16a_2p7: l16 { + /* Unused */ + status = "disabled"; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l18a_1v8: l18 { + status = "disabled"; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + +&adreno_gpu{ + status = "disabled"; +}; + +&blsp_i2c3 { + status = "okay"; + touchscreen@38 { + compatible = "edt,edt-ft5406", "edt,edt-ft5x06"; + reg = <0x38>; + vcc-supply = <&vreg_l11a_1p8>; + pinctrl-0 = <&ts_int_active &ts_rst>; + pinctrl-names = "default"; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1200>; + touchscreen-size-y = <1920>; + }; +}; + +&gpucc{ + status = "disabled"; +}; + +&mmcc{ + status = "disabled"; +}; + +&pm660l_gpios { + vol_up_pin_active: vol_up_pin { + pins = "gpio7"; + function = "normal"; + input-enable; + bias-pull-up; + }; +}; + +&pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qusb2phy0 { + status = "okay"; +}; + +&sdhc_1 { + status = "okay"; + bus-width = <8>; + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&sdhc_2 { + status = "okay"; + + vmmc-supply = <&vreg_l5b_29p5>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; + + ts_int_active: ts-int-active { + pins = "gpio67"; + drive-strength = <8>; + bias-pull-up; + }; + ts_rst: ts-rst { + pins = "gpio66"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + dr_mode = "peripheral"; +}; From cead3ba0a4f86861a82f86c177c844f356f9aa7e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 5 Aug 2021 15:34:21 +0200 Subject: [PATCH 017/143] arm64: dts: qcom: Introduce SDM660 Xiaomi Mi 8 Lite (platina) Add support for the SDM660 Xiaomi Platina (Mi 8 Lite). Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm660-xiaomi-platina.dts | 717 ++++++++++++++++++ 2 files changed, 718 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7bb49465140fa6..1d7da0b99e9651 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -154,6 +154,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm636-asus-x00td.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-clover.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-platina.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm670-google-sargo.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r2.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts new file mode 100644 index 00000000000000..0c7dc90f4661cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "sdm660.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" +#include +#include +#include +#include +#include + +/ { + model = "Xiaomi Mi 8 Lite"; + compatible = "xiaomi,platina", "qcom,sdm660"; + + aliases { + serial0 = &blsp1_uart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + status = "okay"; + }; + + debug_region@ffb00000 { + reg = <0x00 0xffb00000 0x00 0x100000>; + no-map; + }; + + cdsp-region@94e00000 { + reg = <0x00 0x94e00000 0x00 0x600000>; + no-map; + }; + + removed_region@85800000 { + reg = <0x00 0x85800000 0x00 0x3700000>; + no-map; + }; + }; + + board_vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-always-on; + regulator-boot-on; + }; + + cam_avdd_front_vreg: cam-avdd-front-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam-avdd-front-vreg"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 49 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_avdd_front_default>; + vin-supply = <&vreg_bob>; + }; + + cam_actuator_rear_vreg: cam-actuator-rear-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam-actuator-rear-vreg"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 50 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_actuator_rear_default>; + vin-supply = <&vreg_bob>; + }; + + cam_avdd_rear_vreg: cam-avdd-rear-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam-avdd-rear-vreg"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_avdd_rear_default>; + vin-supply = <&vreg_bob>; + }; + + cam_dvdd_front_vreg: cam-dvdd-front-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam-dvdd-front-vreg"; + + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pm660l_gpios 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_dvdd_front_default>; + vin-supply = <&vreg_s5a_1p35>; + }; + + cam_dvdd_rear_vreg: cam-dvdd-rear-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam-dvdd-rear-vreg"; + + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pm660l_gpios 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_dvdd_rear_default>; + vin-supply = <&vreg_s5a_1p35>; + }; + + disp_vdd_vreg: disp-vdd-vreg { + compatible = "regulator-fixed"; + regulator-name = "display-vdd"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ts_vdd_vreg: ts-vdd-vreg { + compatible = "regulator-fixed"; + regulator-name = "ts-vdd"; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 73 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_vdd_default>; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + + regulator-always-on; + regulator-boot-on; + }; + + gpio_keys { + status = "okay"; + compatible = "gpio-keys"; + input-name = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + vol_up { + label = "Volume Up"; + gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + label = "Hall effect sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&hall_sensor_default>; + + hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; + }; + }; + + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + }; +}; + +&blsp_i2c2 { + status = "okay"; + + /* + * Two instances of SMB1355 charger: 0x8, 0xc but only + * one SMB1355 chip is present on board. What's the + * right address? + */ +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&rpm_requests { + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + /* + * At least on Nile's configuration, S3B/S4B (VDD_CX) and + * S5B (VDD_MX) are managed only through RPM Power Domains. + * Trying to set a voltage on the main supply will create + * havoc and freeze the SoC. + * In any case, reference voltages for these regulators are: + * S3B/S4B: 0.870V + * S5B: 0.915V + */ + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <920000>; + regulator-max-microvolt = <928000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2b_2p95: l2 { + /* + * This regulator supports 1.648 - 3.104V on this board + * but we set a max voltage of anything less than 2.7V + * to satisfy a condition in sdhci.c that will disable + * 3.3V SDHCI signaling, which happens to be not really + * supported on the Xperia Nile/Ganges platform. + */ + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2696000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3312000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <2944000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + /* + * Downstream specifies a range of 1721-3600mV, + * but the only assigned consumers are SDHCI2 VMMC + * and Coresight QPDI that both request pinned 2.95V. + * Tighten the range to 1.8-3.328 (closest to 3.3) to + * make the mmc driver happy. + */ + vreg_l5b_29p5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3128000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* L9B (870mV) is currently unused */ + /* L10B (915mV) is currently unused */ + + vreg_bob: bob { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3624000>; + regulator-enable-ramp-delay = <500>; + regulator-ramp-delay = <0>; + }; + }; + + + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + /* + * S1A (FTAPC0), S2A (FTAPC1), S3A (HFAPC1) are managed + * by the Core Power Reduction hardened (CPRh) and the + * Operating State Manager (OSM) HW automatically. + */ + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <2040000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + regulator-ramp-delay = <0>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + regulator-ramp-delay = <0>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1226000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1008000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <944000>; + regulator-max-microvolt = <1008000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1368000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1804000>; + regulator-max-microvolt = <1896000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1784000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1944000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* DRX: QM13111 */ + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2712000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1648000>; + regulator-max-microvolt = <2952000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + }; + + /* L18A (2.7V) is unused */ + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3328000>; + regulator-enable-ramp-delay = <250>; + regulator-ramp-delay = <0>; + regulator-allow-set-load; + }; + }; +}; + +&sdhc_1 { + status = "okay"; + supports-cqe; + + mmc-ddr-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + vmmc-supply = <&vreg_l4b_2p95>; + vqmmc-supply = <&vreg_l8a_1p8>; +}; + +&sdhc_2 { + status = "disabled"; + + vmmc-supply = <&vreg_l5b_29p5>; + vqmmc-supply = <&vreg_l2b_2p95>; +}; + +&pm660_gpios { + nfc_clk_req_n: nfc-clkreq-n { + pins = "gpio4"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-disable; + input-enable; + power-source = <1>; + }; +}; + +&pm660l_gpios { + cam_dvdd_front_default: cam-dvdd-front-default { + pins = "gpio3"; + function = "normal"; + output-low; + power-source = <0>; + }; + + cam_dvdd_rear_default: cam-dvdd-rear-default { + pins = "gpio4"; + function = "normal"; + output-low; + power-source = <0>; + }; + + vol_key_gpio_default: vol-key-gpio-default { + pins = "gpio7"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; + + camera_rear_default: camera-rear-default { + mclk0 { + pins = "gpio32"; + function = "cam_mclk"; + drive-strength = <4>; + bias-disable; + }; + + rst { + pins = "gpio46"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_front_default: camera-front-default { + mclk1 { + pins = "gpio33"; + function = "cam_mclk"; + drive-strength = <4>; + bias-disable; + }; + + rst { + pins = "gpio47"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + camera_front_iris_default: camera-front-iris-default { + mclk1 { + pins = "gpio35"; + function = "cam_mclk"; + drive-strength = <4>; + bias-disable; + }; + + rst { + pins = "gpio52"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + }; + + cam_avdd_front_default: cam-avdd-front-default { + pins = "gpio49"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cam_actuator_rear_default: cam-actuator-rear-default { + pins = "gpio50"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cam_avdd_rear_default: cam-avdd-rear-default { + pins = "gpio51"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + panel_reset_n: panel-rst-n { + pins = "gpio53"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdp_vsync_n: mdp-vsync-n { + pins = "gpio59"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_rst_n: ts-rst-n { + pins = "gpio66"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + ts_int_active: ts-int-active { + pins = "gpio67"; + drive-strength = <16>; + bias-pull-up; + }; + + ts_vdd_default: ts-vdd-default { + pins = "gpio73"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + hall_sensor_default: hall-sensor-default { + pins = "gpio75"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; From d2d3a161e102dfa4bf23341080de369c394b4593 Mon Sep 17 00:00:00 2001 From: Molly Sophia Date: Mon, 17 Jan 2022 10:02:59 +0300 Subject: [PATCH 018/143] arm64: dts: qcom: sdm660-platina: Add several more features * Add simple framebuffer display node and reserve memory for it. * Enable qusb2phy0 and its vdd supplies * Disable gpucc and mmcc, simplefb stops working after few seconds when these are enabled. * Add node for touchscreen * Fix volume keys Signed-off-by: Molly Sophia --- .../boot/dts/qcom/sdm660-xiaomi-platina.dts | 79 +++++++++++++++++-- 1 file changed, 72 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts index 0c7dc90f4661cf..5e9c316ac2505d 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-platina.dts @@ -2,6 +2,7 @@ /* * Copyright (c) 2021, AngeloGioacchino Del Regno * + * Copyright (c) 2022, Molly Sophia */ /dts-v1/; @@ -25,6 +26,19 @@ chosen { stdout-path = "serial0:115200n8"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1080 * 2280 * 4)>; + width = <1080>; + height = <2280>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; }; reserved-memory { @@ -57,6 +71,11 @@ reg = <0x00 0x85800000 0x00 0x3700000>; no-map; }; + + framebuffer_memory@9d400000 { + reg = <0x0 0x9d400000 0x0 (1080 * 2280 * 4)>; + no-map; + }; }; board_vbat: vbat-regulator { @@ -173,17 +192,17 @@ gpio_keys { status = "okay"; - compatible = "gpio-keys"; - input-name = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; + compatible = "gpio-keys-polled"; + poll-interval = <100>; + label = "Volume up"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_gpio_default>; vol_up { label = "Volume Up"; gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>; - linux,input-type = <1>; + linux,input-type = ; linux,code = ; - wakeup-source; debounce-interval = <15>; }; }; @@ -226,6 +245,23 @@ */ }; +&blsp_i2c4 { + status = "okay"; + /* Novatek device tree node */ + novatek@62 { + compatible = "novatek,nt36525"; + reg = <0x62>; + vcc-supply = <&vreg_l11a_1p8>; + pinctrl-0 = <&ts_int_active &ts_rst_n>; + pinctrl-names = "default"; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1080>; + touchscreen-size-y = <2280>; + }; +}; + &blsp1_uart2 { status = "okay"; }; @@ -582,7 +618,7 @@ power-source = <0>; }; - vol_key_gpio_default: vol-key-gpio-default { + vol_up_gpio_default: vol-up-gpio-default { pins = "gpio7"; function = "normal"; bias-pull-up; @@ -591,6 +627,15 @@ }; }; +&pon_resin { + linux,code = ; + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <8 4>; @@ -707,6 +752,26 @@ }; +&adreno_gpu{ + status = "disabled"; +}; + +&gpucc{ + status = "disabled"; +}; + +&mmcc{ + status = "disabled"; +}; + +&qusb2phy0 { + status = "okay"; + + vdd-supply = <&vreg_l1b_0p925>; + vdda-pll-supply = <&vreg_l10a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l7b_3p125>; +}; + &usb3 { status = "okay"; }; From 34005ad217f6b3bf9926e9a275dd2495019ad91b Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 25 Apr 2022 10:21:41 +0700 Subject: [PATCH 019/143] arm64: dts: qcom: sdm660-xiaomi-lavender: Add Touchscreen The Xiaomi Redmi Note 7 uses a Novatek NT36672A touchscreen, so add support for it. Signed-off-by: Dang Huynh --- arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts index 8fb2d178874246..292260d39ef4a5 100644 --- a/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts +++ b/arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dts @@ -89,6 +89,18 @@ }; }; +&blsp_i2c1 { + status = "okay"; + + touchscreen: novatek@62 { + compatible = "novatek,nt36525"; + reg = <0x62>; + interrupt-parent = <&tlmm>; + interrupts = <67 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; + }; +}; + &blsp1_uart2 { status = "okay"; }; From 3c16dea5faa96819e5e0998930216f806cf3438c Mon Sep 17 00:00:00 2001 From: M0Rf30 Date: Sat, 26 Nov 2022 12:09:18 +0100 Subject: [PATCH 020/143] arm64: dts: qcom: add device-tree for Redmi Note 6 Pro (xiaomi-tulip) Signed-off-by: Gianluca Boiano --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sdm636-xiaomi-tulip.dts | 535 ++++++++++++++++++ 2 files changed, 536 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1d7da0b99e9651..7f4be8347fb979 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -152,6 +152,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm632-motorola-ocean.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-asus-x00td.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm636-xiaomi-tulip.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-clover.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-platina.dtb diff --git a/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts b/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts new file mode 100644 index 00000000000000..9d4d053205c7f0 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm636-xiaomi-tulip.dts @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: 2022 Gianluca Boiano + +/dts-v1/; + +#include "sdm636.dtsi" +#include "pm660.dtsi" +#include "pm660l.dtsi" +#include +#include +#include + +/delete-node/ &qhee_code; +/delete-node/ &smem_region; +/delete-node/ &tz_mem; +/delete-node/ &mpss_region; +/delete-node/ &mba_region; +/delete-node/ &adsp_region; +/delete-node/ &buffer_mem; +/delete-node/ &zap_shader_region; + +/ { + model = "Xiaomi Redmi Note 6 Pro"; + compatible = "xiaomi,tulip", "qcom,sdm660", "qcom,sdm636"; + chassis-type = "handset"; + + qcom,msm-id = <0x159 0>; + qcom,board-id = <0x40008 0x00>; + qcom,pmic-id = <0x1001b 0x101011a 0x0 0x0 0x1001b 0x201011a 0x0 0x0>; + + battery: battery { + compatible = "simple-battery"; + + charge-full-design-microamp-hours = <4000000>; + voltage-min-design-microvolt = <3400000>; + voltage-max-design-microvolt = <4408000>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@9d400000 { + compatible = "simple-framebuffer"; + reg = <0x0 0x9d400000 0x0 (1080 * 2280 * 4)>; + status = "okay"; + width = <1080>; + height = <2280>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + }; + }; + + gpio-keys { + status = "okay"; + compatible = "gpio-keys"; + + camera_focus { + label = "Camera Focus"; + gpios = <&tlmm 64 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + debounce-interval = <15>; + }; + + camera_snapshot { + label = "Camera Snapshot"; + gpios = <&tlmm 113 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = <0x2fe>; // not mapped + debounce-interval = <15>; + }; + + vol_up { + label = "Volume Up"; + gpios = <&tlmm 7 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* removed_regions in downstream / qhee_code */ + removed_region: removed_region@85800000 { + reg = <0x0 0x85800000 0x0 0x600000>; + no-map; + }; + + smem_region: smem_memory@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + }; + + tz_mem: tz_memory@86200000 { + reg = <0x0 0x86200000 0x0 0x2D00000>; + no-map; + }; + + modem_fw_mem: modem_fw_region@8ac00000 { + reg = <0x0 0x8ac00000 0x0 0x7e00000>; + no-map; + }; + + adsp_region: adsp@92a00000 { + reg = <0x0 0x92a00000 0x0 0x1e00000>; + no-map; + }; + + buffer_mem: buffer_region@94a00000 { + reg = <0x0 0x94a00000 0x0 0x100000>; + no-map; + }; + + framebuffer_memory@9d400000 { + reg = <0x0 0x9d400000 0x0 (1080 * 2280 * 4)>; + no-map; + }; + + pil_mba_mem: mba@94800000 { + reg = <0x0 0x94800000 0x0 0x200000>; + no-map; + }; + + ramoops@a0000000 { + compatible = "ramoops"; + reg = <0x0 0xa0000000 0x0 0x400000>; + console-size = <0x20000>; + record-size = <0x20000>; + ftrace-size = <0x0>; + pmsg-size = <0x20000>; + }; + }; + + /* Add support of Wi-Fi */ + soc { + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0x18800000 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_msa_mem>; + clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; + clock-names = "cxo_ref_clk_pin"; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + ; + + iommus = <&anoc2_smmu 0x1a00>, + <&anoc2_smmu 0x1a01>; + qcom,msa-fixed-perm; + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l5a_0p848>; + vdd-1.8-xo-supply = <&vreg_l9a_1p8>; + vdd-1.3-rfa-supply = <&vreg_l6a_1p3>; + vdd-3.3-ch0-supply = <&vreg_l19a_3p3>; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&adsp_pil { + status = "okay"; + firmware-name = "adsp.mdt"; +}; + +&anoc2_smmu { + status = "okay"; +}; + +&blsp_i2c1 { + status = "okay"; +}; + +&blsp_i2c2 { + status = "okay"; +}; + +&blsp_i2c6 { + status = "okay"; +}; + +&blsp2_uart1 { + status = "okay"; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&vreg_l6b_3p3>; + vdda-supply = <&vreg_l11a_1p8>; +}; + +&dsi0_phy { + vcca-supply = <&vreg_l1b_0p925>; + status = "okay"; +}; + +&gcc { + status = "okay"; +}; + +&lpass_smmu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mmcc { + status = "okay"; +}; + +&mmss_smmu { + status = "okay"; +}; + +&pm660_charger { + status = "okay"; + monitored-battery = <&battery>; +}; + +&pm660_fg { + status = "okay"; + monitored-battery = <&battery>; + qcom,battery-capacity-ua = <4000000>; + qcom,min-voltage-uv= <3400000>; + qcom,max-voltage-uv= <4408000>; +}; + +&pm660_rradc { + status = "okay"; +}; + +&pm660l_wled { + status = "okay"; + default-brightness = <512>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&qusb2phy0 { + status = "okay"; +}; + +&rpm_requests { + pm660-regulators { + compatible = "qcom,rpm-pm660-regulators"; + + vdd_l1_l6_l7-supply = <&vreg_s5a_1p35>; + vdd_l2_l3-supply = <&vreg_s2b_1p05>; + vdd_l5-supply = <&vreg_s2b_1p05>; + vdd_l8_l9_l10_l11_l12_l13_l14-supply = <&vreg_s4a_2p04>; + vdd_l15_l16_l17_l18_l19-supply = <&vreg_bob>; + + vreg_s4a_2p04: s4 { + regulator-min-microvolt = <1805000>; + regulator-max-microvolt = <2040000>; + regulator-enable-ramp-delay = <200>; + regulator-always-on; + }; + + vreg_s5a_1p35: s5 { + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1350000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s6a_0p87: s6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <992000>; + regulator-enable-ramp-delay = <150>; + }; + + /* LDOs */ + vreg_l1a_1p225: l1 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l2a_1p0: l2 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1010000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l5a_0p848: l5 { + regulator-min-microvolt = <525000>; + regulator-max-microvolt = <950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l6a_1p3: l6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1370000>; + regulator-allow-set-load; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7a_1p2: l7 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8a_1p8: l8 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-system-load = <325000>; + regulator-allow-set-load; + }; + + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1750000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l11a_1p8: l11 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l13a_1p8: l13 { + regulator-min-microvolt = <1780000>; + regulator-max-microvolt = <1950000>; + regulator-enable-ramp-delay = <250>; + regulator-boot-on; + regulator-always-on; + }; + + vreg_l14a_1p8: l14 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l17a_1p8: l17 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l19a_3p3: l19 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + }; + + pm660l-regulators { + compatible = "qcom,rpm-pm660l-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + + vdd_l1_l9_l10-supply = <&vreg_s2b_1p05>; + vdd_l2-supply = <&vreg_bob>; + vdd_l3_l5_l7_l8-supply = <&vreg_bob>; + vdd_l4_l6-supply = <&vreg_bob>; + vdd_bob-supply = <&vph_pwr>; + + vreg_s1b_1p125: s1 { + regulator-min-microvolt = <1125000>; + regulator-max-microvolt = <1125000>; + regulator-enable-ramp-delay = <200>; + }; + + vreg_s2b_1p05: s2 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-enable-ramp-delay = <200>; + }; + + /* LDOs */ + vreg_l1b_0p925: l1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <925000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + /* SDHCI 3.3V signal doesn't seem to be supported. */ + vreg_l2b_2p95: l2 { + regulator-min-microvolt = <350000>; + regulator-max-microvolt = <3100000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l3b_3p3: l3 { + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + }; + + vreg_l4b_2p95: l4 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2950000>; + regulator-enable-ramp-delay = <250>; + + regulator-min-microamp = <200>; + regulator-max-microamp = <600000>; + regulator-system-load = <570000>; + regulator-allow-set-load; + }; + + vreg_l5b_2p95: l5 { + regulator-min-microvolt = <1721000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <250>; + regulator-allow-set-load; + regulator-system-load = <800000>; + }; + + vreg_l6b_3p3: l6 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l7b_3p125: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3125000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_l8b_3p3: l8 { + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-enable-ramp-delay = <250>; + }; + + vreg_bob: bob { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3600000>; + regulator-enable-ramp-delay = <500>; + }; + }; +}; + +&sdhc_1 { + status = "okay"; +}; + +&sdhc_2 { + status = "okay"; +}; + +&tlmm { + gpio-reserved-ranges = <8 4>; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + dr_mode = "peripheral"; +}; + +&venus { + status = "okay"; + firmware-name = "qcom/venus-4.4/venus.mdt"; +}; \ No newline at end of file From e5e62f8f18ee9a1edc9c236a90a223f7b0357ac7 Mon Sep 17 00:00:00 2001 From: Joe Mason Date: Sat, 26 Nov 2022 06:47:07 -0500 Subject: [PATCH 021/143] drm/panel: Add support for xiaomi-jasmine nt36672 panel alexeymin: this needs to be integrated into panel-novatek-nt36672a.c as variation with its own compatible string and own init sequences. [1] https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/panel/panel-novatek-nt36672a.c Signed-off-by: Joe Mason --- drivers/gpu/drm/panel/Kconfig | 9 + drivers/gpu/drm/panel/Makefile | 1 + .../panel-novatek-nt36672-tianma-jasmine.c | 273 ++++++++++++++++++ 3 files changed, 283 insertions(+) create mode 100644 drivers/gpu/drm/panel/panel-novatek-nt36672-tianma-jasmine.c diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index 2b9d6db7860baa..34a637b249c212 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -408,6 +408,15 @@ config DRM_PANEL_NOVATEK_NT36672A around the Novatek NT36672A display controller, such as some Tianma panels used in a few Xiaomi Poco F1 mobile phones. +config DRM_PANEL_NOVATEK_NT36672_TIANMA_JASMINE + tristate "Novatek NT36672 Tianma panel for xiaomi-jasmine" + depends on OF + depends on DRM_MIPI_DSI + depends on BACKLIGHT_CLASS_DEVICE + help + Say Y here if you want to enable support for Tianma nt36672 + command mode panel used in Xiaomi Mi A2 phone (codename jasmine) + config DRM_PANEL_NOVATEK_NT39016 tristate "Novatek NT39016 RGB/SPI panel" depends on OF && SPI diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile index ff169781e82d70..06d09a67f2286a 100644 --- a/drivers/gpu/drm/panel/Makefile +++ b/drivers/gpu/drm/panel/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35560) += panel-novatek-nt35560.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT35950) += panel-novatek-nt35950.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36523) += panel-novatek-nt36523.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672A) += panel-novatek-nt36672a.o +obj-$(CONFIG_DRM_PANEL_NOVATEK_NT36672_TIANMA_JASMINE) += panel-novatek-nt36672-tianma-jasmine.o obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36672-tianma-jasmine.c b/drivers/gpu/drm/panel/panel-novatek-nt36672-tianma-jasmine.c new file mode 100644 index 00000000000000..168d67bb64de72 --- /dev/null +++ b/drivers/gpu/drm/panel/panel-novatek-nt36672-tianma-jasmine.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2022 FIXME +// Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree: +// Copyright (c) 2013, The Linux Foundation. All rights reserved. (FIXME) + +#include +#include +#include +#include +#include + +#include