Hi,
this is really not an issue, just want to understand the code in Chapter 6, page 92, task handle_settings.
The code:
mins <= mins + 1;
if (mins == 9)
begin
mins <= 1
end
I understand that in traditional (sequential) programming languages the condition should be 'if (mins == 10)' in order the code to work as intended. I figured out the code works on FPGA probably because the two statements run in parallel, therefore 'mins' probably never reaches 10. I think this should have been pointed out in the book (if my assumption is correct). I'm also wondering how the FPGA hardware decides whether to set 'mins' to 10 or 1 because both of the assignments (mins <= mins + 1 and mins <= 1) possibly run in parallel. I'm also wondering whether assignments (<=) and decisions (==) operations in general run in parallel or whether the desisions (if) statements are somehow processed before assignments in Verilog.
Also on page 55 the code snippet uses Q = A. In other places the code snippet uses '<=' as an assignment. The book doesn't explain in detail the difference nor shows practical consequences of using blocking or nonblocking assignment. Unfortunately for me (Verilog newbie) it was not apparent as the chapter 4 promises on page 57. For example what would happen if the code block above would be written like that:
if (mins == 9)
begin
mins <= 1
end
mins <= mins + 1
or be written like that
mins = mins + 1
if (mins == 9)
begin
mins <= 1
end
or be written like that:
if (mins == 9)
begin
mins <= 1
end
mins = mins + 1
Which of these 3 statements would run in parallel? Which would run first? Would the blocking assignment have precedence? etc. This doesn't seem to be explained in the book, but I feel this is absolutely crucial in order to write correctly behaving logic in Verilog. If not, it should be IMHO also stated in the book.
BTW. I don't know Verilog, these were just my thoughts while reading the book and trying to understand the examples.
Hi,
this is really not an issue, just want to understand the code in Chapter 6, page 92, task handle_settings.
The code:
I understand that in traditional (sequential) programming languages the condition should be 'if (mins == 10)' in order the code to work as intended. I figured out the code works on FPGA probably because the two statements run in parallel, therefore 'mins' probably never reaches 10. I think this should have been pointed out in the book (if my assumption is correct). I'm also wondering how the FPGA hardware decides whether to set 'mins' to 10 or 1 because both of the assignments (mins <= mins + 1 and mins <= 1) possibly run in parallel. I'm also wondering whether assignments (<=) and decisions (==) operations in general run in parallel or whether the desisions (if) statements are somehow processed before assignments in Verilog.
Also on page 55 the code snippet uses Q = A. In other places the code snippet uses '<=' as an assignment. The book doesn't explain in detail the difference nor shows practical consequences of using blocking or nonblocking assignment. Unfortunately for me (Verilog newbie) it was not apparent as the chapter 4 promises on page 57. For example what would happen if the code block above would be written like that:
or be written like that
or be written like that:
Which of these 3 statements would run in parallel? Which would run first? Would the blocking assignment have precedence? etc. This doesn't seem to be explained in the book, but I feel this is absolutely crucial in order to write correctly behaving logic in Verilog. If not, it should be IMHO also stated in the book.
BTW. I don't know Verilog, these were just my thoughts while reading the book and trying to understand the examples.