Chapter 4: A Counter in Verilog

[jomoengineer]

I'm not sure if this is where to post this, however In the Programming FPGAs book in Chapter 4 on page 57 "A Counter in Verilog", the Constraints file for the Papilio is listed with the highlighted changes from the schematic version. However, the "Clock" line is shown with CLOCK_DEDICATED_ROUTER = TRUE where in the schematic version this is listed as FALSE.

Ex:
Schematic Version:

NET "Clock" LOC = "P22" | PULLUP | CLOCK_DEDICATED_ROUTE = FALSE;

Verilog version:

NET "Clock" LOC = "P22" | PULLUP | CLOCK_DEDICATED_ROUTE = TRUE;

The books does not appear to have this highlighted.

Cheers!

[Sreevatsan2001]

I'm not sure if this is where to post this, however In the Programming FPGAs book in Chapter 4 on page 57 "A Counter in Verilog", the Constraints file for the Papilio is listed with the highlighted changes from the schematic version. However, the "Clock" line is shown with CLOCK_DEDICATED_ROUTER = TRUE where in the schematic version this is listed as FALSE.

Ex:
Schematic Version:

NET "Clock" LOC = "P22" | PULLUP | CLOCK_DEDICATED_ROUTE = FALSE;

Verilog version:

NET "Clock" LOC = "P22" | PULLUP | CLOCK_DEDICATED_ROUTE = TRUE;

The books does not appear to have this highlighted.

Cheers!

Mate I think the author in schematic version has set CLOCK_DEDICATED_ROUTE = FALSE and CLOCK_DEDICATED_ROUTE = TRUE in Verilog case because in the latter case he has clearly defined counter on the falling edge and therefore avoids ambiguity. But in the former author has set Clock route to be false because we cannot explicitly state counter in schematic description.
I am not certain about my explanation as I am just a beginner in VERILOG.. but hopefully it makes sense and it helps.