@@ -27,6 +27,8 @@ architecture testbed of BoxcarIntegratorTb is
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constant TPD_G : time := 2.5 ns ;
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+ constant DOB_REG_C : boolean := true ;
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+
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signal clk : sl := '0' ;
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signal rst : sl := '0' ;
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@@ -40,6 +42,7 @@ architecture testbed of BoxcarIntegratorTb is
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signal dataIn : slv(15 downto 0 );
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signal expData0 : slv(25 downto 0 );
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signal expData1 : slv(25 downto 0 );
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+ signal expData2 : slv(25 downto 0 );
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signal expError : sl;
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signal spacing : slv(15 downto 0 );
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@@ -145,6 +148,7 @@ begin
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generic map (
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TPD_G => TPD_G,
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SIGNED_G => false ,
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+ DOB_REG_G => DOB_REG_C,
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DATA_WIDTH_G => 16 ,
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ADDR_WIDTH_G => 10 )
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port map (
@@ -166,6 +170,7 @@ begin
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if rst = '1' then
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expData0 <= (others => '0' ) after TPD_G;
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expData1 <= (others => '0' ) after TPD_G;
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+ expData2 <= (others => '0' ) after TPD_G;
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expError <= '0' after TPD_G;
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else
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if validEn = '1' then
@@ -179,8 +184,14 @@ begin
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expData1 <= expData0 after TPD_G;
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+ if DOB_REG_C then
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+ expData2 <= expData1 after TPD_G;
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+ else
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+ expData2 <= expData0 after TPD_G;
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+ end if ;
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+
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if obValid = '1' then
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- if obFull = '0' or expData1 = obData then
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+ if obFull = '0' or expData2 = obData then
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expError <= '0' after TPD_G;
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else
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expError <= '1' after TPD_G;
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