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Merge pull request #965 from slaclab/pre-release
Release Candidate v2.30.1
2 parents 22e978e + 6c8f35d commit 0ec145a

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2 files changed

+16
-4
lines changed

2 files changed

+16
-4
lines changed

dsp/fixed/BoxcarIntegrator.vhd

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -126,8 +126,9 @@ begin
126126

127127
-- Clear the output valid and period latches
128128
if obAck = '1' then
129-
v.obValid := '0';
130-
v.obPeriod := '0';
129+
v.obValid := '0';
130+
v.obPeriod := '0';
131+
v.obPeriodD := '0';
131132
end if;
132133

133134
-- Input stage, setup addresses
@@ -170,7 +171,7 @@ begin
170171
v.obData := r.obData + r.ibDataE;
171172

172173
-- Check if full
173-
if r.obFullD = '1' then
174+
if r.obFull = '1' then
174175
v.obData := v.obData - ramDoutE;
175176
end if;
176177

dsp/tb/BoxcarIntegratorTb.vhd

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@ architecture testbed of BoxcarIntegratorTb is
2727

2828
constant TPD_G : time := 2.5 ns;
2929

30+
constant DOB_REG_C : boolean := true;
31+
3032
signal clk : sl := '0';
3133
signal rst : sl := '0';
3234

@@ -40,6 +42,7 @@ architecture testbed of BoxcarIntegratorTb is
4042
signal dataIn : slv(15 downto 0);
4143
signal expData0 : slv(25 downto 0);
4244
signal expData1 : slv(25 downto 0);
45+
signal expData2 : slv(25 downto 0);
4346
signal expError : sl;
4447
signal spacing : slv(15 downto 0);
4548

@@ -145,6 +148,7 @@ begin
145148
generic map (
146149
TPD_G => TPD_G,
147150
SIGNED_G => false,
151+
DOB_REG_G => DOB_REG_C,
148152
DATA_WIDTH_G => 16,
149153
ADDR_WIDTH_G => 10)
150154
port map (
@@ -166,6 +170,7 @@ begin
166170
if rst = '1' then
167171
expData0 <= (others => '0') after TPD_G;
168172
expData1 <= (others => '0') after TPD_G;
173+
expData2 <= (others => '0') after TPD_G;
169174
expError <= '0' after TPD_G;
170175
else
171176
if validEn = '1' then
@@ -179,8 +184,14 @@ begin
179184

180185
expData1 <= expData0 after TPD_G;
181186

187+
if DOB_REG_C then
188+
expData2 <= expData1 after TPD_G;
189+
else
190+
expData2 <= expData0 after TPD_G;
191+
end if;
192+
182193
if obValid = '1' then
183-
if obFull = '0' or expData1 = obData then
194+
if obFull = '0' or expData2 = obData then
184195
expError <= '0' after TPD_G;
185196
else
186197
expError <= '1' after TPD_G;

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