Merge pull request #999 from slaclab/pre-release

Release Candidate v2.34.1

Author: ruck314

base/ram/ruckus.tcl

@@ -5,7 +5,7 @@ source $::env(RUCKUS_QUIET_FLAG) $::env(RUCKUS_PROC_TCL)
 loadSource -lib surf -dir "$::DIR_PATH/inferred"
 
 # Check for min. Vivado version with XPM support
-if {  $::env(VIVADO_VERSION) > 2019.1} {
+if {  $::env(VIVADO_VERSION) >= 2019.1} {
    loadSource -lib surf  -dir "$::DIR_PATH/xilinx"
    loadSource -lib surf -path "$::DIR_PATH/dummy/SimpleDualPortRamAlteraMfDummy.vhd"
    loadSource -lib surf -path "$::DIR_PATH/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd"

devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd

@@ -33,6 +33,7 @@ use surf.Ad9249Pkg.all;
 entity Ad9249Deserializer is
    generic (
       TPD_G             : time                 := 1 ns;
+      SIM_DEVICE_G      : string               := "ULTRASCALE";
       IODELAY_GROUP_G   : string               := "DEFAULT_GROUP";
       IDELAY_CASCADE_G  : boolean              := false;
       IDELAYCTRL_FREQ_G : real                 := 300.0;
@@ -118,7 +119,7 @@ begin
          IS_CLK_INVERTED  => '0',       -- Optional inversion for CLK
          IS_RST_INVERTED  => '0',       -- Optional inversion for RST
          REFCLK_FREQUENCY => IDELAYCTRL_FREQ_G,  -- IDELAYCTRL clock input frequency in MHz (200.0-2667.0)
-         SIM_DEVICE       => "ULTRASCALE",  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
+         SIM_DEVICE       => SIM_DEVICE_G,  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
          -- ULTRASCALE_PLUS_ES2)
          UPDATE_MODE      => "ASYNC"  -- Determines when updates to the delay will take effect (ASYNC, MANUAL,
        -- SYNC)
@@ -190,7 +191,7 @@ begin
          IS_CLK_B_INVERTED => '1',      -- Optional inversion for CLK_B
          IS_CLK_INVERTED   => '0',      -- Optional inversion for CLK
          IS_RST_INVERTED   => '0',      -- Optional inversion for RST
-         SIM_DEVICE        => "ULTRASCALE"  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
+         SIM_DEVICE        => SIM_DEVICE_G  -- Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1,
       )
       port map (
          FIFO_EMPTY      => open,       -- 1-bit output: FIFO empty flag

devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup.vhd

@@ -35,6 +35,7 @@ entity Ad9249ReadoutGroup is
       TPD_G             : time                 := 1 ns;
       NUM_CHANNELS_G    : natural range 1 to 8 := 8;
       IODELAY_GROUP_G   : string               := "DEFAULT_GROUP";
+      SIM_DEVICE_G      : string               := "ULTRASCALE";
       D_DELAY_CASCADE_G : boolean              := false;
       F_DELAY_CASCADE_G : boolean              := false;
       IDELAYCTRL_FREQ_G : real                 := 200.0;
@@ -174,11 +175,6 @@ architecture rtl of Ad9249ReadoutGroup is
 
    signal invertSync    : sl;
 
-   attribute KEEP_HIERARCHY                     : string;
-   attribute KEEP_HIERARCHY of AdcClk_I_Ibufds  : label is "TRUE";
-   attribute dont_touch                         : string;
-   attribute dont_touch of adcDclk              : signal is "TRUE";
-
 begin
    -------------------------------------------------------------------------------------------------
    -- Synchronize adcR.locked across to axil clock domain and count falling edges on it
@@ -315,23 +311,21 @@ begin
       end if;
    end process axilSeq;
 
-
-   AdcClk_I_Ibufds : IBUFDS
-   generic map (
-      DQS_BIAS => "FALSE"
-   )
-   port map (
-      I  => adcSerial.dClkP,
-      IB => adcSerial.dClkN,
-      O  => adcDclk
-   );
-
    -------------------------------------------------------------------------------------------------
    -- Create Clocks
    -------------------------------------------------------------------------------------------------
 
    G_MMCM : if USE_MMCME_G = true generate
 
+      AdcClk_I_Ibufds : IBUFDS
+      generic map (
+         DQS_BIAS => "FALSE"
+      )
+      port map (
+         I  => adcSerial.dClkP,
+         IB => adcSerial.dClkN,
+         O  => adcDclk
+      );
 
       ------------------------------------------
       -- Generate clocks from ADC incoming clock
@@ -384,6 +378,7 @@ begin
    U_FRAME_DESERIALIZER : entity surf.Ad9249Deserializer
       generic map (
          TPD_G             => TPD_G,
+         SIM_DEVICE_G      => SIM_DEVICE_G,
          IODELAY_GROUP_G   => "DEFAULT_GROUP",
          IDELAY_CASCADE_G  => F_DELAY_CASCADE_G,
          IDELAYCTRL_FREQ_G => 350.0,
@@ -433,6 +428,7 @@ begin
       U_DATA_DESERIALIZER : entity surf.Ad9249Deserializer
          generic map (
             TPD_G             => TPD_G,
+            SIM_DEVICE_G      => SIM_DEVICE_G,
             IODELAY_GROUP_G   => "DEFAULT_GROUP",
             IDELAY_CASCADE_G  => D_DELAY_CASCADE_G,
             IDELAYCTRL_FREQ_G => 350.0,

devices/Marvell/Sgmii88E1111/lvdsUltraScale/Sgmii88E1111LvdsUltraScale.vhd

@@ -16,7 +16,6 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
-
 library surf;
 use surf.StdRtlPkg.all;
 use surf.AxiStreamPkg.all;
@@ -27,42 +26,49 @@ entity Sgmii88E1111LvdsUltraScale is
    generic (
       TPD_G             : time                  := 1 ns;
       STABLE_CLK_FREQ_G : real                  := 156.25E+6;
-      USE_BUFG_DIV_G    : boolean               := false;
-      CLKOUT1_PHASE_G   : real                  := 90.0;
+      PAUSE_EN_G        : boolean               := true;
+      EN_AXIL_REG_G     : boolean               := false;
       PHY_G             : natural range 0 to 31 := 7;
       AXIS_CONFIG_G     : AxiStreamConfigType   := EMAC_AXIS_CONFIG_C);
    port (
       -- clock and reset
-      extRst      : in    sl;                -- active high
-      stableClk   : in    sl;                -- Stable clock reference
-      phyClk      : out   sl;
-      phyRst      : out   sl;
+      extRst          : in    sl;                -- active high
+      stableClk       : in    sl;                -- Stable clock reference
+      phyClk          : out   sl;
+      phyRst          : out   sl;
       -- Local Configurations/status
-      localMac    : in    slv(47 downto 0);  --  big-Endian configuration
-      phyReady    : out   sl;
-      linkUp      : out   sl;
-      speed10     : out   sl;
-      speed100    : out   sl;
-      speed1000   : out   sl;
+      localMac        : in    slv(47 downto 0);  --  big-Endian configuration
+      phyReady        : out   sl;
+      linkUp          : out   sl;
+      speed10         : out   sl;
+      speed100        : out   sl;
+      speed1000       : out   sl;
       -- Interface to Ethernet Media Access Controller (MAC)
-      macClk      : in    sl;
-      macRst      : in    sl;
-      obMacMaster : out   AxiStreamMasterType;
-      obMacSlave  : in    AxiStreamSlaveType;
-      ibMacMaster : in    AxiStreamMasterType;
-      ibMacSlave  : out   AxiStreamSlaveType;
+      macClk          : in    sl;
+      macRst          : in    sl;
+      obMacMaster     : out   AxiStreamMasterType;
+      obMacSlave      : in    AxiStreamSlaveType;
+      ibMacMaster     : in    AxiStreamMasterType;
+      ibMacSlave      : out   AxiStreamSlaveType;
+      -- Slave AXI-Lite Interface
+      axilClk         : in    sl                     := '0';
+      axilRst         : in    sl                     := '0';
+      axilReadMaster  : in    AxiLiteReadMasterType  := AXI_LITE_READ_MASTER_INIT_C;
+      axilReadSlave   : out   AxiLiteReadSlaveType;
+      axilWriteMaster : in    AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C;
+      axilWriteSlave  : out   AxiLiteWriteSlaveType;
       -- ETH external PHY Ports
-      phyClkP     : in    sl;                -- 625.0 MHz
-      phyClkN     : in    sl;
-      phyMdc      : out   sl;
-      phyMdio     : inout sl;
-      phyRstN     : out   sl;                -- active low
-      phyIrqN     : in    sl;                -- active low
+      phyClkP         : in    sl;                -- 625.0 MHz
+      phyClkN         : in    sl;
+      phyMdc          : out   sl;
+      phyMdio         : inout sl;
+      phyRstN         : out   sl;                -- active low
+      phyIrqN         : in    sl;                -- active low
       -- LVDS SGMII Ports
-      sgmiiRxP    : in    sl;
-      sgmiiRxN    : in    sl;
-      sgmiiTxP    : out   sl;
-      sgmiiTxN    : out   sl);
+      sgmiiRxP        : in    sl;
+      sgmiiRxN        : in    sl;
+      sgmiiTxP        : out   sl;
+      sgmiiTxN        : out   sl);
 end entity Sgmii88E1111LvdsUltraScale;
 
 architecture mapping of Sgmii88E1111LvdsUltraScale is
@@ -181,36 +187,43 @@ begin
          dataIn  => phyIrqN,
          dataOut => phyIrq);
 
-   U_1GigE : entity surf.GigEthLvdsUltraScaleWrapper
+   U_1GigE : entity surf.GigEthLvdsUltraScale
       generic map (
-         TPD_G           => TPD_G,
-         USE_BUFG_DIV_G  => USE_BUFG_DIV_G,
-         CLKOUT1_PHASE_G => CLKOUT1_PHASE_G,
-         AXIS_CONFIG_G   => (others => AXIS_CONFIG_G))
+         TPD_G         => TPD_G,
+         PAUSE_EN_G    => PAUSE_EN_G,
+         EN_AXIL_REG_G => EN_AXIL_REG_G,
+         AXIS_CONFIG_G => AXIS_CONFIG_G)
       port map (
          -- Local Configurations
-         localMac(0)        => localMac,
+         localMac        => localMac,
          -- Streaming DMA Interface
-         dmaClk(0)          => macClk,
-         dmaRst(0)          => macRst,
-         dmaIbMasters(0)    => obMacMaster,
-         dmaIbSlaves(0)     => obMacSlave,
-         dmaObMasters(0)    => ibMacMaster,
-         dmaObSlaves(0)     => ibMacSlave,
-         -- Misc. Signals
-         extRst             => extRst,
-         phyClk             => phyClock,
-         phyRst             => phyReset,
-         phyReady(0)        => phyReady,
-         speed_is_10_100(0) => sp10_100,
-         speed_is_100(0)    => sp100,
-         -- MGT Clock Port
-         sgmiiClkP          => phyClkP,
-         sgmiiClkN          => phyClkN,
-         -- MGT Ports
-         sgmiiTxP(0)        => sgmiiTxP,
-         sgmiiTxN(0)        => sgmiiTxN,
-         sgmiiRxP(0)        => sgmiiRxP,
-         sgmiiRxN(0)        => sgmiiRxN);
+         dmaClk          => macClk,
+         dmaRst          => macRst,
+         dmaIbMaster     => obMacMaster,
+         dmaIbSlave      => obMacSlave,
+         dmaObMaster     => ibMacMaster,
+         dmaObSlave      => ibMacSlave,
+         -- Slave AXI-Lite Interface
+         axilClk         => axilClk,
+         axilRst         => axilRst,
+         axilReadMaster  => axilReadMaster,
+         axilReadSlave   => axilReadSlave,
+         axilWriteMaster => axilWriteMaster,
+         axilWriteSlave  => axilWriteSlave,
+         -- Speed selection
+         speed_is_10_100 => sp10_100,
+         speed_is_100    => sp100,
+         -- PHY + MAC signals
+         extRst          => extRst,
+         ethClk          => phyClock,
+         ethRst          => phyReset,
+         phyReady        => phyReady,
+         -- SGMII / LVDS Ports
+         sgmiiClkP       => phyClkP,    -- 625 MHz
+         sgmiiClkN       => phyClkN,    -- 625 MHz
+         sgmiiTxP        => sgmiiTxP,
+         sgmiiTxN        => sgmiiTxN,
+         sgmiiRxP        => sgmiiRxP,
+         sgmiiRxN        => sgmiiRxN);
 
 end mapping;

devices/Maxim/rtl/Max5443.vhd

@@ -0,0 +1,129 @@
+-------------------------------------------------------------------------------
+-- Company    : SLAC National Accelerator Laboratory
+-------------------------------------------------------------------------------
+-- Description: Max5443 DAC Module
+-------------------------------------------------------------------------------
+-- This file is part of 'SLAC Firmware Standard Library'.
+-- It is subject to the license terms in the LICENSE.txt file found in the
+-- top-level directory of this distribution and at:
+--    https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
+-- No part of 'SLAC Firmware Standard Library', including this file,
+-- may be copied, modified, propagated, or distributed except according to
+-- the terms contained in the LICENSE.txt file.
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+
+library surf;
+use surf.StdRtlPkg.all;
+use surf.AxiLitePkg.all;
+
+entity Max5443 is
+   generic (
+      TPD_G        : time     := 1 ns;
+      CLK_PERIOD_G : real     := 10.0e-9;
+      NUM_CHIPS_G  : positive := 1);
+   port (
+      -- AXI-Lite Register Interface
+      axilClk         : in  sl;
+      axilRst         : in  sl;
+      axilReadMaster  : in  AxiLiteReadMasterType;
+      axilReadSlave   : out AxiLiteReadSlaveType;
+      axilWriteMaster : in  AxiLiteWriteMasterType;
+      axilWriteSlave  : out AxiLiteWriteSlaveType;
+      -- Guard ring DAC interfaces
+      dacSclk         : out sl;
+      dacDin          : out sl;
+      dacCsb          : out slv(NUM_CHIPS_G-1 downto 0);
+      dacClrb         : out sl);
+end Max5443;
+
+architecture rtl of Max5443 is
+
+   type RegType is record
+      vDacSetting    : Slv16Array(NUM_CHIPS_G-1 downto 0);
+      axilReadSlave  : AxiLiteReadSlaveType;
+      axilWriteSlave : AxiLiteWriteSlaveType;
+   end record RegType;
+
+   constant REG_INIT_C : RegType := (
+      vDacSetting    => (others => (others => '0')),
+      axilReadSlave  => AXI_LITE_READ_SLAVE_INIT_C,
+      axilWriteSlave => AXI_LITE_WRITE_SLAVE_INIT_C);
+
+   signal r   : RegType := REG_INIT_C;
+   signal rin : RegType;
+
+   signal dacDinSig  : slv(NUM_CHIPS_G-1 downto 0);
+   signal dacSclkSig : slv(NUM_CHIPS_G-1 downto 0);
+   signal dacClrbSig : slv(NUM_CHIPS_G-1 downto 0);
+
+begin
+
+   dacDin  <= uOr(dacDinSig);
+   dacSclk <= uOr(dacSclkSig);
+   dacClrb <= uOr(dacClrbSig);
+
+   -------------------------------
+   -- Configuration Register
+   -------------------------------
+   comb : process (axilReadMaster, axilRst, axilWriteMaster, r) is
+      variable v      : RegType;
+      variable axilEp : AxiLiteEndPointType;
+
+   begin
+      -- Latch the current value
+      v := r;
+
+      -- Determine the transaction type
+      axiSlaveWaitTxn(axilEp, axilWriteMaster, axilReadMaster, v.axilWriteSlave, v.axilReadSlave);
+
+      -- Map out standard registers
+      for i in 0 to NUM_CHIPS_G-1 loop
+         axiSlaveRegister(axilEp, toSlv(4*i, 8), 0, v.vDacSetting(i));
+      end loop;
+
+      -- Closeout the transaction
+      axiSlaveDefault(axilEp, v.axilWriteSlave, v.axilReadSlave, AXI_RESP_DECERR_C);
+
+      -- Synchronous Reset
+      if axilRst = '1' then
+         v := REG_INIT_C;
+      end if;
+
+      -- Register the variable for next clock cycle
+      rin <= v;
+
+      axilWriteSlave <= r.axilWriteSlave;
+      axilReadSlave  <= r.axilReadSlave;
+
+   end process comb;
+
+   seq : process (axilClk) is
+   begin
+      if rising_edge(axilClk) then
+         r <= rin after TPD_G;
+      end if;
+   end process seq;
+
+   -----------------------------------------------
+   -- DAC Controller
+   -----------------------------------------------
+   G_MAX5443 : for i in 0 to NUM_CHIPS_G-1 generate
+      U_DacCntrl : entity surf.Max5443DacCntrl
+         generic map (
+            TPD_G => TPD_G)
+         port map (
+            sysClk    => axilClk,
+            sysClkRst => axilRst,
+            dacData   => r.vDacSetting(i),
+            dacDin    => dacDinSig(i),
+            dacSclk   => dacSclkSig(i),
+            dacCsL    => dacCsb(i),
+            dacClrL   => dacClrbSig(i));
+   end generate;
+
+end rtl;