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Merge pull request #1245 from slaclab/pre-release
Release Candidate v2.57.0
2 parents b42ea0e + af17c5b commit 6773235

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14 files changed

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‎README.md

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Original file line numberDiff line numberDiff line change
@@ -1,5 +1,7 @@
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# SURF
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[DOE Code](https://www.osti.gov/doecode/biblio/8176)
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SLAC Ultimate RTL Framework
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<!--- ########################################################################################### -->

‎axi/axi-stream/rtl/AxiStreamPkg.vhd

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,7 +24,7 @@ use surf.StdRtlPkg.all;
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package AxiStreamPkg is
2626

27-
constant AXI_STREAM_MAX_TDATA_WIDTH_C : positive := 512; -- Units of bits
27+
constant AXI_STREAM_MAX_TDATA_WIDTH_C : positive := 1024; -- Units of bits
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constant AXI_STREAM_MAX_TKEEP_WIDTH_C : positive := (AXI_STREAM_MAX_TDATA_WIDTH_C/8); -- Units of bytes
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type AxiStreamMasterType is record

‎axi/dma/rtl/AxiDmaPkg.vhd

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -194,6 +194,7 @@ package AxiDmaPkg is
194194
maxSize : slv(31 downto 0);
195195
contEn : sl;
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buffId : slv(31 downto 0);
197+
timeout : slv(31 downto 0);
197198
end record;
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199200
constant AXI_WRITE_DMA_DESC_ACK_INIT_C : AxiWriteDmaDescAckType := (
@@ -204,7 +205,8 @@ package AxiDmaPkg is
204205
dropEn => '0',
205206
maxSize => (others=>'0'),
206207
contEn => '0',
207-
buffId => (others=>'0')
208+
buffId => (others=>'0'),
209+
timeout => x"0000FFFF"
208210
);
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210212
type AxiWriteDmaDescAckArray is array (natural range<>) of AxiWriteDmaDescAckType;
@@ -226,7 +228,7 @@ package AxiDmaPkg is
226228
lastUser : slv(7 downto 0);
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size : slv(31 downto 0);
228230
continue : sl;
229-
result : slv(2 downto 0);
231+
result : slv(3 downto 0);
230232
dest : slv(7 downto 0);
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id : slv(7 downto 0); -- TID
232234
end record;
@@ -269,6 +271,7 @@ package AxiDmaPkg is
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id : slv(7 downto 0); -- TID
270272
buffId : slv(31 downto 0);
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overflow : sl;
274+
timeout : slv(31 downto 0);
272275
end record;
273276

274277
constant AXI_WRITE_DMA_TRACK_INIT_C : AxiWriteDmaTrackType := (
@@ -284,7 +287,8 @@ package AxiDmaPkg is
284287
dropEn => '0',
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id => (others=>'0'),
286289
buffId => (others=>'0'),
287-
overflow => '0'
290+
overflow => '0',
291+
timeout => x"0000FFFF"
288292
);
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290294
type AxiWriteDmaTrackArray is array (natural range<>) of AxiWriteDmaTrackType;

‎axi/dma/rtl/v2/AxiStreamDmaV2Desc.vhd

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,7 @@ architecture rtl of AxiStreamDmaV2Desc is
145145
buffWrCache : slv(3 downto 0);
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enableCnt : slv(7 downto 0);
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idBuffThold : Slv32Array(7 downto 0);
148+
wrTimeout : slv(31 downto 0);
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-- FIFOs
150151
fifoDin : slv(31 downto 0);
@@ -222,6 +223,7 @@ architecture rtl of AxiStreamDmaV2Desc is
222223
buffWrCache => (others => '0'),
223224
enableCnt => (others => '0'),
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idBuffThold => (others => (others => '0')),
226+
wrTimeout => x"0000FFFF",
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-- FIFOs
226228
fifoDin => (others => '0'),
227229
wrFifoWr => (others => '0'),
@@ -433,7 +435,7 @@ begin
433435
axiSlaveRegister(regCon, x"000", 0, v.enable);
434436
axiSlaveRegisterR(regCon, x"000", 8, r.enableCnt); -- Count the number of times enable transitions from 0->1
435437
axiSlaveRegisterR(regCon, x"000", 16, '1'); -- Legacy DESC_128_EN_C constant (always 0x1 now)
436-
axiSlaveRegisterR(regCon, x"000", 24, toSlv(4, 8)); -- Version Number for aes-stream-driver to case on
438+
axiSlaveRegisterR(regCon, x"000", 24, toSlv(5, 8)); -- Version Number for aes-stream-driver to case on
437439
axiSlaveRegister(regCon, x"004", 0, v.intEnable);
438440
axiSlaveRegister(regCon, x"008", 0, v.contEn);
439441
axiSlaveRegister(regCon, x"00C", 0, v.dropEn);
@@ -486,6 +488,8 @@ begin
486488

487489
axiSlaveRegister(regCon, x"084", 0, v.intHoldoff);
488490

491+
axiSlaveRegister(regCon, x"088", 0, v.wrTimeout);
492+
489493
for i in 0 to 7 loop
490494
axiSlaveRegister(regCon, toSlv(144 + i*4, 12), 0, v.idBuffThold(i)); -- 0x090 - 0xAC
491495
axiSlaveRegisterR(regCon, toSlv(176 + i*4, 12), 0, r.idBuffCount(i)); -- 0x0B0 - 0xCC
@@ -583,6 +587,7 @@ begin
583587
v.dmaWrDescAck(i).dropEn := r.dropEn;
584588
v.dmaWrDescAck(i).contEn := r.contEn;
585589
v.dmaWrDescAck(i).maxSize := r.maxSize;
590+
v.dmaWrDescAck(i).timeout := r.wrTimeout;
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587592
v.dmaWrDescAck(i).buffId(27 downto 0) := wrFifoDout(27 downto 0);
588593

@@ -693,9 +698,10 @@ begin
693698
v.axiWriteMaster.wdata(31 downto 24) := dmaWrDescRet(descIndex).firstUser;
694699
v.axiWriteMaster.wdata(23 downto 16) := dmaWrDescRet(descIndex).lastUser;
695700
v.axiWriteMaster.wdata(15 downto 8) := dmaWrDescRet(descIndex).id;
696-
v.axiWriteMaster.wdata(7 downto 4) := (others => '0');
701+
v.axiWriteMaster.wdata(7 downto 5) := (others => '0');
702+
v.axiWriteMaster.wdata(4) := dmaWrDescRet(descIndex).result(3);
697703
v.axiWriteMaster.wdata(3) := dmaWrDescRet(descIndex).continue;
698-
v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result;
704+
v.axiWriteMaster.wdata(2 downto 0) := dmaWrDescRet(descIndex).result(2 downto 0);
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700706
v.axiWriteMaster.wstrb := resize(x"FFFF", 128);
701707

‎axi/dma/rtl/v2/AxiStreamDmaV2Write.vhd

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,8 @@ architecture rtl of AxiStreamDmaV2Write is
8181
result : slv(1 downto 0);
8282
reqCount : slv(31 downto 0);
8383
ackCount : slv(31 downto 0);
84-
stCount : slv(15 downto 0);
84+
stCount : slv(31 downto 0);
85+
timeoutCnt : slv(31 downto 0);
8586
awlen : slv(AXI_CONFIG_G.LEN_BITS_C-1 downto 0);
8687
axiLen : AxiLenType;
8788
wMaster : AxiWriteMasterType;
@@ -100,6 +101,7 @@ architecture rtl of AxiStreamDmaV2Write is
100101
reqCount => (others => '0'),
101102
ackCount => (others => '0'),
102103
stCount => (others => '0'),
104+
timeoutCnt => (others => '0'),
103105
awlen => (others => '0'),
104106
axiLen => AXI_LEN_INIT_C,
105107
wMaster => axiWriteMasterInit(AXI_CONFIG_G, '1', "01", "0000"),
@@ -271,6 +273,7 @@ begin
271273
v.dmaWrTrack.metaAddr := dmaWrDescAck.metaAddr;
272274
v.dmaWrTrack.address := dmaWrDescAck.address;
273275
v.dmaWrTrack.maxSize := dmaWrDescAck.maxSize;
276+
v.dmaWrTrack.timeout := dmaWrDescAck.timeout;
274277

275278
-- Descriptor return calls for dumping frame?
276279
if dmaWrDescAck.dropEn = '1' then
@@ -464,6 +467,7 @@ begin
464467
v.dmaWrDescRet.id := r.dmaWrTrack.id;
465468
v.dmaWrDescRet.lastUser := r.lastUser;
466469
v.dmaWrDescRet.continue := r.continue;
470+
v.dmaWrDescRet.result(3) := '0';
467471
v.dmaWrDescRet.result(2) := r.dmaWrTrack.overflow;
468472
v.dmaWrDescRet.result(1 downto 0) := r.result;
469473
-- Init record
@@ -473,10 +477,11 @@ begin
473477
v.dmaWrDescRet.valid := '1';
474478
v.state := IDLE_S;
475479
-- Check for ACK timeout
476-
elsif (r.stCount = x"FFFF") then
480+
elsif (r.stCount = r.dmaWrTrack.timeout) then
477481
-- Set the flags
478482
v.dmaWrDescRet.result(1 downto 0) := "11";
479483
v.dmaWrDescRet.valid := '1';
484+
v.dmaWrDescRet.result(3) := '1';
480485
v.reqCount := (others => '0');
481486
v.ackCount := (others => '0');
482487
v.state := IDLE_S;

‎devices/Silabs/si5394/ruckus.tcl

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@@ -1,5 +1,5 @@
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# Load RUCKUS library
2-
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
2+
source $::env(RUCKUS_PROC_TCL)
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# Load Source Code
55
loadSource -lib surf -dir "$::DIR_PATH/rtl"

‎protocols/pgp/pgp2fc/core/ruckus.tcl

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@@ -1,5 +1,5 @@
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# Load RUCKUS library
2-
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
2+
source $::env(RUCKUS_PROC_TCL)
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# Load Source Code
55
loadSource -lib surf -dir "$::DIR_PATH/rtl"

‎protocols/pgp/pgp2fc/gtp7/ruckus.tcl

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@@ -1,5 +1,5 @@
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# Load RUCKUS library
2-
source -quiet $::env(RUCKUS_DIR)/vivado/proc.tcl
2+
source $::env(RUCKUS_PROC_TCL)
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# Load Source Code
55
loadSource -lib surf -dir "$::DIR_PATH/rtl"

‎protocols/pgp/pgp2fc/ruckus.tcl

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@@ -1,5 +1,5 @@
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# Load RUCKUS library
2-
source -quiet $::env(RUCKUS_DIR)/vivado_proc.tcl
2+
source $::env(RUCKUS_PROC_TCL)
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44
# Load the Core
55
loadRuckusTcl "$::DIR_PATH/core"

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