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Merge pull request #906 from slaclab/pre-release
Release Candidate v2.25.0
2 parents 54a146e + de06830 commit 8caa69a

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15 files changed

+155
-98
lines changed

15 files changed

+155
-98
lines changed

‎axi/axi-stream/rtl/AxiStreamMux.vhd

Lines changed: 49 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -26,36 +26,37 @@ use surf.AxiStreamPkg.all;
2626

2727
entity AxiStreamMux is
2828
generic (
29-
TPD_G : time := 1 ns;
30-
PIPE_STAGES_G : integer range 0 to 16 := 0;
31-
NUM_SLAVES_G : integer range 1 to 256 := 4;
29+
TPD_G : time := 1 ns;
30+
PIPE_STAGES_G : integer range 0 to 16 := 0;
31+
NUM_SLAVES_G : integer range 1 to 256 := 4;
3232
-- In INDEXED mode, the output TDEST is set based on the selected slave index (default)
3333
-- In ROUTED mode, TDEST is set according to the TDEST_ROUTES_G table
3434
-- In PASSTHROUGH mode, TDEST is passed through from the slave untouched
35-
MODE_G : string := "INDEXED"; -- Note: Planning to rename "MODE_G" to "TDEST_MODE_G" in a future MAJOR release of SURF
35+
MODE_G : string := "INDEXED"; -- Note: Planning to rename "MODE_G" to "TDEST_MODE_G" in a future MAJOR release of SURF
3636
-- In ROUTED mode, an array mapping how TDEST should be assigned for each slave port
3737
-- Each TDEST bit can be set to '0', '1' or '-' for passthrough from slave TDEST.
38-
TDEST_ROUTES_G : Slv8Array := (0 => "--------");
38+
TDEST_ROUTES_G : Slv8Array := (0 => "--------");
3939
-- In INDEXED mode, the output TID is set based on the selected slave index
4040
-- In ROUTED mode, TID is set according to the TID_ROUTES_G table
4141
-- In PASSTHROUGH mode, TID is passed through from the slave untouched (default)
42-
TID_MODE_G : string := "PASSTHROUGH";
42+
TID_MODE_G : string := "PASSTHROUGH";
4343
-- In ROUTED mode, an array mapping how TID should be assigned for each slave port
44-
TID_ROUTES_G : Slv8Array := (0 => "--------");
44+
TID_ROUTES_G : Slv8Array := (0 => "--------");
45+
PRIORITY_G : IntegerArray := (0 => 0);
4546
-- In INDEXED mode, assign slave index to TDEST at this bit offset
46-
TDEST_LOW_G : integer range 0 to 7 := 0;
47+
TDEST_LOW_G : integer range 0 to 7 := 0;
4748
-- Set to true if interleaving dests
48-
ILEAVE_EN_G : boolean := false;
49+
ILEAVE_EN_G : boolean := false;
4950
-- Rearbitrate when tValid drops on selected channel, ignored when ILEAVE_EN_G=false
50-
ILEAVE_ON_NOTVALID_G : boolean := false;
51+
ILEAVE_ON_NOTVALID_G : boolean := false;
5152
-- Max number of transactions between arbitrations, 0 = unlimited, ignored when ILEAVE_EN_G=false
52-
ILEAVE_REARB_G : natural range 0 to 4095 := 0;
53+
ILEAVE_REARB_G : natural range 0 to 4095 := 0;
5354
-- One cycle gap in stream between during re-arbitration.
5455
-- Set true for better timing, false for higher throughput.
55-
REARB_DELAY_G : boolean := true;
56+
REARB_DELAY_G : boolean := true;
5657
-- Block selected slave txns arriving on same cycle as rearbitrate or disableSel from going through,
5758
-- creating 1 cycle gap. This might be needed logically but decreases throughput.
58-
FORCED_REARB_HOLD_G : boolean := false);
59+
FORCED_REARB_HOLD_G : boolean := false);
5960

6061
port (
6162
-- Clock and reset
@@ -64,7 +65,7 @@ entity AxiStreamMux is
6465
-- Slaves
6566
disableSel : in slv(NUM_SLAVES_G-1 downto 0) := (others => '0');
6667
rearbitrate : in sl := '0';
67-
ileaveRearb : in slv(11 downto 0) := toSlv(ILEAVE_REARB_G,12);
68+
ileaveRearb : in slv(11 downto 0) := toSlv(ILEAVE_REARB_G, 12);
6869
sAxisMasters : in AxiStreamMasterArray(NUM_SLAVES_G-1 downto 0);
6970
sAxisSlaves : out AxiStreamSlaveArray(NUM_SLAVES_G-1 downto 0);
7071

@@ -102,27 +103,29 @@ architecture rtl of AxiStreamMux is
102103
signal pipeAxisMaster : AxiStreamMasterType;
103104
signal pipeAxisSlave : AxiStreamSlaveType;
104105

106+
signal intDisableSel : slv(NUM_SLAVES_G-1 downto 0);
107+
105108
begin
106109

107-
assert ( (MODE_G = "PASSTHROUGH") or (MODE_G = "INDEXED") or (MODE_G = "ROUTED") )
110+
assert ((MODE_G = "PASSTHROUGH") or (MODE_G = "INDEXED") or (MODE_G = "ROUTED"))
108111
report "MODE_G must be either [PASSTHROUGH,INDEXED,ROUTED]"
109112
severity error;
110113

111-
assert ( (MODE_G = "INDEXED") and (7 - TDEST_LOW_G + 1 >= log2(NUM_SLAVES_G)) ) or (MODE_G /= "INDEXED")
114+
assert ((MODE_G = "INDEXED") and (7 - TDEST_LOW_G + 1 >= log2(NUM_SLAVES_G))) or (MODE_G /= "INDEXED")
112115
report "In INDEXED mode, TDest range 7 downto " & integer'image(TDEST_LOW_G) &
113116
" is too small for NUM_SLAVES_G=" & integer'image(NUM_SLAVES_G)
114117
severity error;
115118

116-
assert ( (MODE_G = "ROUTED") and (TDEST_ROUTES_G'length = NUM_SLAVES_G) ) or (MODE_G /= "ROUTED")
119+
assert ((MODE_G = "ROUTED") and (TDEST_ROUTES_G'length = NUM_SLAVES_G)) or (MODE_G /= "ROUTED")
117120
report "In ROUTED mode, length of TDEST_ROUTES_G: " & integer'image(TDEST_ROUTES_G'length) &
118121
" must equal NUM_SLAVES_G: " & integer'image(NUM_SLAVES_G)
119122
severity error;
120123

121-
assert ( (TID_MODE_G = "PASSTHROUGH") or (TID_MODE_G = "INDEXED") or (TID_MODE_G = "ROUTED") )
124+
assert ((TID_MODE_G = "PASSTHROUGH") or (TID_MODE_G = "INDEXED") or (TID_MODE_G = "ROUTED"))
122125
report "TID_MODE_G must be either [PASSTHROUGH,INDEXED,ROUTED]"
123126
severity error;
124127

125-
assert ( (TID_MODE_G = "ROUTED") and (TID_ROUTES_G'length = NUM_SLAVES_G) ) or (TID_MODE_G /= "ROUTED")
128+
assert ((TID_MODE_G = "ROUTED") and (TID_ROUTES_G'length = NUM_SLAVES_G)) or (TID_MODE_G /= "ROUTED")
126129
report "In ROUTED mode, length of TID_ROUTES_G: " & integer'image(TID_ROUTES_G'length) &
127130
" must equal NUM_SLAVES_G: " & integer'image(NUM_SLAVES_G)
128131
severity error;
@@ -171,7 +174,31 @@ begin
171174

172175
end process;
173176

174-
comb : process (axisRst, disableSel, ileaveRearb, pipeAxisSlave, r, rearbitrate, sAxisMastersTmp) is
177+
-- When in INDEXED priority mode, tvalid on a given slave side index disables selection
178+
-- for all channels with higer index
179+
PRIORITY_CONTROL : process (disableSel, sAxisMasters) is
180+
variable tmp : slv(NUM_SLAVES_G-1 downto 0);
181+
begin
182+
tmp := disableSel;
183+
184+
for ch in NUM_SLAVES_G-1 downto 0 loop
185+
if (sAxisMasters(ch).tValid = '1') then
186+
if (ch < PRIORITY_G'length) then
187+
for sel in PRIORITY_G'range loop
188+
if (PRIORITY_G(ch) > PRIORITY_G(sel)) then
189+
tmp(sel) := '1';
190+
end if;
191+
end loop;
192+
end if;
193+
end if;
194+
end loop;
195+
196+
intDisableSel <= tmp;
197+
198+
end process PRIORITY_CONTROL;
199+
200+
comb : process (axisRst, ileaveRearb, intDisableSel, pipeAxisSlave, r, rearbitrate,
201+
sAxisMastersTmp) is
175202
variable v : RegType;
176203
variable requests : slv(ARB_BITS_C-1 downto 0);
177204
variable selData : AxiStreamMasterType;
@@ -223,15 +250,15 @@ begin
223250
-- Format requests
224251
requests := (others => '0');
225252
for i in 0 to (NUM_SLAVES_G-1) loop
226-
requests(i) := sAxisMastersTmp(i).tValid and not disableSel(i);
253+
requests(i) := sAxisMastersTmp(i).tValid and not intDisableSel(i);
227254
end loop;
228255

229256
if (r.valid = '1') then
230257
-- RE-arbitrate on gaps if configured to do so
231258
-- Also allow disableSel and rearbitrate to work at any time
232259
if (ILEAVE_EN_G) then
233260
if ((ILEAVE_ON_NOTVALID_G and selData.tValid = '0') or
234-
(rearbitrate = '1' or disableSel(conv_integer(r.ackNum)) = '1')) then
261+
(rearbitrate = '1' or intDisableSel(conv_integer(r.ackNum)) = '1')) then
235262
v.valid := '0';
236263
end if;
237264
end if;

‎ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ begin
6666
PwrUpRst_Inst : entity surf.PwrUpRst
6767
generic map (
6868
TPD_G => TPD_G,
69-
DURATION_G => 15625000) -- 100 ms
69+
DURATION_G => 156250000) -- 1000 ms
7070
port map (
7171
arst => extRst,
7272
clk => phyClock,
@@ -110,14 +110,14 @@ begin
110110
QPLL_CFG_G => x"04801C7",
111111
QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_C,
112112
QPLL_FBDIV_G => "0101000000", -- 64B/66B Encoding
113-
QPLL_FBDIV_RATIO_G => '0', -- 64B/66B Encoding
113+
QPLL_FBDIV_RATIO_G => '0', -- 64B/66B Encoding
114114
QPLL_REFCLK_DIV_G => 1)
115115
port map (
116-
qPllRefClk => refClk, -- 156.25 MHz
116+
qPllRefClk => refClk, -- 156.25 MHz
117117
qPllOutClk => qPllOutClk,
118118
qPllOutRefClk => qPllOutRefClk,
119119
qPllLock => qPllLock,
120-
qPllLockDetClk => '0', -- IP Core ties this to GND (see note below)
120+
qPllLockDetClk => '0', -- IP Core ties this to GND (see note below)
121121
qPllRefClkLost => open,
122122
qPllPowerDown => '0',
123123
qPllReset => qpllReset);

‎ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleWrapper.vhd

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ begin
102102
PwrUpRst_Inst : entity surf.PwrUpRst
103103
generic map (
104104
TPD_G => TPD_G,
105-
DURATION_G => 15625000) -- 100 ms
105+
DURATION_G => 156250000) -- 1000 ms
106106
port map (
107107
arst => extRst,
108108
clk => coreClock,
@@ -142,12 +142,12 @@ begin
142142

143143
TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale
144144
generic map (
145-
TPD_G => TPD_G,
146-
PAUSE_EN_G => PAUSE_EN_G,
145+
TPD_G => TPD_G,
146+
PAUSE_EN_G => PAUSE_EN_G,
147147
-- AXI-Lite Configurations
148-
EN_AXI_REG_G => EN_AXI_REG_G,
148+
EN_AXI_REG_G => EN_AXI_REG_G,
149149
-- AXI Streaming Configurations
150-
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
150+
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
151151
port map (
152152
-- Local Configurations
153153
localMac => localMac(i),

‎ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleWrapper.vhd

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -106,7 +106,7 @@ begin
106106
PwrUpRst_Inst : entity surf.PwrUpRst
107107
generic map (
108108
TPD_G => TPD_G,
109-
DURATION_G => 15625000) -- 100 ms
109+
DURATION_G => 156250000) -- 1000 ms
110110
port map (
111111
arst => extRst,
112112
clk => coreClock,
@@ -145,12 +145,12 @@ begin
145145

146146
TenGigEthGthUltraScale_Inst : entity surf.TenGigEthGthUltraScale
147147
generic map (
148-
TPD_G => TPD_G,
149-
PAUSE_EN_G => PAUSE_EN_G,
148+
TPD_G => TPD_G,
149+
PAUSE_EN_G => PAUSE_EN_G,
150150
-- AXI-Lite Configurations
151-
EN_AXI_REG_G => EN_AXI_REG_G,
151+
EN_AXI_REG_G => EN_AXI_REG_G,
152152
-- AXI Streaming Configurations
153-
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
153+
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
154154
port map (
155155
-- Local Configurations
156156
localMac => localMac(i),

‎ethernet/TenGigEthCore/gtx7/rtl/TenGigEthGtx7Clk.vhd

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ begin
6868
PwrUpRst_Inst : entity surf.PwrUpRst
6969
generic map (
7070
TPD_G => TPD_G,
71-
DURATION_G => 15625000) -- 100 ms
71+
DURATION_G => 156250000) -- 1000 ms
7272
port map (
7373
arst => extRst,
7474
clk => phyClock,
@@ -110,14 +110,14 @@ begin
110110
QPLL_CFG_G => x"0680181",
111111
QPLL_REFCLK_SEL_G => QPLL_REFCLK_SEL_C,
112112
QPLL_FBDIV_G => "0101000000", -- 64B/66B Encoding
113-
QPLL_FBDIV_RATIO_G => '0', -- 64B/66B Encoding
113+
QPLL_FBDIV_RATIO_G => '0', -- 64B/66B Encoding
114114
QPLL_REFCLK_DIV_G => 1)
115115
port map (
116-
qPllRefClk => refClk, -- 156.25 MHz
116+
qPllRefClk => refClk, -- 156.25 MHz
117117
qPllOutClk => qPllOutClk,
118118
qPllOutRefClk => qPllOutRefClk,
119119
qPllLock => qPllLock,
120-
qPllLockDetClk => '0', -- IP Core ties this to GND (see note below)
120+
qPllLockDetClk => '0', -- IP Core ties this to GND (see note below)
121121
qPllRefClkLost => open,
122122
qPllPowerDown => '0',
123123
qPllReset => qpllReset);

‎ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleWrapper.vhd

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -101,7 +101,7 @@ begin
101101
PwrUpRst_Inst : entity surf.PwrUpRst
102102
generic map (
103103
TPD_G => TPD_G,
104-
DURATION_G => 15625000) -- 100 ms
104+
DURATION_G => 156250000) -- 1000 ms
105105
port map (
106106
arst => extRst,
107107
clk => coreClock,
@@ -139,12 +139,12 @@ begin
139139

140140
TenGigEthGtyUltraScale_Inst : entity surf.TenGigEthGtyUltraScale
141141
generic map (
142-
TPD_G => TPD_G,
143-
PAUSE_EN_G => PAUSE_EN_G,
142+
TPD_G => TPD_G,
143+
PAUSE_EN_G => PAUSE_EN_G,
144144
-- AXI-Lite Configurations
145-
EN_AXI_REG_G => EN_AXI_REG_G,
145+
EN_AXI_REG_G => EN_AXI_REG_G,
146146
-- AXI Streaming Configurations
147-
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
147+
AXIS_CONFIG_G => AXIS_CONFIG_G(i))
148148
port map (
149149
-- Local Configurations
150150
localMac => localMac(i),

‎protocols/rssi/v1/rtl/RssiCoreWrapper.vhd

Lines changed: 32 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -29,41 +29,42 @@ use surf.AxiLitePkg.all;
2929

3030
entity RssiCoreWrapper is
3131
generic (
32-
TPD_G : time := 1 ns;
33-
CLK_FREQUENCY_G : real := 156.25E+6; -- In units of Hz
34-
TIMEOUT_UNIT_G : real := 1.0E-3; -- In units of seconds
35-
SERVER_G : boolean := true; -- Module is server or client
36-
RETRANSMIT_ENABLE_G : boolean := true; -- Enable/Disable retransmissions in tx module
37-
WINDOW_ADDR_SIZE_G : positive := 3; -- 2^WINDOW_ADDR_SIZE_G = Max number of segments in buffer
38-
SEGMENT_ADDR_SIZE_G : positive := 7; -- Unused (legacy generic)
39-
BYPASS_CHUNKER_G : boolean := false; -- Bypass the AXIS chunker layer
40-
PIPE_STAGES_G : natural := 0;
41-
APP_STREAMS_G : positive := 1;
42-
APP_STREAM_ROUTES_G : Slv8Array := (0 => "--------");
43-
APP_ILEAVE_EN_G : boolean := false;
44-
BYP_TX_BUFFER_G : boolean := false;
45-
BYP_RX_BUFFER_G : boolean := false;
46-
SYNTH_MODE_G : string := "inferred";
47-
MEMORY_TYPE_G : string := "block";
48-
ILEAVE_ON_NOTVALID_G : boolean := false; -- Unused (legacy generic)
32+
TPD_G : time := 1 ns;
33+
CLK_FREQUENCY_G : real := 156.25E+6; -- In units of Hz
34+
TIMEOUT_UNIT_G : real := 1.0E-3; -- In units of seconds
35+
SERVER_G : boolean := true; -- Module is server or client
36+
RETRANSMIT_ENABLE_G : boolean := true; -- Enable/Disable retransmissions in tx module
37+
WINDOW_ADDR_SIZE_G : positive := 3; -- 2^WINDOW_ADDR_SIZE_G = Max number of segments in buffer
38+
SEGMENT_ADDR_SIZE_G : positive := 7; -- Unused (legacy generic)
39+
BYPASS_CHUNKER_G : boolean := false; -- Bypass the AXIS chunker layer
40+
PIPE_STAGES_G : natural := 0;
41+
APP_STREAMS_G : positive := 1;
42+
APP_STREAM_ROUTES_G : Slv8Array := (0 => "--------");
43+
APP_STREAM_PRIORITY_G : IntegerArray := (0 => 0); -- Determines priority of outbound streams
44+
APP_ILEAVE_EN_G : boolean := false;
45+
BYP_TX_BUFFER_G : boolean := false;
46+
BYP_RX_BUFFER_G : boolean := false;
47+
SYNTH_MODE_G : string := "inferred";
48+
MEMORY_TYPE_G : string := "block";
49+
ILEAVE_ON_NOTVALID_G : boolean := false; -- Unused (legacy generic)
4950
-- AXIS Configurations
50-
APP_AXIS_CONFIG_G : AxiStreamConfigArray;
51-
TSP_AXIS_CONFIG_G : AxiStreamConfigType;
51+
APP_AXIS_CONFIG_G : AxiStreamConfigArray;
52+
TSP_AXIS_CONFIG_G : AxiStreamConfigType;
5253
-- Version and connection ID
53-
INIT_SEQ_N_G : natural := 16#80#;
54-
CONN_ID_G : positive := 16#12345678#;
55-
VERSION_G : positive := 1;
56-
HEADER_CHKSUM_EN_G : boolean := true;
54+
INIT_SEQ_N_G : natural := 16#80#;
55+
CONN_ID_G : positive := 16#12345678#;
56+
VERSION_G : positive := 1;
57+
HEADER_CHKSUM_EN_G : boolean := true;
5758
-- Window parameters of receiver module
58-
MAX_NUM_OUTS_SEG_G : positive := 8; -- Unused (legacy generic)
59-
MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes
59+
MAX_NUM_OUTS_SEG_G : positive := 8; -- Unused (legacy generic)
60+
MAX_SEG_SIZE_G : positive := 1024; -- <= (2**SEGMENT_ADDR_SIZE_G)*8 Number of bytes
6061
-- RSSI Timeouts
61-
ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G
62-
RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time)
63-
NULL_TOUT_G : positive := 200; -- unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G)
62+
ACK_TOUT_G : positive := 25; -- unit depends on TIMEOUT_UNIT_G
63+
RETRANS_TOUT_G : positive := 50; -- unit depends on TIMEOUT_UNIT_G (Recommended >= MAX_NUM_OUTS_SEG_G*Data segment transmission time)
64+
NULL_TOUT_G : positive := 200; -- unit depends on TIMEOUT_UNIT_G (Recommended >= 4*RETRANS_TOUT_G)
6465
-- Counters
65-
MAX_RETRANS_CNT_G : positive := 2;
66-
MAX_CUM_ACK_CNT_G : positive := 3);
66+
MAX_RETRANS_CNT_G : positive := 2;
67+
MAX_CUM_ACK_CNT_G : positive := 3);
6768
port (
6869
-- Clock and Reset
6970
clk_i : in sl;
@@ -182,6 +183,7 @@ begin
182183
NUM_SLAVES_G => APP_STREAMS_G,
183184
MODE_G => "ROUTED",
184185
TDEST_ROUTES_G => APP_STREAM_ROUTES_G,
186+
PRIORITY_G => APP_STREAM_PRIORITY_G,
185187
ILEAVE_EN_G => APP_ILEAVE_EN_G,
186188
ILEAVE_ON_NOTVALID_G => true, -- Because of ILEAVE_REARB_G value != power of 2, forcing rearb on not(tValid)
187189
ILEAVE_REARB_G => (MAX_SEG_SIZE_G/CONV_AXIS_CONFIG_C.TDATA_BYTES_C) - 3, -- AxiStreamPacketizer2.PROTO_WORDS_C=3

‎protocols/ssp/rtl/SspLowSpeedDecoder10b12bWrapper.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ architecture mapping of SspLowSpeedDecoder10b12bWrapper is
5757
signal dlyConfig : Slv9Array(NUM_LANE_G-1 downto 0);
5858

5959
signal enUsrDlyCfg : sl;
60-
signal usrDlyCfg : slv(8 downto 0);
60+
signal usrDlyCfg : Slv9Array(NUM_LANE_G-1 downto 0);
6161
signal minEyeWidth : slv(7 downto 0);
6262
signal lockingCntCfg : slv(23 downto 0);
6363
signal bypFirstBerDet : sl;
@@ -93,7 +93,7 @@ begin
9393
dlyCfg => dlyConfig(i),
9494
-- Config/Status Interface
9595
enUsrDlyCfg => enUsrDlyCfg,
96-
usrDlyCfg => usrDlyCfg,
96+
usrDlyCfg => usrDlyCfg(i),
9797
minEyeWidth => minEyeWidth,
9898
lockingCntCfg => lockingCntCfg,
9999
bypFirstBerDet => bypFirstBerDet,

‎protocols/ssp/rtl/SspLowSpeedDecoder12b14bWrapper.vhd

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ architecture mapping of SspLowSpeedDecoder12b14bWrapper is
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signal dlyConfig : Slv9Array(NUM_LANE_G-1 downto 0);
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signal enUsrDlyCfg : sl;
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signal usrDlyCfg : slv(8 downto 0);
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signal usrDlyCfg : Slv9Array(NUM_LANE_G-1 downto 0);
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signal minEyeWidth : slv(7 downto 0);
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signal lockingCntCfg : slv(23 downto 0);
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signal bypFirstBerDet : sl;
@@ -93,7 +93,7 @@ begin
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dlyCfg => dlyConfig(i),
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-- Config/Status Interface
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enUsrDlyCfg => enUsrDlyCfg,
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usrDlyCfg => usrDlyCfg,
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usrDlyCfg => usrDlyCfg(i),
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minEyeWidth => minEyeWidth,
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lockingCntCfg => lockingCntCfg,
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bypFirstBerDet => bypFirstBerDet,

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